aboutsummaryrefslogtreecommitdiff
path: root/drivers/media/video/cx18/cx18-io.c
diff options
context:
space:
mode:
authorAndy Walls <awalls@radix.net>2008-09-28 21:46:02 -0300
committerMauro Carvalho Chehab <mchehab@redhat.com>2008-10-12 09:37:14 -0200
commitd267d85101c509020a12686b96cbd179deaf4ecd (patch)
tree1a016966d11efb400ca310cd5726478053cd00a0 /drivers/media/video/cx18/cx18-io.c
parent7f9876785276ac7f8606f8bf53a3dae4c10b8adb (diff)
V4L/DVB (9110): cx18: Add default behavior of checking and retrying PCI MMIO accesses
cx18: Add default behavior of checking and retrying PCI MMIO accesses. The concept of checking and retrying PCI MMIO accesses for better reliability in older motherboards was suggested by Steve Toth <stoth@linuxtv.org>. This change implements MMIO retries and the retry_mmio module parameter that is enabled by default. Limited experiments have shown this is more reliable than the mmio_ndelay parameter. mmio_ndelay has insignificant effect with retries enabled. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video/cx18/cx18-io.c')
-rw-r--r--drivers/media/video/cx18/cx18-io.c135
1 files changed, 125 insertions, 10 deletions
diff --git a/drivers/media/video/cx18/cx18-io.c b/drivers/media/video/cx18/cx18-io.c
index 55d1df93292..700ab9439c1 100644
--- a/drivers/media/video/cx18/cx18-io.c
+++ b/drivers/media/video/cx18/cx18-io.c
@@ -24,6 +24,131 @@
#include "cx18-io.h"
#include "cx18-irq.h"
+void cx18_log_statistics(struct cx18 *cx)
+{
+ int i;
+
+ if (!(cx18_debug & CX18_DBGFLG_INFO))
+ return;
+
+ for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++)
+ CX18_DEBUG_INFO("retried_write[%d] = %d\n", i,
+ atomic_read(&cx->mmio_stats.retried_write[i]));
+ for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++)
+ CX18_DEBUG_INFO("retried_read[%d] = %d\n", i,
+ atomic_read(&cx->mmio_stats.retried_read[i]));
+ return;
+}
+
+void cx18_raw_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
+{
+ int i;
+ for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ cx18_raw_writel_noretry(cx, val, addr);
+ if (val == cx18_raw_readl_noretry(cx, addr))
+ break;
+ }
+ cx18_log_write_retries(cx, i, addr);
+}
+
+u32 cx18_raw_readl_retry(struct cx18 *cx, const void __iomem *addr)
+{
+ int i;
+ u32 val;
+ for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ val = cx18_raw_readl_noretry(cx, addr);
+ if (val != 0xffffffff) /* PCI bus read error */
+ break;
+ }
+ cx18_log_read_retries(cx, i, addr);
+ return val;
+}
+
+u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr)
+{
+ int i;
+ u16 val;
+ for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ val = cx18_raw_readw_noretry(cx, addr);
+ if (val != 0xffff) /* PCI bus read error */
+ break;
+ }
+ cx18_log_read_retries(cx, i, addr);
+ return val;
+}
+
+void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
+{
+ int i;
+ for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ cx18_writel_noretry(cx, val, addr);
+ if (val == cx18_readl_noretry(cx, addr))
+ break;
+ }
+ cx18_log_write_retries(cx, i, addr);
+}
+
+void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr)
+{
+ int i;
+ for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ cx18_writew_noretry(cx, val, addr);
+ if (val == cx18_readw_noretry(cx, addr))
+ break;
+ }
+ cx18_log_write_retries(cx, i, addr);
+}
+
+void cx18_writeb_retry(struct cx18 *cx, u8 val, void __iomem *addr)
+{
+ int i;
+ for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ cx18_writeb_noretry(cx, val, addr);
+ if (val == cx18_readb_noretry(cx, addr))
+ break;
+ }
+ cx18_log_write_retries(cx, i, addr);
+}
+
+u32 cx18_readl_retry(struct cx18 *cx, const void __iomem *addr)
+{
+ int i;
+ u32 val;
+ for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ val = cx18_readl_noretry(cx, addr);
+ if (val != 0xffffffff) /* PCI bus read error */
+ break;
+ }
+ cx18_log_read_retries(cx, i, addr);
+ return val;
+}
+
+u16 cx18_readw_retry(struct cx18 *cx, const void __iomem *addr)
+{
+ int i;
+ u16 val;
+ for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ val = cx18_readw_noretry(cx, addr);
+ if (val != 0xffff) /* PCI bus read error */
+ break;
+ }
+ cx18_log_read_retries(cx, i, addr);
+ return val;
+}
+
+u8 cx18_readb_retry(struct cx18 *cx, const void __iomem *addr)
+{
+ int i;
+ u8 val;
+ for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ val = cx18_readb_noretry(cx, addr);
+ if (val != 0xff) /* PCI bus read error */
+ break;
+ }
+ cx18_log_read_retries(cx, i, addr);
+ return val;
+}
+
void cx18_memcpy_fromio(struct cx18 *cx, void *to,
const void __iomem *from, unsigned int len)
{
@@ -127,13 +252,3 @@ void cx18_setup_page(struct cx18 *cx, u32 addr)
val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00);
cx18_write_reg(cx, val, 0xD000F8);
}
-
-/* Tries to recover from the CX23418 responding improperly on the PCI bus */
-int cx18_pci_try_recover(struct cx18 *cx)
-{
- u16 status;
-
- pci_read_config_word(cx->dev, PCI_STATUS, &status);
- pci_write_config_word(cx->dev, PCI_STATUS, status);
- return 0;
-}