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authorDivy Le Ray <divy@chelsio.com>2007-05-30 21:10:58 -0700
committerJeff Garzik <jeff@garzik.org>2007-07-08 22:16:39 -0400
commit480fe1a31c662ef4ff0598a7cacefa21f98335f1 (patch)
tree66da8f259d7093d7f9290054f4fbda1f68ff9e0a /drivers/net/cxgb3/l2t.c
parent8a9fab22cf6a3abde7731f4425d4ff87509bc15a (diff)
cxgb3 - TP SRAM update
The chip executes microcode present in internal RAM, whose content is loaded from EEPROM on power cycle. This patch allows an update of the microcode through PIO without forcing a power cycle. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/cxgb3/l2t.c')
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