diff options
author | Dave Airlie <airlied@redhat.com> | 2009-03-28 20:22:18 -0400 |
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committer | Dave Airlie <airlied@redhat.com> | 2009-03-28 20:22:18 -0400 |
commit | 90f959bcb386da2c71613dcefc6a285e054a539e (patch) | |
tree | ee3e9dd4111d4aad12e579cb0c2c159114dff263 /drivers/net/sfc/xfp_phy.c | |
parent | 41f13fe81dd1b08723ab9f3fc3c7f29cfa81f1a5 (diff) | |
parent | 07d43ba98621f08e252a48c96b258b4d572b0257 (diff) |
drm: merge Linux master into HEAD
Conflicts:
drivers/gpu/drm/drm_info.c
drivers/gpu/drm/drm_proc.c
drivers/gpu/drm/i915/i915_gem_debugfs.c
Diffstat (limited to 'drivers/net/sfc/xfp_phy.c')
-rw-r--r-- | drivers/net/sfc/xfp_phy.c | 105 |
1 files changed, 92 insertions, 13 deletions
diff --git a/drivers/net/sfc/xfp_phy.c b/drivers/net/sfc/xfp_phy.c index 2d50b6ecf5f..bb1ef77d5f5 100644 --- a/drivers/net/sfc/xfp_phy.c +++ b/drivers/net/sfc/xfp_phy.c @@ -7,8 +7,8 @@ * by the Free Software Foundation, incorporated herein by reference. */ /* - * Driver for XFP optical PHYs (plus some support specific to the Quake 2022/32) - * See www.amcc.com for details (search for qt2032) + * Driver for SFP+ and XFP optical PHYs plus some support specific to the + * AMCC QT20xx adapters; see www.amcc.com for details */ #include <linux/timer.h> @@ -31,6 +31,21 @@ /* Quake-specific MDIO registers */ #define MDIO_QUAKE_LED0_REG (0xD006) +/* QT2025C only */ +#define PCS_FW_HEARTBEAT_REG 0xd7ee +#define PCS_FW_HEARTB_LBN 0 +#define PCS_FW_HEARTB_WIDTH 8 +#define PCS_UC8051_STATUS_REG 0xd7fd +#define PCS_UC_STATUS_LBN 0 +#define PCS_UC_STATUS_WIDTH 8 +#define PCS_UC_STATUS_FW_SAVE 0x20 +#define PMA_PMD_FTX_CTRL2_REG 0xc309 +#define PMA_PMD_FTX_STATIC_LBN 13 +#define PMA_PMD_VEND1_REG 0xc001 +#define PMA_PMD_VEND1_LBTXD_LBN 15 +#define PCS_VEND1_REG 0xc000 +#define PCS_VEND1_LBTXD_LBN 5 + void xfp_set_led(struct efx_nic *p, int led, int mode) { int addr = MDIO_QUAKE_LED0_REG + led; @@ -45,7 +60,49 @@ struct xfp_phy_data { #define XFP_MAX_RESET_TIME 500 #define XFP_RESET_WAIT 10 -/* Reset the PHYXS MMD. This is documented (for the Quake PHY) as doing +static int qt2025c_wait_reset(struct efx_nic *efx) +{ + unsigned long timeout = jiffies + 10 * HZ; + int phy_id = efx->mii.phy_id; + int reg, old_counter = 0; + + /* Wait for firmware heartbeat to start */ + for (;;) { + int counter; + reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS, + PCS_FW_HEARTBEAT_REG); + if (reg < 0) + return reg; + counter = ((reg >> PCS_FW_HEARTB_LBN) & + ((1 << PCS_FW_HEARTB_WIDTH) - 1)); + if (old_counter == 0) + old_counter = counter; + else if (counter != old_counter) + break; + if (time_after(jiffies, timeout)) + return -ETIMEDOUT; + msleep(10); + } + + /* Wait for firmware status to look good */ + for (;;) { + reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS, + PCS_UC8051_STATUS_REG); + if (reg < 0) + return reg; + if ((reg & + ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >= + PCS_UC_STATUS_FW_SAVE) + break; + if (time_after(jiffies, timeout)) + return -ETIMEDOUT; + msleep(100); + } + + return 0; +} + +/* Reset the PHYXS MMD. This is documented (for the Quake PHYs) as doing * a complete soft reset. */ static int xfp_reset_phy(struct efx_nic *efx) @@ -58,6 +115,12 @@ static int xfp_reset_phy(struct efx_nic *efx) if (rc < 0) goto fail; + if (efx->phy_type == PHY_TYPE_QT2025C) { + rc = qt2025c_wait_reset(efx); + if (rc < 0) + goto fail; + } + /* Wait 250ms for the PHY to complete bootup */ msleep(250); @@ -73,7 +136,7 @@ static int xfp_reset_phy(struct efx_nic *efx) return rc; fail: - EFX_ERR(efx, "XFP: reset timed out!\n"); + EFX_ERR(efx, "PHY reset timed out\n"); return rc; } @@ -88,15 +151,15 @@ static int xfp_phy_init(struct efx_nic *efx) return -ENOMEM; efx->phy_data = phy_data; - EFX_INFO(efx, "XFP: PHY ID reg %x (OUI %x model %x revision" - " %x)\n", devid, MDIO_ID_OUI(devid), MDIO_ID_MODEL(devid), - MDIO_ID_REV(devid)); + EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n", + devid, mdio_id_oui(devid), mdio_id_model(devid), + mdio_id_rev(devid)); phy_data->phy_mode = efx->phy_mode; rc = xfp_reset_phy(efx); - EFX_INFO(efx, "XFP: PHY init %s.\n", + EFX_INFO(efx, "PHY init %s.\n", rc ? "failed" : "successful"); if (rc < 0) goto fail; @@ -131,12 +194,28 @@ static void xfp_phy_reconfigure(struct efx_nic *efx) { struct xfp_phy_data *phy_data = efx->phy_data; - /* Reset the PHY when moving from tx off to tx on */ - if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) && - (phy_data->phy_mode & PHY_MODE_TX_DISABLED)) - xfp_reset_phy(efx); + if (efx->phy_type == PHY_TYPE_QT2025C) { + /* There are several different register bits which can + * disable TX (and save power) on direct-attach cables + * or optical transceivers, varying somewhat between + * firmware versions. Only 'static mode' appears to + * cover everything. */ + mdio_clause45_set_flag( + efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, + PMA_PMD_FTX_CTRL2_REG, PMA_PMD_FTX_STATIC_LBN, + efx->phy_mode & PHY_MODE_TX_DISABLED || + efx->phy_mode & PHY_MODE_LOW_POWER || + efx->loopback_mode == LOOPBACK_PCS || + efx->loopback_mode == LOOPBACK_PMAPMD); + } else { + /* Reset the PHY when moving from tx off to tx on */ + if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) && + (phy_data->phy_mode & PHY_MODE_TX_DISABLED)) + xfp_reset_phy(efx); + + mdio_clause45_transmit_disable(efx); + } - mdio_clause45_transmit_disable(efx); mdio_clause45_phy_reconfigure(efx); phy_data->phy_mode = efx->phy_mode; |