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| author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-12-03 08:15:08 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-12-03 08:15:08 -0800 |
| commit | e87cb5db0dc357473ac71801051954ddd6ff604f (patch) | |
| tree | e901e2ed972dfe81af6a61cfb3424d94bad13b82 /drivers/net/sky2.h | |
| parent | d894f4510d2155f9136c8c1bb91912481329f6e0 (diff) | |
| parent | 9ec46c6dae343688ff1136a0899b6a3c5e95e44b (diff) | |
Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/netdev-2.6
* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/netdev-2.6: (48 commits)
LIB82596: correct data types for hardware addresses
via-velocity: don't oops on MTU change (resend)
Stop phy code from returning success to unknown ioctls.
SET_NETDEV_DEV() in fec_mpc52xx.c
net: smc911x: only enable for mpr2 on sh.
e1000: Fix NAPI state bug when Rx complete
sky2: turn of dynamic Tx watermark workaround (FE+ only)
sky2: don't use AER routines
sky2: revert to access PCI config via device space
cxgb - fix stats
cxgb - fix NAPI
cxgb - fix T2 GSO
ucc_geth: handle passing of RX-only and TX-only internal delay PHY connection type parameters
phylib: marvell: add support for TX-only and RX-only Internal Delay
phylib: add PHY interface modes for internal delay for tx and rx only
skge: MTU changing fix
skge: serial mode register values
skge version 1.13
skge: increase TX threshold for Jumbo
skge: fiber link up/down fix
...
Diffstat (limited to 'drivers/net/sky2.h')
| -rw-r--r-- | drivers/net/sky2.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h index 69525fd7908..bc646a47edd 100644 --- a/drivers/net/sky2.h +++ b/drivers/net/sky2.h @@ -2128,4 +2128,25 @@ static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg, gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8)); gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8)); } + +/* PCI config space access */ +static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg) +{ + return sky2_read32(hw, Y2_CFG_SPC + reg); +} + +static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg) +{ + return sky2_read16(hw, Y2_CFG_SPC + reg); +} + +static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val) +{ + sky2_write32(hw, Y2_CFG_SPC + reg, val); +} + +static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val) +{ + sky2_write16(hw, Y2_CFG_SPC + reg, val); +} #endif |