diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 14:32:24 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 14:32:24 -0700 |
| commit | a348a7e6fdbcd2d5192a09719a479bb238fde727 (patch) | |
| tree | 5ff94185f4e5a810777469d7fe7832a8ec2d3430 /drivers/net/ucc_geth.h | |
| parent | 808347f6a31792079e345ec865e9cfcb6e8ae6b2 (diff) | |
| parent | 28d0325ce6e0a52f53d8af687e6427fee59004d3 (diff) | |
Merge commit 'v2.6.31-rc1' into dmaengine
Diffstat (limited to 'drivers/net/ucc_geth.h')
| -rw-r--r-- | drivers/net/ucc_geth.h | 35 |
1 files changed, 30 insertions, 5 deletions
diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h index 2f8ee7c87ef..195ab267ead 100644 --- a/drivers/net/ucc_geth.h +++ b/drivers/net/ucc_geth.h @@ -1,5 +1,5 @@ /* - * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved. + * Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved. * * Author: Shlomi Gridish <gridish@freescale.com> * @@ -193,6 +193,31 @@ struct ucc_geth { #define ENET_TBI_MII_JD 0x10 /* Jitter diagnostics */ #define ENET_TBI_MII_TBICON 0x11 /* TBI control */ +/* TBI MDIO register bit fields*/ +#define TBISR_LSTATUS 0x0004 +#define TBICON_CLK_SELECT 0x0020 +#define TBIANA_ASYMMETRIC_PAUSE 0x0100 +#define TBIANA_SYMMETRIC_PAUSE 0x0080 +#define TBIANA_HALF_DUPLEX 0x0040 +#define TBIANA_FULL_DUPLEX 0x0020 +#define TBICR_PHY_RESET 0x8000 +#define TBICR_ANEG_ENABLE 0x1000 +#define TBICR_RESTART_ANEG 0x0200 +#define TBICR_FULL_DUPLEX 0x0100 +#define TBICR_SPEED1_SET 0x0040 + +#define TBIANA_SETTINGS ( \ + TBIANA_ASYMMETRIC_PAUSE \ + | TBIANA_SYMMETRIC_PAUSE \ + | TBIANA_FULL_DUPLEX \ + ) +#define TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */ #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */ @@ -852,7 +877,6 @@ struct ucc_geth_hardware_statistics { /* Driver definitions */ #define TX_BD_RING_LEN 0x10 #define RX_BD_RING_LEN 0x10 -#define UCC_GETH_DEV_WEIGHT TX_BD_RING_LEN #define TX_RING_MOD_MASK(size) (size-1) #define RX_RING_MOD_MASK(size) (size-1) @@ -1100,7 +1124,8 @@ struct ucc_geth_info { u32 eventRegMask; u16 pausePeriod; u16 extensionField; - char phy_bus_id[BUS_ID_SIZE]; + struct device_node *phy_node; + struct device_node *tbi_node; u8 weightfactor[NUM_TX_QUEUES]; u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES]; u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX]; @@ -1120,8 +1145,8 @@ struct ucc_geth_info { enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc; enum ucc_geth_num_of_threads numThreadsTx; enum ucc_geth_num_of_threads numThreadsRx; - enum qe_risc_allocation riscTx; - enum qe_risc_allocation riscRx; + unsigned int riscTx; + unsigned int riscRx; }; /* structure representing UCC GETH */ |