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authorSujith <Sujith.Manoharan@atheros.com>2009-02-12 10:06:43 +0530
committerJohn W. Linville <linville@tuxdriver.com>2009-02-27 14:51:43 -0500
commitfec0de1110e58ed39647e484bff8437e4185158d (patch)
tree61c7af7a434c92d3ef0d2423b1150744adf9dbc3 /drivers/net/wireless/ath9k/eeprom.h
parente421c7b35c17752dbe6d26d910eb2d6814073355 (diff)
ath9k: Fix rd_ext EEPROM capability for AR9285
AR9285 chipsets have a different EEPROM layout, handle this appropriately when populating the rd_ext capability. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k/eeprom.h')
-rw-r--r--drivers/net/wireless/ath9k/eeprom.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h
index b7c656c84ba..5c0d6c339fe 100644
--- a/drivers/net/wireless/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath9k/eeprom.h
@@ -78,6 +78,18 @@
#define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
#define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
+/*
+ * For AR9285 and later chipsets, the following bits are not being programmed
+ * in EEPROM and so need to be enabled always.
+ *
+ * Bit 0: en_fcc_mid
+ * Bit 1: en_jap_mid
+ * Bit 2: en_fcc_dfs_ht40
+ * Bit 3: en_jap_ht40
+ * Bit 4: en_jap_dfs_ht40
+ */
+#define AR9285_RDEXT_DEFAULT 0x1F
+
#define AR_EEPROM_MAC(i) (0x1d+(i))
#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))