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authorHaiying Wang <Haiying.Wang@freescale.com>2009-06-02 04:04:14 +0000
committerDavid S. Miller <davem@davemloft.net>2009-06-03 02:52:46 -0700
commitfbcc0e2ce5a4fde63c7f33153bd7e3a4791e01c8 (patch)
tree4d73a04e7265788a47a9bbf7981ceeadc25e761b /drivers/net
parent32d0c1e1bee16781e94c7ea8c75499696bce0a33 (diff)
fsl_pq_mido: Set the first UCC as the mii management interface master
Current code makes the UCC whose register range includes the current mdio register to be the MII managemnt interface master of the QE. If there is more than one mdio bus for QE, the UCC of the last mdio bus will be the MII management interface master which will make the primary mdio bus working unproperly, e.g. can not get the right clock. Normally the primary mdio bus is the first UEC's mdio bus. This patch allows the first UCC to be the MII management interface master of the multiple UCC mdio buses. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/fsl_pq_mdio.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/net/fsl_pq_mdio.c b/drivers/net/fsl_pq_mdio.c
index d12e0e0336f..3af581303ca 100644
--- a/drivers/net/fsl_pq_mdio.c
+++ b/drivers/net/fsl_pq_mdio.c
@@ -301,13 +301,17 @@ static int fsl_pq_mdio_probe(struct of_device *ofdev,
of_device_is_compatible(np, "ucc_geth_phy")) {
#ifdef CONFIG_UCC_GETH
u32 id;
+ static u32 mii_mng_master;
tbipa = &regs->utbipar;
if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
goto err_free_irqs;
- ucc_set_qe_mux_mii_mng(id - 1);
+ if (!mii_mng_master) {
+ mii_mng_master = id;
+ ucc_set_qe_mux_mii_mng(id - 1);
+ }
#else
err = -ENODEV;
goto err_free_irqs;