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authorAndres Salomon <dilinger@collabora.co.uk>2010-02-05 01:42:43 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2010-02-05 07:36:50 -0800
commit73d2eaac8a3f1ec1d6d0a80ea7302a439ca9b933 (patch)
tree1656adeecc51ba47cc4c081d0d7c56d7ec75ced2 /drivers/scsi/NCR53c406a.c
parent2938429501b73f6aeb312236eac7ed0416a07cd5 (diff)
CS5536: apply pci quirk for BIOS SMBUS bug
The new cs5535-* drivers use PCI header config info rather than MSRs to determine the memory region to use for things like GPIOs and MFGPTs. As anticipated, we've run into a buggy BIOS: [ 0.081818] pci 0000:00:14.0: reg 10: [io 0x6000-0x7fff] [ 0.081906] pci 0000:00:14.0: reg 14: [io 0x6100-0x61ff] [ 0.082015] pci 0000:00:14.0: reg 18: [io 0x6200-0x63ff] [ 0.082917] pci 0000:00:14.2: reg 20: [io 0xe000-0xe00f] [ 0.083551] pci 0000:00:15.0: reg 10: [mem 0xa0010000-0xa0010fff] [ 0.084436] pci 0000:00:15.1: reg 10: [mem 0xa0011000-0xa0011fff] [ 0.088816] PCI: pci_cache_line_size set to 32 bytes [ 0.088938] pci 0000:00:14.0: address space collision: [io 0x6100-0x61ff] already in use [ 0.089052] pci 0000:00:14.0: can't reserve [io 0x6100-0x61ff] This is a Soekris board, and its BIOS sets the size of the PCI ISA bridge device's BAR0 to 8k. In reality, it should be 8 bytes (BAR0 is used for SMBus stuff). This quirk checks for an incorrect size, and resets it accordingly. Signed-off-by: Andres Salomon <dilinger@collabora.co.uk> Tested-by: Leigh Porter <leigh@leighporter.org> Tested-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/scsi/NCR53c406a.c')
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