diff options
author | David S. Miller <davem@davemloft.net> | 2010-03-15 16:23:54 -0700 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-03-15 16:23:54 -0700 |
commit | 4961e02f1999e1c3468c09b2669c94d7c3ae82a8 (patch) | |
tree | 44c15abb09d7ba5e17a9aba95ee246648b1c1a8a /drivers/staging/et131x | |
parent | d14a0ebda7d3daede1a99c01527affb9ceaa4c22 (diff) | |
parent | a3d3203e4bb40f253b1541e310dc0f9305be7c84 (diff) |
Merge branch 'master' of /home/davem/src/GIT/linux-2.6/
Diffstat (limited to 'drivers/staging/et131x')
24 files changed, 705 insertions, 1640 deletions
diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index e715e4dcb52..ea746ba41fa 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h @@ -149,7 +149,7 @@ * GLOBAL Module of JAGCore Address Mapping * Located at address 0x0000 */ -typedef struct _GLOBAL_t { /* Location: */ +struct global_regs { /* Location: */ u32 txq_start_addr; /* 0x0000 */ u32 txq_end_addr; /* 0x0004 */ u32 rxq_start_addr; /* 0x0008 */ @@ -165,9 +165,7 @@ typedef struct _GLOBAL_t { /* Location: */ u32 msi_config; /* 0x0030 */ u32 loopback; /* 0x0034 */ u32 watchdog_timer; /* 0x0038 */ -} GLOBAL_t, *PGLOBAL_t; - -/* END OF GLOBAL REGISTER ADDRESS MAP */ +}; /* START OF TXDMA REGISTER ADDRESS MAP */ @@ -255,7 +253,7 @@ extern inline void add_12bit(u32 *v, int n) * Tx DMA Module of JAGCore Address Mapping * Located at address 0x1000 */ -typedef struct _TXDMA_t { /* Location: */ +struct txdma_regs { /* Location: */ u32 csr; /* 0x1000 */ u32 pr_base_hi; /* 0x1004 */ u32 pr_base_lo; /* 0x1008 */ @@ -282,7 +280,7 @@ typedef struct _TXDMA_t { /* Location: */ u32 DroppedTLPCount; /* 0x105c */ u32 NewServiceComplete; /* 0x1060 */ u32 EthernetPacketCount; /* 0x1064 */ -} TXDMA_t, *PTXDMA_t; +}; /* END OF TXDMA REGISTER ADDRESS MAP */ @@ -292,45 +290,25 @@ typedef struct _TXDMA_t { /* Location: */ /* * structure for control status reg in rxdma address map * Located at address 0x2000 + * + * CSR + * 0: halt + * 1-3: tc + * 4: fbr_big_endian + * 5: psr_big_endian + * 6: pkt_big_endian + * 7: dma_big_endian + * 8-9: fbr0_size + * 10: fbr0_enable + * 11-12: fbr1_size + * 13: fbr1_enable + * 14: unused + * 15: pkt_drop_disable + * 16: pkt_done_flush + * 17: halt_status + * 18-31: unused */ -typedef union _RXDMA_CSR_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused2:14; /* bits 18-31 */ - u32 halt_status:1; /* bit 17 */ - u32 pkt_done_flush:1; /* bit 16 */ - u32 pkt_drop_disable:1; /* bit 15 */ - u32 unused1:1; /* bit 14 */ - u32 fbr1_enable:1; /* bit 13 */ - u32 fbr1_size:2; /* bits 11-12 */ - u32 fbr0_enable:1; /* bit 10 */ - u32 fbr0_size:2; /* bits 8-9 */ - u32 dma_big_endian:1; /* bit 7 */ - u32 pkt_big_endian:1; /* bit 6 */ - u32 psr_big_endian:1; /* bit 5 */ - u32 fbr_big_endian:1; /* bit 4 */ - u32 tc:3; /* bits 1-3 */ - u32 halt:1; /* bit 0 */ -#else - u32 halt:1; /* bit 0 */ - u32 tc:3; /* bits 1-3 */ - u32 fbr_big_endian:1; /* bit 4 */ - u32 psr_big_endian:1; /* bit 5 */ - u32 pkt_big_endian:1; /* bit 6 */ - u32 dma_big_endian:1; /* bit 7 */ - u32 fbr0_size:2; /* bits 8-9 */ - u32 fbr0_enable:1; /* bit 10 */ - u32 fbr1_size:2; /* bits 11-12 */ - u32 fbr1_enable:1; /* bit 13 */ - u32 unused1:1; /* bit 14 */ - u32 pkt_drop_disable:1; /* bit 15 */ - u32 pkt_done_flush:1; /* bit 16 */ - u32 halt_status:1; /* bit 17 */ - u32 unused2:14; /* bits 18-31 */ -#endif - } bits; -} RXDMA_CSR_t, *PRXDMA_CSR_t; + /* * structure for dma writeback lo reg in rxdma address map @@ -451,18 +429,6 @@ typedef union _RXDMA_CSR_t { * 31-10: unused * 9-0: fbr ndesc */ -typedef union _RXDMA_FBR_NUM_DES_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused:22; /* bits 10-31 */ - u32 fbr_ndesc:10; /* bits 0-9 */ -#else - u32 fbr_ndesc:10; /* bits 0-9 */ - u32 unused:22; /* bits 10-31 */ -#endif - } bits; -} RXDMA_FBR_NUM_DES_t, *PRXDMA_FBR_NUM_DES_t; /* * structure for free buffer ring 0 available offset reg in rxdma address map @@ -532,8 +498,8 @@ typedef union _RXDMA_FBR_NUM_DES_t { * Rx DMA Module of JAGCore Address Mapping * Located at address 0x2000 */ -typedef struct _RXDMA_t { /* Location: */ - RXDMA_CSR_t csr; /* 0x2000 */ +struct rxdma_regs { /* Location: */ + u32 csr; /* 0x2000 */ u32 dma_wb_base_lo; /* 0x2004 */ u32 dma_wb_base_hi; /* 0x2008 */ u32 num_pkt_done; /* 0x200C */ @@ -562,7 +528,7 @@ typedef struct _RXDMA_t { /* Location: */ u32 fbr1_full_offset; /* 0x2068 */ u32 fbr1_rd_index; /* 0x206C */ u32 fbr1_min_des; /* 0x2070 */ -} RXDMA_t, *PRXDMA_t; +}; /* END OF RXDMA REGISTER ADDRESS MAP */ @@ -572,33 +538,18 @@ typedef struct _RXDMA_t { /* Location: */ /* * structure for control reg in txmac address map * located at address 0x3000 + * + * bits + * 31-8: unused + * 7: cklseg_disable + * 6: ckbcnt_disable + * 5: cksegnum + * 4: async_disable + * 3: fc_disable + * 2: mcif_disable + * 1: mif_disable + * 0: txmac_en */ -typedef union _TXMAC_CTL_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused:24; /* bits 8-31 */ - u32 cklseg_diable:1; /* bit 7 */ - u32 ckbcnt_disable:1; /* bit 6 */ - u32 cksegnum:1; /* bit 5 */ - u32 async_disable:1; /* bit 4 */ - u32 fc_disable:1; /* bit 3 */ - u32 mcif_disable:1; /* bit 2 */ - u32 mif_disable:1; /* bit 1 */ - u32 txmac_en:1; /* bit 0 */ -#else - u32 txmac_en:1; /* bit 0 */ - u32 mif_disable:1; /* bit 1 mac interface */ - u32 mcif_disable:1; /* bit 2 mem. contr. interface */ - u32 fc_disable:1; /* bit 3 */ - u32 async_disable:1; /* bit 4 */ - u32 cksegnum:1; /* bit 5 */ - u32 ckbcnt_disable:1; /* bit 6 */ - u32 cklseg_diable:1; /* bit 7 */ - u32 unused:24; /* bits 8-31 */ -#endif - } bits; -} TXMAC_CTL_t, *PTXMAC_CTL_t; /* * structure for shadow pointer reg in txmac address map @@ -612,23 +563,12 @@ typedef union _TXMAC_CTL_t { /* * structure for error count reg in txmac address map * located at address 0x3008 + * + * 31-12: unused + * 11-8: reserved + * 7-4: txq_underrun + * 3-0: fifo_underrun */ -typedef union _TXMAC_ERR_CNT_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused:20; /* bits 12-31 */ - u32 reserved:4; /* bits 8-11 */ - u32 txq_underrun:4; /* bits 4-7 */ - u32 fifo_underrun:4; /* bits 0-3 */ -#else - u32 fifo_underrun:4; /* bits 0-3 */ - u32 txq_underrun:4; /* bits 4-7 */ - u32 reserved:4; /* bits 8-11 */ - u32 unused:20; /* bits 12-31 */ -#endif - } bits; -} TXMAC_ERR_CNT_t, *PTXMAC_ERR_CNT_t; /* * structure for max fill reg in txmac address map @@ -657,64 +597,32 @@ typedef union _TXMAC_ERR_CNT_t { /* * structure for error reg in txmac address map * located at address 0x3018 + * + * 31-9: unused + * 8: fifo_underrun + * 7-6: unused + * 5: ctrl2_err + * 4: txq_underrun + * 3: bcnt_err + * 2: lseg_err + * 1: segnum_err + * 0: seg0_err */ -typedef union _TXMAC_ERR_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused2:23; /* bits 9-31 */ - u32 fifo_underrun:1; /* bit 8 */ - u32 unused1:2; /* bits 6-7 */ - u32 ctrl2_err:1; /* bit 5 */ - u32 txq_underrun:1; /* bit 4 */ - u32 bcnt_err:1; /* bit 3 */ - u32 lseg_err:1; /* bit 2 */ - u32 segnum_err:1; /* bit 1 */ - u32 seg0_err:1; /* bit 0 */ -#else - u32 seg0_err:1; /* bit 0 */ - u32 segnum_err:1; /* bit 1 */ - u32 lseg_err:1; /* bit 2 */ - u32 bcnt_err:1; /* bit 3 */ - u32 txq_underrun:1; /* bit 4 */ - u32 ctrl2_err:1; /* bit 5 */ - u32 unused1:2; /* bits 6-7 */ - u32 fifo_underrun:1; /* bit 8 */ - u32 unused2:23; /* bits 9-31 */ -#endif - } bits; -} TXMAC_ERR_t, *PTXMAC_ERR_t; /* * structure for error interrupt reg in txmac address map * located at address 0x301C + * + * 31-9: unused + * 8: fifo_underrun + * 7-6: unused + * 5: ctrl2_err + * 4: txq_underrun + * 3: bcnt_err + * 2: lseg_err + * 1: segnum_err + * 0: seg0_err */ -typedef union _TXMAC_ERR_INT_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused2:23; /* bits 9-31 */ - u32 fifo_underrun:1; /* bit 8 */ - u32 unused1:2; /* bits 6-7 */ - u32 ctrl2_err:1; /* bit 5 */ - u32 txq_underrun:1; /* bit 4 */ - u32 bcnt_err:1; /* bit 3 */ - u32 lseg_err:1; /* bit 2 */ - u32 segnum_err:1; /* bit 1 */ - u32 seg0_err:1; /* bit 0 */ -#else - u32 seg0_err:1; /* bit 0 */ - u32 segnum_err:1; /* bit 1 */ - u32 lseg_err:1; /* bit 2 */ - u32 bcnt_err:1; /* bit 3 */ - u32 txq_underrun:1; /* bit 4 */ - u32 ctrl2_err:1; /* bit 5 */ - u32 unused1:2; /* bits 6-7 */ - u32 fifo_underrun:1; /* bit 8 */ - u32 unused2:23; /* bits 9-31 */ -#endif - } bits; -} TXMAC_ERR_INT_t, *PTXMAC_ERR_INT_t; /* * structure for error interrupt reg in txmac address map @@ -728,17 +636,17 @@ typedef union _TXMAC_ERR_INT_t { /* * Tx MAC Module of JAGCore Address Mapping */ -typedef struct _TXMAC_t { /* Location: */ - TXMAC_CTL_t ctl; /* 0x3000 */ +struct txmac_regs { /* Location: */ + u32 ctl; /* 0x3000 */ u32 shadow_ptr; /* 0x3004 */ - TXMAC_ERR_CNT_t err_cnt; /* 0x3008 */ + u32 err_cnt; /* 0x3008 */ u32 max_fill; /* 0x300C */ u32 cf_param; /* 0x3010 */ u32 tx_test; /* 0x3014 */ - TXMAC_ERR_t err; /* 0x3018 */ - TXMAC_ERR_INT_t err_int; /* 0x301C */ + u32 err; /* 0x3018 */ + u32 err_int; /* 0x301C */ u32 bp_ctrl; /* 0x3020 */ -} TXMAC_t, *PTXMAC_t; +}; /* END OF TXMAC REGISTER ADDRESS MAP */ @@ -747,106 +655,47 @@ typedef struct _TXMAC_t { /* Location: */ /* * structure for rxmac control reg in rxmac address map * located at address 0x4000 + * + * 31-7: reserved + * 6: rxmac_int_disable + * 5: async_disable + * 4: mif_disable + * 3: wol_disable + * 2: pkt_filter_disable + * 1: mcif_disable + * 0: rxmac_en */ -typedef union _RXMAC_CTRL_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved:25; /* bits 7-31 */ - u32 rxmac_int_disable:1; /* bit 6 */ - u32 async_disable:1; /* bit 5 */ - u32 mif_disable:1; /* bit 4 */ - u32 wol_disable:1; /* bit 3 */ - u32 pkt_filter_disable:1; /* bit 2 */ - u32 mcif_disable:1; /* bit 1 */ - u32 rxmac_en:1; /* bit 0 */ -#else - u32 rxmac_en:1; /* bit 0 */ - u32 mcif_disable:1; /* bit 1 */ - u32 pkt_filter_disable:1; /* bit 2 */ - u32 wol_disable:1; /* bit 3 */ - u32 mif_disable:1; /* bit 4 */ - u32 async_disable:1; /* bit 5 */ - u32 rxmac_int_disable:1; /* bit 6 */ - u32 reserved:25; /* bits 7-31 */ -#endif - } bits; -} RXMAC_CTRL_t, *PRXMAC_CTRL_t; /* * structure for Wake On Lan Control and CRC 0 reg in rxmac address map * located at address 0x4004 + * 31-16: crc + * 15-12: reserved + * 11: ignore_pp + * 10: ignore_mp + * 9: clr_intr + * 8: ignore_link_chg + * 7: ignore_uni + * 6: ignore_multi + * 5: ignore_broad + * 4-0: valid_crc 4-0 */ -typedef union _RXMAC_WOL_CTL_CRC0_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 crc0:16; /* bits 16-31 */ - u32 reserve:4; /* bits 12-15 */ - u32 ignore_pp:1; /* bit 11 */ - u32 ignore_mp:1; /* bit 10 */ - u32 clr_intr:1; /* bit 9 */ - u32 ignore_link_chg:1; /* bit 8 */ - u32 ignore_uni:1; /* bit 7 */ - u32 ignore_multi:1; /* bit 6 */ - u32 ignore_broad:1; /* bit 5 */ - u32 valid_crc4:1; /* bit 4 */ - u32 valid_crc3:1; /* bit 3 */ - u32 valid_crc2:1; /* bit 2 */ - u32 valid_crc1:1; /* bit 1 */ - u32 valid_crc0:1; /* bit 0 */ -#else - u32 valid_crc0:1; /* bit 0 */ - u32 valid_crc1:1; /* bit 1 */ - u32 valid_crc2:1; /* bit 2 */ - u32 valid_crc3:1; /* bit 3 */ - u32 valid_crc4:1; /* bit 4 */ - u32 ignore_broad:1; /* bit 5 */ - u32 ignore_multi:1; /* bit 6 */ - u32 ignore_uni:1; /* bit 7 */ - u32 ignore_link_chg:1; /* bit 8 */ - u32 clr_intr:1; /* bit 9 */ - u32 ignore_mp:1; /* bit 10 */ - u32 ignore_pp:1; /* bit 11 */ - u32 reserve:4; /* bits 12-15 */ - u32 crc0:16; /* bits 16-31 */ -#endif - } bits; -} RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t; /* * structure for CRC 1 and CRC 2 reg in rxmac address map * located at address 0x4008 + * + * 31-16: crc2 + * 15-0: crc1 */ -typedef union _RXMAC_WOL_CRC12_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 crc2:16; /* bits 16-31 */ - u32 crc1:16; /* bits 0-15 */ -#else - u32 crc1:16; /* bits 0-15 */ - u32 crc2:16; /* bits 16-31 */ -#endif - } bits; -} RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t; /* * structure for CRC 3 and CRC 4 reg in rxmac address map * located at address 0x400C + * + * 31-16: crc4 + * 15-0: crc3 */ -typedef union _RXMAC_WOL_CRC34_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 crc4:16; /* bits 16-31 */ - u32 crc3:16; /* bits 0-15 */ -#else - u32 crc3:16; /* bits 0-15 */ - u32 crc4:16; /* bits 16-31 */ -#endif - } bits; -} RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t; /* * structure for Wake On Lan Source Address Lo reg in rxmac address map @@ -966,164 +815,84 @@ typedef union _RXMAC_UNI_PF_ADDR3_t { /* * structure for Packet Filter Control reg in rxmac address map * located at address 0x4084 + * + * 31-23: unused + * 22-16: min_pkt_size + * 15-4: unused + * 3: filter_frag_en + * 2: filter_uni_en + * 1: filter_multi_en + * 0: filter_broad_en */ -typedef union _RXMAC_PF_CTRL_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused2:9; /* bits 23-31 */ - u32 min_pkt_size:7; /* bits 16-22 */ - u32 unused1:12; /* bits 4-15 */ - u32 filter_frag_en:1; /* bit 3 */ - u32 filter_uni_en:1; /* bit 2 */ - u32 filter_multi_en:1; /* bit 1 */ - u32 filter_broad_en:1; /* bit 0 */ -#else - u32 filter_broad_en:1; /* bit 0 */ - u32 filter_multi_en:1; /* bit 1 */ - u32 filter_uni_en:1; /* bit 2 */ - u32 filter_frag_en:1; /* bit 3 */ - u32 unused1:12; /* bits 4-15 */ - u32 min_pkt_size:7; /* bits 16-22 */ - u32 unused2:9; /* bits 23-31 */ -#endif - } bits; -} RXMAC_PF_CTRL_t, *PRXMAC_PF_CTRL_t; /* * structure for Memory Controller Interface Control Max Segment reg in rxmac * address map. Located at address 0x4088 + * + * 31-10: reserved + * 9-2: max_size + * 1: fc_en + * 0: seg_en */ -typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved:22; /* bits 10-31 */ - u32 max_size:8; /* bits 2-9 */ - u32 fc_en:1; /* bit 1 */ - u32 seg_en:1; /* bit 0 */ -#else - u32 seg_en:1; /* bit 0 */ - u32 fc_en:1; /* bit 1 */ - u32 max_size:8; /* bits 2-9 */ - u32 reserved:22; /* bits 10-31 */ -#endif - } bits; -} RXMAC_MCIF_CTRL_MAX_SEG_t, *PRXMAC_MCIF_CTRL_MAX_SEG_t; /* * structure for Memory Controller Interface Water Mark reg in rxmac address * map. Located at address 0x408C + * + * 31-26: unused + * 25-16: mark_hi + * 15-10: unused + * 9-0: mark_lo */ -typedef union _RXMAC_MCIF_WATER_MARK_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved2:6; /* bits 26-31 */ - u32 mark_hi:10; /* bits 16-25 */ - u32 reserved1:6; /* bits 10-15 */ - u32 mark_lo:10; /* bits 0-9 */ -#else - u32 mark_lo:10; /* bits 0-9 */ - u32 reserved1:6; /* bits 10-15 */ - u32 mark_hi:10; /* bits 16-25 */ - u32 reserved2:6; /* bits 26-31 */ -#endif - } bits; -} RXMAC_MCIF_WATER_MARK_t, *PRXMAC_MCIF_WATER_MARK_t; /* * structure for Rx Queue Dialog reg in rxmac address map. * located at address 0x4090 + * + * 31-26: reserved + * 25-16: rd_ptr + * 15-10: reserved + * 9-0: wr_ptr */ -typedef union _RXMAC_RXQ_DIAG_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved2:6; /* bits 26-31 */ - u32 rd_ptr:10; /* bits 16-25 */ - u32 reserved1:6; /* bits 10-15 */ - u32 wr_ptr:10; /* bits 0-9 */ -#else - u32 wr_ptr:10; /* bits 0-9 */ - u32 reserved1:6; /* bits 10-15 */ - u32 rd_ptr:10; /* bits 16-25 */ - u32 reserved2:6; /* bits 26-31 */ -#endif - } bits; -} RXMAC_RXQ_DIAG_t, *PRXMAC_RXQ_DIAG_t; /* * structure for space availiable reg in rxmac address map. * located at address 0x4094 + * + * 31-17: reserved + * 16: space_avail_en + * 15-10: reserved + * 9-0: space_avail */ -typedef union _RXMAC_SPACE_AVAIL_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved2:15; /* bits 17-31 */ - u32 space_avail_en:1; /* bit 16 */ - u32 reserved1:6; /* bits 10-15 */ - u32 space_avail:10; /* bits 0-9 */ -#else - u32 space_avail:10; /* bits 0-9 */ - u32 reserved1:6; /* bits 10-15 */ - u32 space_avail_en:1; /* bit 16 */ - u32 reserved2:15; /* bits 17-31 */ -#endif - } bits; -} RXMAC_SPACE_AVAIL_t, *PRXMAC_SPACE_AVAIL_t; /* * structure for management interface reg in rxmac address map. * located at address 0x4098 + * + * 31-18: reserved + * 17: drop_pkt_en + * 16-0: drop_pkt_mask */ -typedef union _RXMAC_MIF_CTL_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserve:14; /* bits 18-31 */ - u32 drop_pkt_en:1; /* bit 17 */ - u32 drop_pkt_mask:17; /* bits 0-16 */ -#else - u32 drop_pkt_mask:17; /* bits 0-16 */ - u32 drop_pkt_en:1; /* bit 17 */ - u32 reserve:14; /* bits 18-31 */ -#endif - } bits; -} RXMAC_MIF_CTL_t, *PRXMAC_MIF_CTL_t; /* * structure for Error reg in rxmac address map. * located at address 0x409C + * + * 31-4: unused + * 3: mif + * 2: async + * 1: pkt_filter + * 0: mcif */ -typedef union _RXMAC_ERROR_REG_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserve:28; /* bits 4-31 */ - u32 mif:1; /* bit 3 */ - u32 async:1; /* bit 2 */ - u32 pkt_filter:1; /* bit 1 */ - u32 mcif:1; /* bit 0 */ -#else - u32 mcif:1; /* bit 0 */ - u32 pkt_filter:1; /* bit 1 */ - u32 async:1; /* bit 2 */ - u32 mif:1; /* bit 3 */ - u32 reserve:28; /* bits 4-31 */ -#endif - } bits; -} RXMAC_ERROR_REG_t, *PRXMAC_ERROR_REG_t; /* * Rx MAC Module of JAGCore Address Mapping */ typedef struct _RXMAC_t { /* Location: */ - RXMAC_CTRL_t ctrl; /* 0x4000 */ - RXMAC_WOL_CTL_CRC0_t crc0; /* 0x4004 */ - RXMAC_WOL_CRC12_t crc12; /* 0x4008 */ - RXMAC_WOL_CRC34_t crc34; /* 0x400C */ + u32 ctrl; /* 0x4000 */ + u32 crc0; /* 0x4004 */ + u32 crc12; /* 0x4008 */ + u32 crc34; /* 0x400C */ RXMAC_WOL_SA_LO_t sa_lo; /* 0x4010 */ RXMAC_WOL_SA_HI_t sa_hi; /* 0x4014 */ u32 mask0_word0; /* 0x4018 */ @@ -1153,17 +922,17 @@ typedef struct _RXMAC_t { /* Location: */ u32 multi_hash2; /* 0x4078 */ u32 multi_hash3; /* 0x407C */ u32 multi_hash4; /* 0x4080 */ - RXMAC_PF_CTRL_t pf_ctrl; /* 0x4084 */ - RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; /* 0x4088 */ - RXMAC_MCIF_WATER_MARK_t mcif_water_mark; /* 0x408C */ - RXMAC_RXQ_DIAG_t rxq_diag; /* 0x4090 */ - RXMAC_SPACE_AVAIL_t space_avail; /* 0x4094 */ - - RXMAC_MIF_CTL_t mif_ctrl; /* 0x4098 */ - RXMAC_ERROR_REG_t err_reg; /* 0x409C */ + u32 pf_ctrl; /* 0x4084 */ + u32 mcif_ctrl_max_seg; /* 0x4088 */ + u32 mcif_water_mark; /* 0x408C */ + u32 rxq_diag; /* 0x4090 */ + u32 space_avail; /* 0x4094 */ + + u32 mif_ctrl; /* 0x4098 */ + u32 err_reg; /* 0x409C */ } RXMAC_t, *PRXMAC_t; -/* END OF TXMAC REGISTER ADDRESS MAP */ +/* END OF RXMAC REGISTER ADDRESS MAP */ /* START OF MAC REGISTER ADDRESS MAP */ @@ -1337,37 +1106,19 @@ typedef struct _RXMAC_t { /* Location: */ /* * structure for Interface Status reg in mac address map. * located at address 0x503C + * + * 31-10: reserved + * 9: excess_defer + * 8: clash + * 7: phy_jabber + * 6: phy_link_ok + * 5: phy_full_duplex + * 4: phy_speed + * 3: pe100x_link_fail + * 2: pe10t_loss_carrier + * 1: pe10t_sqe_error + * 0: pe10t_jabber */ -typedef union _MAC_IF_STAT_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved:22; /* bits 10-31 */ - u32 excess_defer:1; /* bit 9 */ - u32 clash:1; /* bit 8 */ - u32 phy_jabber:1; /* bit 7 */ - u32 phy_link_ok:1; /* bit 6 */ - u32 phy_full_duplex:1; /* bit 5 */ - u32 phy_speed:1; /* bit 4 */ - u32 pe100x_link_fail:1; /* bit 3 */ - u32 pe10t_loss_carrie:1; /* bit 2 */ - u32 pe10t_sqe_error:1; /* bit 1 */ - u32 pe10t_jabber:1; /* bit 0 */ -#else - u32 pe10t_jabber:1; /* bit 0 */ - u32 pe10t_sqe_error:1; /* bit 1 */ - u32 pe10t_loss_carrie:1; /* bit 2 */ - u32 pe100x_link_fail:1; /* bit 3 */ - u32 phy_speed:1; /* bit 4 */ - u32 phy_full_duplex:1; /* bit 5 */ - u32 phy_link_ok:1; /* bit 6 */ - u32 phy_jabber:1; /* bit 7 */ - u32 clash:1; /* bit 8 */ - u32 excess_defer:1; /* bit 9 */ - u32 reserved:22; /* bits 10-31 */ -#endif - } bits; -} MAC_IF_STAT_t, *PMAC_IF_STAT_t; /* * structure for Mac Station Address, Part 1 reg in mac address map. @@ -1428,7 +1179,7 @@ typedef struct _MAC_t { /* Location: */ u32 mii_mgmt_stat; /* 0x5030 */ u32 mii_mgmt_indicator; /* 0x5034 */ u32 if_ctrl; /* 0x5038 */ - MAC_IF_STAT_t if_stat; /* 0x503C */ + u32 if_stat; /* 0x503C */ MAC_STATION_ADDR1_t station_addr_1; /* 0x5040 */ MAC_STATION_ADDR2_t station_addr_2; /* 0x5044 */ } MAC_t, *PMAC_t; @@ -1498,8 +1249,9 @@ typedef struct _MAC_t { /* Location: */ /* * MAC STATS Module of JAGCore Address Mapping */ -typedef struct _MAC_STAT_t { /* Location: */ - u32 pad[32]; /* 0x6000 - 607C */ +struct macstat_regs +{ /* Location: */ + u32 pad[32]; /* 0x6000 - 607C */ /* Tx/Rx 0-64 Byte Frame Counter */ u32 TR64; /* 0x6080 */ @@ -1644,7 +1396,7 @@ typedef struct _MAC_STAT_t { /* Location: */ /* Carry Register Two Mask Register */ u32 Carry2M; /* 0x613C */ -} MAC_STAT_t, *PMAC_STAT_t; +}; /* END OF MAC STAT REGISTER ADDRESS MAP */ @@ -1682,70 +1434,49 @@ typedef struct _MAC_STAT_t { /* Location: */ /* * Memory Control Module of JAGCore Address Mapping */ -typedef struct _MMC_t { /* Location: */ +struct mmc_regs { /* Location: */ u32 mmc_ctrl; /* 0x7000 */ u32 sram_access; /* 0x7004 */ u32 sram_word1; /* 0x7008 */ u32 sram_word2; /* 0x700C */ u32 sram_word3; /* 0x7010 */ u32 sram_word4; /* 0x7014 */ -} MMC_t, *PMMC_t; +}; /* END OF MMC REGISTER ADDRESS MAP */ -/* START OF EXP ROM REGISTER ADDRESS MAP */ - -/* - * Expansion ROM Module of JAGCore Address Mapping - */ - -/* Take this out until it is not empty */ -#if 0 -typedef struct _EXP_ROM_t { - -} EXP_ROM_t, *PEXP_ROM_t; -#endif - -/* END OF EXP ROM REGISTER ADDRESS MAP */ - - /* * JAGCore Address Mapping */ typedef struct _ADDRESS_MAP_t { - GLOBAL_t global; + struct global_regs global; /* unused section of global address map */ - u8 unused_global[4096 - sizeof(GLOBAL_t)]; - TXDMA_t txdma; + u8 unused_global[4096 - sizeof(struct global_regs)]; + struct txdma_regs txdma; /* unused section of txdma address map */ - u8 unused_txdma[4096 - sizeof(TXDMA_t)]; - RXDMA_t rxdma; + u8 unused_txdma[4096 - sizeof(struct txdma_regs)]; + struct rxdma_regs rxdma; /* unused section of rxdma address map */ - u8 unused_rxdma[4096 - sizeof(RXDMA_t)]; - TXMAC_t txmac; + u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)]; + struct txmac_regs txmac; /* unused section of txmac address map */ - u8 unused_txmac[4096 - sizeof(TXMAC_t)]; + u8 unused_txmac[4096 - sizeof(struct txmac_regs)]; RXMAC_t rxmac; /* unused section of rxmac address map */ u8 unused_rxmac[4096 - sizeof(RXMAC_t)]; MAC_t mac; /* unused section of mac address map */ u8 unused_mac[4096 - sizeof(MAC_t)]; - MAC_STAT_t macStat; + struct macstat_regs macstat; /* unused section of mac stat address map */ - u8 unused_mac_stat[4096 - sizeof(MAC_STAT_t)]; - MMC_t mmc; + u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)]; + struct mmc_regs mmc; /* unused section of mmc address map */ - u8 unused_mmc[4096 - sizeof(MMC_t)]; + u8 unused_mmc[4096 - sizeof(struct mmc_regs)]; /* unused section of address map */ u8 unused_[1015808]; -/* Take this out until it is not empty */ -#if 0 - EXP_ROM_t exp_rom; -#endif - u8 unused_exp_rom[4096]; /* MGS-size TBD */ u8 unused__[524288]; /* unused section of address map */ } ADDRESS_MAP_t, *PADDRESS_MAP_t; diff --git a/drivers/staging/et131x/et1310_eeprom.c b/drivers/staging/et131x/et1310_eeprom.c index bcca1f86f51..3ca253672ba 100644 --- a/drivers/staging/et131x/et1310_eeprom.c +++ b/drivers/staging/et131x/et1310_eeprom.c @@ -84,17 +84,42 @@ #include <linux/ioport.h> #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" -#include "et1310_eeprom.h" - #include "et131x_adapter.h" -#include "et131x_initpci.h" -#include "et131x_isr.h" - -#include "et1310_tx.h" +#include "et131x.h" +/* + * EEPROM Defines + */ +/* LBCIF Register Groups (addressed via 32-bit offsets) */ +#define LBCIF_DWORD0_GROUP 0xAC +#define LBCIF_DWORD1_GROUP 0xB0 + +/* LBCIF Registers (addressed via 8-bit offsets) */ +#define LBCIF_ADDRESS_REGISTER 0xAC +#define LBCIF_DATA_REGISTER 0xB0 +#define LBCIF_CONTROL_REGISTER 0xB1 +#define LBCIF_STATUS_REGISTER 0xB2 + +/* LBCIF Control Register Bits */ +#define LBCIF_CONTROL_SEQUENTIAL_READ 0x01 +#define LBCIF_CONTROL_PAGE_WRITE 0x02 +#define LBCIF_CONTROL_EEPROM_RELOAD 0x08 +#define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20 +#define LBCIF_CONTROL_I2C_WRITE 0x40 +#define LBCIF_CONTROL_LBCIF_ENABLE 0x80 + +/* LBCIF Status Register Bits */ +#define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01 +#define LBCIF_STATUS_I2C_IDLE 0x02 +#define LBCIF_STATUS_ACK_ERROR 0x04 +#define LBCIF_STATUS_GENERAL_ERROR 0x08 +#define LBCIF_STATUS_CHECKSUM_ERROR 0x40 +#define LBCIF_STATUS_EEPROM_PRESENT 0x80 + +/* Miscellaneous Constraints */ +#define MAX_NUM_REGISTER_POLLS 1000 +#define MAX_NUM_WRITE_RETRIES 2 static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status) { diff --git a/drivers/staging/et131x/et1310_eeprom.h b/drivers/staging/et131x/et1310_eeprom.h deleted file mode 100644 index 6a6c6a632a8..00000000000 --- a/drivers/staging/et131x/et1310_eeprom.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Agere Systems Inc. - * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * http://www.agere.com - * - *------------------------------------------------------------------------------ - * - * et1310_eeprom.h - Defines, structs, enums, prototypes, etc. used for EEPROM - * access routines - * - *------------------------------------------------------------------------------ - * - * SOFTWARE LICENSE - * - * This software is provided subject to the following terms and conditions, - * which you should read carefully before using the software. Using this - * software indicates your acceptance of these terms and conditions. If you do - * not agree with these terms and conditions, do not use the software. - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * - * Redistribution and use in source or binary forms, with or without - * modifications, are permitted provided that the following conditions are met: - * - * . Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following Disclaimer as comments in the code as - * well as in the documentation and/or other materials provided with the - * distribution. - * - * . Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following Disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * . Neither the name of Agere Systems Inc. nor the names of the contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * Disclaimer - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY - * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN - * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * - */ - -#ifndef __ET1310_EEPROM_H__ -#define __ET1310_EEPROM_H__ - -#include "et1310_address_map.h" - -/* - * EEPROM Defines - */ - -/* LBCIF Register Groups (addressed via 32-bit offsets) */ -#define LBCIF_DWORD0_GROUP 0xAC -#define LBCIF_DWORD1_GROUP 0xB0 - -/* LBCIF Registers (addressed via 8-bit offsets) */ -#define LBCIF_ADDRESS_REGISTER 0xAC -#define LBCIF_DATA_REGISTER 0xB0 -#define LBCIF_CONTROL_REGISTER 0xB1 -#define LBCIF_STATUS_REGISTER 0xB2 - -/* LBCIF Control Register Bits */ -#define LBCIF_CONTROL_SEQUENTIAL_READ 0x01 -#define LBCIF_CONTROL_PAGE_WRITE 0x02 -#define LBCIF_CONTROL_EEPROM_RELOAD 0x08 -#define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20 -#define LBCIF_CONTROL_I2C_WRITE 0x40 -#define LBCIF_CONTROL_LBCIF_ENABLE 0x80 - -/* LBCIF Status Register Bits */ -#define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01 -#define LBCIF_STATUS_I2C_IDLE 0x02 -#define LBCIF_STATUS_ACK_ERROR 0x04 -#define LBCIF_STATUS_GENERAL_ERROR 0x08 -#define LBCIF_STATUS_CHECKSUM_ERROR 0x40 -#define LBCIF_STATUS_EEPROM_PRESENT 0x80 - -/* Miscellaneous Constraints */ -#define MAX_NUM_REGISTER_POLLS 1000 -#define MAX_NUM_WRITE_RETRIES 2 - -/* Forward declaration of the private adapter structure */ -struct et131x_adapter; - -int et131x_init_eeprom(struct et131x_adapter *etdev); - -#endif /* _ET1310_EEPROM_H_ */ diff --git a/drivers/staging/et131x/et1310_jagcore.h b/drivers/staging/et131x/et1310_jagcore.h deleted file mode 100644 index 0807a01d88a..00000000000 --- a/drivers/staging/et131x/et1310_jagcore.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Agere Systems Inc. - * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * http://www.agere.com - * - *------------------------------------------------------------------------------ - * - * et1310_jagcore.h - Defines, structs, enums, prototypes, etc. pertaining to - * the JAGCore - * - *------------------------------------------------------------------------------ - * - * SOFTWARE LICENSE - * - * This software is provided subject to the following terms and conditions, - * which you should read carefully before using the software. Using this - * software indicates your acceptance of these terms and conditions. If you do - * not agree with these terms and conditions, do not use the software. - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * - * Redistribution and use in source or binary forms, with or without - * modifications, are permitted provided that the following conditions are met: - * - * . Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following Disclaimer as comments in the code as - * well as in the documentation and/or other materials provided with the - * distribution. - * - * . Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following Disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * . Neither the name of Agere Systems Inc. nor the names of the contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * Disclaimer - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY - * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN - * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * - */ - -#ifndef __ET1310_JAGCORE_H__ -#define __ET1310_JAGCORE_H__ - -#include "et1310_address_map.h" - - -#define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */ -#define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */ - -/* - * For interrupts, normal running is: - * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt, - * watchdog_interrupt & txdma_xfer_done - * - * In both cases, when flow control is enabled for either Tx or bi-direction, - * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the - * buffer rings are running low. - */ -#define INT_MASK_DISABLE 0xffffffff - -/* NOTE: Masking out MAC_STAT Interrupt for now... - * #define INT_MASK_ENABLE 0xfff6bf17 - * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7 - */ -#define INT_MASK_ENABLE 0xfffebf17 -#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7 - -/* Forward declaration of the private adapter structure */ -struct et131x_adapter; - -void ConfigGlobalRegs(struct et131x_adapter *pAdapter); -void ConfigMMCRegs(struct et131x_adapter *pAdapter); -void et131x_enable_interrupts(struct et131x_adapter *adapter); -void et131x_disable_interrupts(struct et131x_adapter *adapter); - -#endif /* __ET1310_JAGCORE_H__ */ diff --git a/drivers/staging/et131x/et1310_mac.c b/drivers/staging/et131x/et1310_mac.c index b8a1f203731..a292b1edc41 100644 --- a/drivers/staging/et131x/et1310_mac.c +++ b/drivers/staging/et131x/et1310_mac.c @@ -85,12 +85,19 @@ #include <linux/crc32.h> #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" -#include "et1310_mac.h" - #include "et131x_adapter.h" -#include "et131x_initpci.h" +#include "et131x.h" + + +#define COUNTER_WRAP_28_BIT 0x10000000 +#define COUNTER_WRAP_22_BIT 0x400000 +#define COUNTER_WRAP_16_BIT 0x10000 +#define COUNTER_WRAP_12_BIT 0x1000 + +#define COUNTER_MASK_28_BIT (COUNTER_WRAP_28_BIT - 1) +#define COUNTER_MASK_22_BIT (COUNTER_WRAP_22_BIT - 1) +#define COUNTER_MASK_16_BIT (COUNTER_WRAP_16_BIT - 1) +#define COUNTER_MASK_12_BIT (COUNTER_WRAP_12_BIT - 1) /** * ConfigMacRegs1 - Initialize the first part of MAC regs @@ -163,9 +170,9 @@ void ConfigMACRegs2(struct et131x_adapter *etdev) u32 cfg1; u32 cfg2; u32 ifctrl; - TXMAC_CTL_t ctl; + u32 ctl; - ctl.value = readl(&etdev->regs->txmac.ctl.value); + ctl = readl(&etdev->regs->txmac.ctl); cfg1 = readl(&pMac->cfg1); cfg2 = readl(&pMac->cfg2); ifctrl = readl(&pMac->if_ctrl); @@ -219,9 +226,8 @@ void ConfigMACRegs2(struct et131x_adapter *etdev) } /* Enable TXMAC */ - ctl.bits.txmac_en = 0x1; - ctl.bits.fc_disable = 0x1; - writel(ctl.value, &etdev->regs->txmac.ctl.value); + ctl |= 0x05; /* TX mac enable, FC disable */ + writel(ctl, &etdev->regs->txmac.ctl); /* Ready to start the RXDMA/TXDMA engine */ if (etdev->Flags & fMP_ADAPTER_LOWER_POWER) { @@ -235,15 +241,15 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) struct _RXMAC_t __iomem *pRxMac = &etdev->regs->rxmac; RXMAC_WOL_SA_LO_t sa_lo; RXMAC_WOL_SA_HI_t sa_hi; - RXMAC_PF_CTRL_t pf_ctrl = { 0 }; + u32 pf_ctrl = 0; /* Disable the MAC while it is being configured (also disable WOL) */ - writel(0x8, &pRxMac->ctrl.value); + writel(0x8, &pRxMac->ctrl); /* Initialize WOL to disabled. */ - writel(0, &pRxMac->crc0.value); - writel(0, &pRxMac->crc12.value); - writel(0, &pRxMac->crc34.value); + writel(0, &pRxMac->crc0); + writel(0, &pRxMac->crc12); + writel(0, &pRxMac->crc34); /* We need to set the WOL mask0 - mask4 next. We initialize it to * its default Values of 0x00000000 because there are not WOL masks @@ -286,12 +292,12 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) writel(sa_hi.value, &pRxMac->sa_hi.value); /* Disable all Packet Filtering */ - writel(0, &pRxMac->pf_ctrl.value); + writel(0, &pRxMac->pf_ctrl); /* Let's initialize the Unicast Packet filtering address */ if (etdev->PacketFilter & ET131X_PACKET_TYPE_DIRECTED) { SetupDeviceForUnicast(etdev); - pf_ctrl.bits.filter_uni_en = 1; + pf_ctrl |= 4; /* Unicast filter */ } else { writel(0, &pRxMac->uni_pf_addr1.value); writel(0, &pRxMac->uni_pf_addr2.value); @@ -299,20 +305,16 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) } /* Let's initialize the Multicast hash */ - if (etdev->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST) { - pf_ctrl.bits.filter_multi_en = 0; - } else { - pf_ctrl.bits.filter_multi_en = 1; + if (!(etdev->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST)) { + pf_ctrl |= 2; /* Multicast filter */ SetupDeviceForMulticast(etdev); } /* Runt packet filtering. Didn't work in version A silicon. */ - pf_ctrl.bits.min_pkt_size = NIC_MIN_PACKET_SIZE + 4; - pf_ctrl.bits.filter_frag_en = 1; - - if (etdev->RegistryJumboPacket > 8192) { - RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; + pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << 16; + pf_ctrl |= 8; /* Fragment filter */ + if (etdev->RegistryJumboPacket > 8192) /* In order to transmit jumbo packets greater than 8k, the * FIFO between RxMAC and RxDMA needs to be reduced in size * to (16k - Jumbo packet size). In order to implement this, @@ -320,25 +322,21 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) * packets down into segments which are (max_size * 16). In * this case we selected 256 bytes, since this is the size of * the PCI-Express TLP's that the 1310 uses. + * + * seg_en on, fc_en off, size 0x10 */ - mcif_ctrl_max_seg.bits.seg_en = 0x1; - mcif_ctrl_max_seg.bits.fc_en = 0x0; - mcif_ctrl_max_seg.bits.max_size = 0x10; - - writel(mcif_ctrl_max_seg.value, - &pRxMac->mcif_ctrl_max_seg.value); - } else { - writel(0, &pRxMac->mcif_ctrl_max_seg.value); - } + writel(0x41, &pRxMac->mcif_ctrl_max_seg); + else + writel(0, &pRxMac->mcif_ctrl_max_seg); /* Initialize the MCIF water marks */ - writel(0, &pRxMac->mcif_water_mark.value); + writel(0, &pRxMac->mcif_water_mark); /* Initialize the MIF control */ - writel(0, &pRxMac->mif_ctrl.value); + writel(0, &pRxMac->mif_ctrl); /* Initialize the Space Available Register */ - writel(0, &pRxMac->space_avail.value); + writel(0, &pRxMac->space_avail); /* Initialize the the mif_ctrl register * bit 3: Receive code error. One or more nibbles were signaled as @@ -354,9 +352,9 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) * bit 17: Drop packet enable */ if (etdev->linkspeed == TRUEPHY_SPEED_100MBPS) - writel(0x30038, &pRxMac->mif_ctrl.value); + writel(0x30038, &pRxMac->mif_ctrl); else - writel(0x30030, &pRxMac->mif_ctrl.value); + writel(0x30030, &pRxMac->mif_ctrl); /* Finally we initialize RxMac to be enabled & WOL disabled. Packet * filter is always enabled since it is where the runt packets are @@ -364,28 +362,28 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) * dropping doesn't work, so it is disabled in the pf_ctrl register, * but we still leave the packet filter on. */ - writel(pf_ctrl.value, &pRxMac->pf_ctrl.value); - writel(0x9, &pRxMac->ctrl.value); + writel(pf_ctrl, &pRxMac->pf_ctrl); + writel(0x9, &pRxMac->ctrl); } void ConfigTxMacRegs(struct et131x_adapter *etdev) { - struct _TXMAC_t __iomem *pTxMac = &etdev->regs->txmac; + struct txmac_regs *txmac = &etdev->regs->txmac; /* We need to update the Control Frame Parameters * cfpt - control frame pause timer set to 64 (0x40) * cfep - control frame extended pause timer set to 0x0 */ if (etdev->FlowControl == None) - writel(0, &pTxMac->cf_param); + writel(0, &txmac->cf_param); else - writel(0x40, &pTxMac->cf_param); + writel(0x40, &txmac->cf_param); } void ConfigMacStatRegs(struct et131x_adapter *etdev) { - struct _MAC_STAT_t __iomem *macstat = - &etdev->regs->macStat; + struct macstat_regs __iomem *macstat = + &etdev->regs->macstat; /* Next we need to initialize all the MAC_STAT registers to zero on * the device. @@ -456,8 +454,8 @@ void ConfigFlowControl(struct et131x_adapter *etdev) void UpdateMacStatHostCounters(struct et131x_adapter *etdev) { struct _ce_stats_t *stats = &etdev->Stats; - struct _MAC_STAT_t __iomem *macstat = - &etdev->regs->macStat; + struct macstat_regs __iomem *macstat = + &etdev->regs->macstat; stats->collisions += readl(&macstat->TNcl); stats->first_collision += readl(&macstat->TScl); @@ -493,11 +491,11 @@ void HandleMacStatInterrupt(struct et131x_adapter *etdev) /* Read the interrupt bits from the register(s). These are Clear On * Write. */ - Carry1 = readl(&etdev->regs->macStat.Carry1); - Carry2 = readl(&etdev->regs->macStat.Carry2); + Carry1 = readl(&etdev->regs->macstat.Carry1); + Carry2 = readl(&etdev->regs->macstat.Carry2); - writel(Carry1, &etdev->regs->macStat.Carry1); - writel(Carry2, &etdev->regs->macStat.Carry2); + writel(Carry1, &etdev->regs->macstat.Carry1); + writel(Carry2, &etdev->regs->macstat.Carry2); /* We need to do update the host copy of all the MAC_STAT counters. * For each counter, check it's overflow bit. If the overflow bit is diff --git a/drivers/staging/et131x/et1310_mac.h b/drivers/staging/et131x/et1310_mac.h deleted file mode 100644 index 2c385959453..00000000000 --- a/drivers/staging/et131x/et1310_mac.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Agere Systems Inc. - * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * http://www.agere.com - * - *------------------------------------------------------------------------------ - * - * et1310_mac.h - Defines, structs, enums, prototypes, etc. pertaining to the - * MAC. - * - *------------------------------------------------------------------------------ - * - * SOFTWARE LICENSE - * - * This software is provided subject to the following terms and conditions, - * which you should read carefully before using the software. Using this - * software indicates your acceptance of these terms and conditions. If you do - * not agree with these terms and conditions, do not use the software. - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * - * Redistribution and use in source or binary forms, with or without - * modifications, are permitted provided that the following conditions are met: - * - * . Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following Disclaimer as comments in the code as - * well as in the documentation and/or other materials provided with the - * distribution. - * - * . Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following Disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * . Neither the name of Agere Systems Inc. nor the names of the contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * Disclaimer - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY - * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN - * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * - */ - -#ifndef _ET1310_MAC_H_ -#define _ET1310_MAC_H_ - - -#include "et1310_address_map.h" - - -#define COUNTER_WRAP_28_BIT 0x10000000 -#define COUNTER_WRAP_22_BIT 0x400000 -#define COUNTER_WRAP_16_BIT 0x10000 -#define COUNTER_WRAP_12_BIT 0x1000 - -#define COUNTER_MASK_28_BIT (COUNTER_WRAP_28_BIT - 1) -#define COUNTER_MASK_22_BIT (COUNTER_WRAP_22_BIT - 1) -#define COUNTER_MASK_16_BIT (COUNTER_WRAP_16_BIT - 1) -#define COUNTER_MASK_12_BIT (COUNTER_WRAP_12_BIT - 1) - -#define UPDATE_COUNTER(HostCnt, DevCnt) \ - HostCnt = HostCnt + DevCnt; - -/* Forward declaration of the private adapter structure */ -struct et131x_adapter; - -void ConfigMACRegs1(struct et131x_adapter *adapter); -void ConfigMACRegs2(struct et131x_adapter *adapter); -void ConfigRxMacRegs(struct et131x_adapter *adapter); -void ConfigTxMacRegs(struct et131x_adapter *adapter); -void ConfigMacStatRegs(struct et131x_adapter *adapter); -void ConfigFlowControl(struct et131x_adapter *adapter); -void UpdateMacStatHostCounters(struct et131x_adapter *adapter); -void HandleMacStatInterrupt(struct et131x_adapter *adapter); -void SetupDeviceForMulticast(struct et131x_adapter *adapter); -void SetupDeviceForUnicast(struct et131x_adapter *adapter); - -#endif /* _ET1310_MAC_H_ */ diff --git a/drivers/staging/et131x/et1310_phy.c b/drivers/staging/et131x/et1310_phy.c index 6ecad619f77..4a55fbfbd59 100644 --- a/drivers/staging/et131x/et1310_phy.c +++ b/drivers/staging/et131x/et1310_phy.c @@ -85,17 +85,14 @@ #include <linux/random.h> #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" #include "et131x_adapter.h" -#include "et131x_netdev.h" -#include "et131x_initpci.h" #include "et1310_address_map.h" #include "et1310_tx.h" #include "et1310_rx.h" -#include "et1310_mac.h" + +#include "et131x.h" /* Prototypes for functions with local scope */ static void et131x_xcvr_init(struct et131x_adapter *etdev); diff --git a/drivers/staging/et131x/et1310_phy.h b/drivers/staging/et131x/et1310_phy.h index 758b9b25171..47907ba7601 100644 --- a/drivers/staging/et131x/et1310_phy.h +++ b/drivers/staging/et131x/et1310_phy.h @@ -736,32 +736,8 @@ typedef union _MI_LCR2_t { /* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */ -/* Forward declaration of the private adapter structure */ -struct et131x_adapter; /* Prototypes for ET1310_phy.c */ -int et131x_xcvr_find(struct et131x_adapter *adapter); -void et131x_setphy_normal(struct et131x_adapter *adapter); - -/* static inline function does not work because et131x_adapter is not always - * defined - */ -int PhyMiRead(struct et131x_adapter *adapter, u8 xcvrAddr, - u8 xcvrReg, u16 *value); -#define MiRead(adapter, xcvrReg, value) \ - PhyMiRead((adapter), (adapter)->Stats.xcvr_addr, (xcvrReg), (value)) - -int32_t MiWrite(struct et131x_adapter *adapter, - u8 xcvReg, u16 value); -void et131x_Mii_check(struct et131x_adapter *pAdapter, - MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints); - -/* This last is not strictly required (the driver could call the TPAL - * version instead), but this sets the adapter up correctly, and calls the - * access routine indirectly. This protects the driver from changes in TPAL. - */ -void SetPhy_10BaseTHalfDuplex(struct et131x_adapter *adapter); - /* Defines for PHY access routines */ /* Define bit operation flags */ @@ -843,14 +819,4 @@ void SetPhy_10BaseTHalfDuplex(struct et131x_adapter *adapter); /* #define TRU_VMI_LINK_CONTROL_REGISTER 29 */ /* #define TRU_VMI_TIMING_CONTROL_REGISTER */ -/* Prototypes for PHY access routines */ -void ET1310_PhyInit(struct et131x_adapter *adapter); -void ET1310_PhyReset(struct et131x_adapter *adapter); -void ET1310_PhyPowerDown(struct et131x_adapter *adapter, bool down); -void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *adapter, - u16 duplex); -void ET1310_PhyAccessMiBit(struct et131x_adapter *adapter, - u16 action, - u16 regnum, u16 bitnum, u8 *value); - #endif /* _ET1310_PHY_H_ */ diff --git a/drivers/staging/et131x/et1310_pm.c b/drivers/staging/et131x/et1310_pm.c index 7d077235929..41019e390af 100644 --- a/drivers/staging/et131x/et1310_pm.c +++ b/drivers/staging/et131x/et1310_pm.c @@ -83,13 +83,9 @@ #include <linux/ioport.h> #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" -#include "et1310_mac.h" #include "et1310_rx.h" - #include "et131x_adapter.h" -#include "et131x_initpci.h" +#include "et131x.h" /** * EnablePhyComa - called when network cable is unplugged diff --git a/drivers/staging/et131x/et1310_pm.h b/drivers/staging/et131x/et1310_pm.h deleted file mode 100644 index 295f3ab132f..00000000000 --- a/drivers/staging/et131x/et1310_pm.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Agere Systems Inc. - * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * http://www.agere.com - * - *------------------------------------------------------------------------------ - * - * et1310_pm.h - Defines, structs, enums, prototypes, etc. pertaining to power - * management. - * - *------------------------------------------------------------------------------ - * - * SOFTWARE LICENSE - * - * This software is provided subject to the following terms and conditions, - * which you should read carefully before using the software. Using this - * software indicates your acceptance of these terms and conditions. If you do - * not agree with these terms and conditions, do not use the software. - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * - * Redistribution and use in source or binary forms, with or without - * modifications, are permitted provided that the following conditions are met: - * - * . Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following Disclaimer as comments in the code as - * well as in the documentation and/or other materials provided with the - * distribution. - * - * . Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following Disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * . Neither the name of Agere Systems Inc. nor the names of the contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * Disclaimer - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY - * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN - * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * - */ - -#ifndef _ET1310_PM_H_ -#define _ET1310_PM_H_ - -#include "et1310_address_map.h" - -typedef struct _MP_POWER_MGMT { - /* variable putting the phy into coma mode when boot up with no cable - * plugged in after 5 seconds - */ - u8 TransPhyComaModeOnBoot; - - /* Next two used to save power information at power down. This - * information will be used during power up to set up parts of Power - * Management in JAGCore - */ - u16 PowerDownSpeed; - u8 PowerDownDuplex; -} MP_POWER_MGMT, *PMP_POWER_MGMT; - -/* Forward declaration of the private adapter structure - */ -struct et131x_adapter; - -void EnablePhyComa(struct et131x_adapter *adapter); -void DisablePhyComa(struct et131x_adapter *adapter); - -#endif /* _ET1310_PM_H_ */ diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c index 81c1a7478ad..54686e2ace6 100644 --- a/drivers/staging/et131x/et1310_rx.c +++ b/drivers/staging/et131x/et1310_rx.c @@ -84,14 +84,9 @@ #include <linux/ioport.h> #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" - #include "et131x_adapter.h" -#include "et131x_initpci.h" - #include "et1310_rx.h" - +#include "et131x.h" void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD pMpRfd); @@ -109,17 +104,16 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) u32 i, j; u32 bufsize; u32 pktStatRingSize, FBRChunkSize; - RX_RING_t *rx_ring; + struct rx_ring *rx_ring; /* Setup some convenience pointers */ - rx_ring = (RX_RING_t *) &adapter->RxRing; + rx_ring = &adapter->rx_ring; /* Alloc memory for the lookup table */ #ifdef USE_FBR0 - rx_ring->Fbr[0] = kmalloc(sizeof(FBRLOOKUPTABLE), GFP_KERNEL); + rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL); #endif - - rx_ring->Fbr[1] = kmalloc(sizeof(FBRLOOKUPTABLE), GFP_KERNEL); + rx_ring->fbr[1] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL); /* The first thing we will do is configure the sizes of the buffer * rings. These will change based on jumbo packet support. Larger @@ -163,14 +157,14 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) } #ifdef USE_FBR0 - adapter->RxRing.PsrNumEntries = adapter->RxRing.Fbr0NumEntries + - adapter->RxRing.Fbr1NumEntries; + adapter->rx_ring.PsrNumEntries = adapter->rx_ring.Fbr0NumEntries + + adapter->rx_ring.Fbr1NumEntries; #else - adapter->RxRing.PsrNumEntries = adapter->RxRing.Fbr1NumEntries; + adapter->rx_ring.PsrNumEntries = adapter->rx_ring.Fbr1NumEntries; #endif /* Allocate an area of memory for Free Buffer Ring 1 */ - bufsize = (sizeof(FBR_DESC_t) * rx_ring->Fbr1NumEntries) + 0xfff; + bufsize = (sizeof(struct fbr_desc) * rx_ring->Fbr1NumEntries) + 0xfff; rx_ring->pFbr1RingVa = pci_alloc_consistent(adapter->pdev, bufsize, &rx_ring->pFbr1RingPa); @@ -194,12 +188,12 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) &rx_ring->Fbr1Realpa, &rx_ring->Fbr1offset, 0x0FFF); - rx_ring->pFbr1RingVa = (void *)((uint8_t *) rx_ring->pFbr1RingVa + + rx_ring->pFbr1RingVa = (void *)((u8 *) rx_ring->pFbr1RingVa + rx_ring->Fbr1offset); #ifdef USE_FBR0 /* Allocate an area of memory for Free Buffer Ring 0 */ - bufsize = (sizeof(FBR_DESC_t) * rx_ring->Fbr0NumEntries) + 0xfff; + bufsize = (sizeof(struct fbr_desc) * rx_ring->Fbr0NumEntries) + 0xfff; rx_ring->pFbr0RingVa = pci_alloc_consistent(adapter->pdev, bufsize, &rx_ring->pFbr0RingPa); @@ -223,7 +217,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) &rx_ring->Fbr0Realpa, &rx_ring->Fbr0offset, 0x0FFF); - rx_ring->pFbr0RingVa = (void *)((uint8_t *) rx_ring->pFbr0RingVa + + rx_ring->pFbr0RingVa = (void *)((u8 *) rx_ring->pFbr0RingVa + rx_ring->Fbr0offset); #endif @@ -270,23 +264,23 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) /* Save the Virtual address of this index for quick * access later */ - rx_ring->Fbr[1]->Va[index] = - (uint8_t *) rx_ring->Fbr1MemVa[i] + + rx_ring->fbr[1]->virt[index] = + (u8 *) rx_ring->Fbr1MemVa[i] + (j * rx_ring->Fbr1BufferSize) + Fbr1Offset; /* now store the physical address in the descriptor * so the device can access it */ - rx_ring->Fbr[1]->PAHigh[index] = + rx_ring->fbr[1]->bus_high[index] = (u32) (Fbr1TempPa >> 32); - rx_ring->Fbr[1]->PALow[index] = (u32) Fbr1TempPa; + rx_ring->fbr[1]->bus_low[index] = (u32) Fbr1TempPa; Fbr1TempPa += rx_ring->Fbr1BufferSize; - rx_ring->Fbr[1]->Buffer1[index] = - rx_ring->Fbr[1]->Va[index]; - rx_ring->Fbr[1]->Buffer2[index] = - rx_ring->Fbr[1]->Va[index] - 4; + rx_ring->fbr[1]->buffer1[index] = + rx_ring->fbr[1]->virt[index]; + rx_ring->fbr[1]->buffer2[index] = + rx_ring->fbr[1]->virt[index] - 4; } } @@ -319,27 +313,27 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) for (j = 0; j < FBR_CHUNKS; j++) { u32 index = (i * FBR_CHUNKS) + j; - rx_ring->Fbr[0]->Va[index] = - (uint8_t *) rx_ring->Fbr0MemVa[i] + + rx_ring->fbr[0]->virt[index] = + (u8 *) rx_ring->Fbr0MemVa[i] + (j * rx_ring->Fbr0BufferSize) + Fbr0Offset; - rx_ring->Fbr[0]->PAHigh[index] = + rx_ring->fbr[0]->bus_high[index] = (u32) (Fbr0TempPa >> 32); - rx_ring->Fbr[0]->PALow[index] = (u32) Fbr0TempPa; + rx_ring->fbr[0]->bus_low[index] = (u32) Fbr0TempPa; Fbr0TempPa += rx_ring->Fbr0BufferSize; - rx_ring->Fbr[0]->Buffer1[index] = - rx_ring->Fbr[0]->Va[index]; - rx_ring->Fbr[0]->Buffer2[index] = - rx_ring->Fbr[0]->Va[index] - 4; + rx_ring->fbr[0]->buffer1[index] = + rx_ring->fbr[0]->virt[index]; + rx_ring->fbr[0]->buffer2[index] = + rx_ring->fbr[0]->virt[index] - 4; } } #endif /* Allocate an area of memory for FIFO of Packet Status ring entries */ pktStatRingSize = - sizeof(PKT_STAT_DESC_t) * adapter->RxRing.PsrNumEntries; + sizeof(struct pkt_stat_desc) * adapter->rx_ring.PsrNumEntries; rx_ring->pPSRingVa = pci_alloc_consistent(adapter->pdev, pktStatRingSize, @@ -360,16 +354,16 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) */ /* Allocate an area of memory for writeback of status information */ - rx_ring->pRxStatusVa = pci_alloc_consistent(adapter->pdev, - sizeof(RX_STATUS_BLOCK_t), - &rx_ring->pRxStatusPa); - if (!rx_ring->pRxStatusVa) { + rx_ring->rx_status_block = pci_alloc_consistent(adapter->pdev, + sizeof(struct rx_status_block), + &rx_ring->rx_status_bus); + if (!rx_ring->rx_status_block) { dev_err(&adapter->pdev->dev, "Cannot alloc memory for Status Block\n"); return -ENOMEM; } rx_ring->NumRfd = NIC_DEFAULT_NUM_RFD; - printk("PRS %lx\n", (unsigned long)rx_ring->pRxStatusPa); + printk("PRS %lx\n", (unsigned long)rx_ring->rx_status_bus); /* Recv * pci_pool_create initializes a lookaside list. After successful @@ -403,10 +397,10 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) u32 bufsize; u32 pktStatRingSize; PMP_RFD rfd; - RX_RING_t *rx_ring; + struct rx_ring *rx_ring; /* Setup some convenience pointers */ - rx_ring = (RX_RING_t *) &adapter->RxRing; + rx_ring = &adapter->rx_ring; /* Free RFDs and associated packet descriptors */ WARN_ON(rx_ring->nReadyRecv != rx_ring->NumRfd); @@ -417,7 +411,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) list_del(&rfd->list_node); rfd->Packet = NULL; - kmem_cache_free(adapter->RxRing.RecvLookaside, rfd); + kmem_cache_free(adapter->rx_ring.RecvLookaside, rfd); } /* Free Free Buffer Ring 1 */ @@ -447,15 +441,14 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) } /* Now the FIFO itself */ - rx_ring->pFbr1RingVa = (void *)((uint8_t *) + rx_ring->pFbr1RingVa = (void *)((u8 *) rx_ring->pFbr1RingVa - rx_ring->Fbr1offset); - bufsize = - (sizeof(FBR_DESC_t) * rx_ring->Fbr1NumEntries) + 0xfff; + bufsize = (sizeof(struct fbr_desc) * rx_ring->Fbr1NumEntries) + + 0xfff; - pci_free_consistent(adapter->pdev, - bufsize, - rx_ring->pFbr1RingVa, rx_ring->pFbr1RingPa); + pci_free_consistent(adapter->pdev, bufsize, + rx_ring->pFbr1RingVa, rx_ring->pFbr1RingPa); rx_ring->pFbr1RingVa = NULL; } @@ -481,11 +474,11 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) } /* Now the FIFO itself */ - rx_ring->pFbr0RingVa = (void *)((uint8_t *) + rx_ring->pFbr0RingVa = (void *)((u8 *) rx_ring->pFbr0RingVa - rx_ring->Fbr0offset); - bufsize = - (sizeof(FBR_DESC_t) * rx_ring->Fbr0NumEntries) + 0xfff; + bufsize = (sizeof(struct fbr_desc) * rx_ring->Fbr0NumEntries) + + 0xfff; pci_free_consistent(adapter->pdev, bufsize, @@ -498,7 +491,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) /* Free Packet Status Ring */ if (rx_ring->pPSRingVa) { pktStatRingSize = - sizeof(PKT_STAT_DESC_t) * adapter->RxRing.PsrNumEntries; + sizeof(struct pkt_stat_desc) * adapter->rx_ring.PsrNumEntries; pci_free_consistent(adapter->pdev, pktStatRingSize, rx_ring->pPSRingVa, rx_ring->pPSRingPa); @@ -507,12 +500,11 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) } /* Free area of memory for the writeback of status information */ - if (rx_ring->pRxStatusVa) { + if (rx_ring->rx_status_block) { pci_free_consistent(adapter->pdev, - sizeof(RX_STATUS_BLOCK_t), - rx_ring->pRxStatusVa, rx_ring->pRxStatusPa); - - rx_ring->pRxStatusVa = NULL; + sizeof(struct rx_status_block), + rx_ring->rx_status_block, rx_ring->rx_status_bus); + rx_ring->rx_status_block = NULL; } /* Free receive buffer pool */ @@ -527,10 +519,10 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) /* Free the FBR Lookup Table */ #ifdef USE_FBR0 - kfree(rx_ring->Fbr[0]); + kfree(rx_ring->fbr[0]); #endif - kfree(rx_ring->Fbr[1]); + kfree(rx_ring->fbr[1]); /* Reset Counters */ rx_ring->nReadyRecv = 0; @@ -548,10 +540,10 @@ int et131x_init_recv(struct et131x_adapter *adapter) PMP_RFD rfd = NULL; u32 rfdct; u32 numrfd = 0; - RX_RING_t *rx_ring = NULL; + struct rx_ring *rx_ring; /* Setup some convenience pointers */ - rx_ring = (RX_RING_t *) &adapter->RxRing; + rx_ring = &adapter->rx_ring; /* Setup each RFD */ for (rfdct = 0; rfdct < rx_ring->NumRfd; rfdct++) { @@ -594,9 +586,9 @@ int et131x_init_recv(struct et131x_adapter *adapter) */ void ConfigRxDmaRegs(struct et131x_adapter *etdev) { - struct _RXDMA_t __iomem *rx_dma = &etdev->regs->rxdma; - struct _rx_ring_t *rx_local = &etdev->RxRing; - PFBR_DESC_t fbr_entry; + struct rxdma_regs __iomem *rx_dma = &etdev->regs->rxdma; + struct rx_ring *rx_local = &etdev->rx_ring; + struct fbr_desc *fbr_entry; u32 entry; u32 psr_num_des; unsigned long flags; @@ -611,11 +603,11 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev) * are ever returned, make sure the high part is retrieved here * before storing the adjusted address. */ - writel((u32) ((u64)rx_local->pRxStatusPa >> 32), + writel((u32) ((u64)rx_local->rx_status_bus >> 32), &rx_dma->dma_wb_base_hi); - writel((u32) rx_local->pRxStatusPa, &rx_dma->dma_wb_base_lo); + writel((u32) rx_local->rx_status_bus, &rx_dma->dma_wb_base_lo); - memset(rx_local->pRxStatusVa, 0, sizeof(RX_STATUS_BLOCK_t)); + memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block)); /* Set the address and parameters of the packet status ring into the * 1310's registers @@ -636,11 +628,11 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev) rx_local->local_psr_full = 0; /* Now's the best time to initialize FBR1 contents */ - fbr_entry = (PFBR_DESC_t) rx_local->pFbr1RingVa; + fbr_entry = (struct fbr_desc *) rx_local->pFbr1RingVa; for (entry = 0; entry < rx_local->Fbr1NumEntries; entry++) { - fbr_entry->addr_hi = rx_local->Fbr[1]->PAHigh[entry]; - fbr_entry->addr_lo = rx_local->Fbr[1]->PALow[entry]; - fbr_entry->word2.bits.bi = entry; + fbr_entry->addr_hi = rx_local->fbr[1]->bus_high[entry]; + fbr_entry->addr_lo = rx_local->fbr[1]->bus_low[entry]; + fbr_entry->word2 = entry; fbr_entry++; } @@ -661,11 +653,11 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev) #ifdef USE_FBR0 /* Now's the best time to initialize FBR0 contents */ - fbr_entry = (PFBR_DESC_t) rx_local->pFbr0RingVa; + fbr_entry = (struct fbr_desc *) rx_local->pFbr0RingVa; for (entry = 0; entry < rx_local->Fbr0NumEntries; entry++) { - fbr_entry->addr_hi = rx_local->Fbr[0]->PAHigh[entry]; - fbr_entry->addr_lo = rx_local->Fbr[0]->PALow[entry]; - fbr_entry->word2.bits.bi = entry; + fbr_entry->addr_hi = rx_local->fbr[0]->bus_high[entry]; + fbr_entry->addr_lo = rx_local->fbr[0]->bus_low[entry]; + fbr_entry->word2 = entry; fbr_entry++; } @@ -721,18 +713,17 @@ void SetRxDmaTimer(struct et131x_adapter *etdev) */ void et131x_rx_dma_disable(struct et131x_adapter *etdev) { - RXDMA_CSR_t csr; - + u32 csr; /* Setup the receive dma configuration register */ - writel(0x00002001, &etdev->regs->rxdma.csr.value); - csr.value = readl(&etdev->regs->rxdma.csr.value); - if (csr.bits.halt_status != 1) { + writel(0x00002001, &etdev->regs->rxdma.csr); + csr = readl(&etdev->regs->rxdma.csr); + if ((csr & 0x00020000) != 1) { /* Check halt status (bit 17) */ udelay(5); - csr.value = readl(&etdev->regs->rxdma.csr.value); - if (csr.bits.halt_status != 1) + csr = readl(&etdev->regs->rxdma.csr); + if ((csr & 0x00020000) != 1) dev_err(&etdev->pdev->dev, - "RX Dma failed to enter halt state. CSR 0x%08x\n", - csr.value); + "RX Dma failed to enter halt state. CSR 0x%08x\n", + csr); } } @@ -743,34 +734,33 @@ void et131x_rx_dma_disable(struct et131x_adapter *etdev) void et131x_rx_dma_enable(struct et131x_adapter *etdev) { /* Setup the receive dma configuration register for normal operation */ - RXDMA_CSR_t csr = { 0 }; - - csr.bits.fbr1_enable = 1; - if (etdev->RxRing.Fbr1BufferSize == 4096) - csr.bits.fbr1_size = 1; - else if (etdev->RxRing.Fbr1BufferSize == 8192) - csr.bits.fbr1_size = 2; - else if (etdev->RxRing.Fbr1BufferSize == 16384) - csr.bits.fbr1_size = 3; + u32 csr = 0x2000; /* FBR1 enable */ + + if (etdev->rx_ring.Fbr1BufferSize == 4096) + csr |= 0x0800; + else if (etdev->rx_ring.Fbr1BufferSize == 8192) + csr |= 0x1000; + else if (etdev->rx_ring.Fbr1BufferSize == 16384) + csr |= 0x1800; #ifdef USE_FBR0 - csr.bits.fbr0_enable = 1; - if (etdev->RxRing.Fbr0BufferSize == 256) - csr.bits.fbr0_size = 1; - else if (etdev->RxRing.Fbr0BufferSize == 512) - csr.bits.fbr0_size = 2; - else if (etdev->RxRing.Fbr0BufferSize == 1024) - csr.bits.fbr0_size = 3; + csr |= 0x0400; /* FBR0 enable */ + if (etdev->rx_ring.Fbr0BufferSize == 256) + csr |= 0x0100; + else if (etdev->rx_ring.Fbr0BufferSize == 512) + csr |= 0x0200; + else if (etdev->rx_ring.Fbr0BufferSize == 1024) + csr |= 0x0300; #endif - writel(csr.value, &etdev->regs->rxdma.csr.value); + writel(csr, &etdev->regs->rxdma.csr); - csr.value = readl(&etdev->regs->rxdma.csr.value); - if (csr.bits.halt_status != 0) { + csr = readl(&etdev->regs->rxdma.csr); + if ((csr & 0x00020000) != 0) { udelay(5); - csr.value = readl(&etdev->regs->rxdma.csr.value); - if (csr.bits.halt_status != 0) { + csr = readl(&etdev->regs->rxdma.csr); + if ((csr & 0x00020000) != 0) { dev_err(&etdev->pdev->dev, "RX Dma failed to exit halt state. CSR 0x%08x\n", - csr.value); + csr); } } } @@ -788,46 +778,44 @@ void et131x_rx_dma_enable(struct et131x_adapter *etdev) */ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) { - struct _rx_ring_t *rx_local = &etdev->RxRing; - PRX_STATUS_BLOCK_t status; - PPKT_STAT_DESC_t psr; + struct rx_ring *rx_local = &etdev->rx_ring; + struct rx_status_block *status; + struct pkt_stat_desc *psr; PMP_RFD rfd; u32 i; - uint8_t *buf; + u8 *buf; unsigned long flags; struct list_head *element; - uint8_t rindex; - uint16_t bindex; + u8 rindex; + u16 bindex; u32 len; - PKT_STAT_DESC_WORD0_t Word0; + u32 word0; + u32 word1; /* RX Status block is written by the DMA engine prior to every * interrupt. It contains the next to be used entry in the Packet * Status Ring, and also the two Free Buffer rings. */ - status = (PRX_STATUS_BLOCK_t) rx_local->pRxStatusVa; + status = rx_local->rx_status_block; + word1 = status->Word1 >> 16; /* Get the useful bits */ - /* FIXME: tidy later when conversions complete */ - if (status->Word1.bits.PSRoffset == - (rx_local->local_psr_full & 0xFFF) && - status->Word1.bits.PSRwrap == - ((rx_local->local_psr_full >> 12) & 1)) { + /* Check the PSR and wrap bits do not match */ + if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF)) /* Looks like this ring is not updated yet */ return NULL; - } /* The packet status ring indicates that data is available. */ - psr = (PPKT_STAT_DESC_t) (rx_local->pPSRingVa) + + psr = (struct pkt_stat_desc *) (rx_local->pPSRingVa) + (rx_local->local_psr_full & 0xFFF); /* Grab any information that is required once the PSR is * advanced, since we can no longer rely on the memory being * accurate */ - len = psr->word1.bits.length; - rindex = (uint8_t) psr->word1.bits.ri; - bindex = (uint16_t) psr->word1.bits.bi; - Word0 = psr->word0; + len = psr->word1 & 0xFFFF; + rindex = (psr->word1 >> 26) & 0x03; + bindex = (psr->word1 >> 16) & 0x3FF; + word0 = psr->word0; /* Indicate that we have used this PSR entry. */ /* FIXME wrap 12 */ @@ -842,9 +830,8 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) &etdev->regs->rxdma.psr_full_offset); #ifndef USE_FBR0 - if (rindex != 1) { + if (rindex != 1) return NULL; - } #endif #ifdef USE_FBR0 @@ -899,7 +886,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) if (len) { if (etdev->ReplicaPhyLoopbk == 1) { - buf = rx_local->Fbr[rindex]->Va[bindex]; + buf = rx_local->fbr[rindex]->virt[bindex]; if (memcmp(&buf[6], &etdev->CurrentAddress[0], ETH_ALEN) == 0) { @@ -911,8 +898,8 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) } /* Determine if this is a multicast packet coming in */ - if ((Word0.value & ALCATEL_MULTICAST_PKT) && - !(Word0.value & ALCATEL_BROADCAST_PKT)) { + if ((word0 & ALCATEL_MULTICAST_PKT) && + !(word0 & ALCATEL_BROADCAST_PKT)) { /* Promiscuous mode and Multicast mode are * not mutually exclusive as was first * thought. I guess Promiscuous is just @@ -923,8 +910,8 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) if ((etdev->PacketFilter & ET131X_PACKET_TYPE_MULTICAST) && !(etdev->PacketFilter & ET131X_PACKET_TYPE_PROMISCUOUS) && !(etdev->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST)) { - buf = rx_local->Fbr[rindex]-> - Va[bindex]; + buf = rx_local->fbr[rindex]-> + virt[bindex]; /* Loop through our list to see if the * destination address of this packet @@ -963,7 +950,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) if (len > 0) etdev->Stats.multircv++; - } else if (Word0.value & ALCATEL_BROADCAST_PKT) + } else if (word0 & ALCATEL_BROADCAST_PKT) etdev->Stats.brdcstrcv++; else /* Not sure what this counter measures in @@ -990,7 +977,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) etdev->net_stats.rx_bytes += rfd->PacketSize; memcpy(skb_put(skb, rfd->PacketSize), - rx_local->Fbr[rindex]->Va[bindex], + rx_local->fbr[rindex]->virt[bindex], rfd->PacketSize); skb->dev = etdev->netdev; @@ -1014,7 +1001,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) */ void et131x_reset_recv(struct et131x_adapter *etdev) { - WARN_ON(list_empty(&etdev->RxRing.RecvList)); + WARN_ON(list_empty(&etdev->rx_ring.RecvList)); } @@ -1032,8 +1019,8 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *etdev) /* Process up to available RFD's */ while (count < NUM_PACKETS_HANDLED) { - if (list_empty(&etdev->RxRing.RecvList)) { - WARN_ON(etdev->RxRing.nReadyRecv != 0); + if (list_empty(&etdev->rx_ring.RecvList)) { + WARN_ON(etdev->rx_ring.nReadyRecv != 0); done = false; break; } @@ -1058,7 +1045,7 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *etdev) etdev->Stats.ipackets++; /* Set the status on the packet, either resources or success */ - if (etdev->RxRing.nReadyRecv < RFD_LOW_WATER_MARK) { + if (etdev->rx_ring.nReadyRecv < RFD_LOW_WATER_MARK) { dev_warn(&etdev->pdev->dev, "RFD's are running out\n"); } @@ -1066,12 +1053,12 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *etdev) } if (count == NUM_PACKETS_HANDLED || !done) { - etdev->RxRing.UnfinishedReceives = true; + etdev->rx_ring.UnfinishedReceives = true; writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO, &etdev->regs->global.watchdog_timer); } else /* Watchdog timer will disable itself if appropriate. */ - etdev->RxRing.UnfinishedReceives = false; + etdev->rx_ring.UnfinishedReceives = false; } static inline u32 bump_fbr(u32 *fbr, u32 limit) @@ -1099,10 +1086,10 @@ static inline u32 bump_fbr(u32 *fbr, u32 limit) */ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD rfd) { - struct _rx_ring_t *rx_local = &etdev->RxRing; - struct _RXDMA_t __iomem *rx_dma = &etdev->regs->rxdma; - uint16_t bi = rfd->bufferindex; - uint8_t ri = rfd->ringindex; + struct rx_ring *rx_local = &etdev->rx_ring; + struct rxdma_regs __iomem *rx_dma = &etdev->regs->rxdma; + u16 bi = rfd->bufferindex; + u8 ri = rfd->ringindex; unsigned long flags; /* We don't use any of the OOB data besides status. Otherwise, we @@ -1116,17 +1103,17 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD rfd) spin_lock_irqsave(&etdev->FbrLock, flags); if (ri == 1) { - PFBR_DESC_t next = - (PFBR_DESC_t) (rx_local->pFbr1RingVa) + - INDEX10(rx_local->local_Fbr1_full); + struct fbr_desc *next = + (struct fbr_desc *) (rx_local->pFbr1RingVa) + + INDEX10(rx_local->local_Fbr1_full); /* Handle the Free Buffer Ring advancement here. Write * the PA / Buffer Index for the returned buffer into * the oldest (next to be freed)FBR entry */ - next->addr_hi = rx_local->Fbr[1]->PAHigh[bi]; - next->addr_lo = rx_local->Fbr[1]->PALow[bi]; - next->word2.value = bi; + next->addr_hi = rx_local->fbr[1]->bus_high[bi]; + next->addr_lo = rx_local->fbr[1]->bus_low[bi]; + next->word2 = bi; writel(bump_fbr(&rx_local->local_Fbr1_full, rx_local->Fbr1NumEntries - 1), @@ -1134,17 +1121,17 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD rfd) } #ifdef USE_FBR0 else { - PFBR_DESC_t next = - (PFBR_DESC_t) rx_local->pFbr0RingVa + - INDEX10(rx_local->local_Fbr0_full); + struct fbr_desc *next = (struct fbr_desc *) + rx_local->pFbr0RingVa + + INDEX10(rx_local->local_Fbr0_full); /* Handle the Free Buffer Ring advancement here. Write * the PA / Buffer Index for the returned buffer into * the oldest (next to be freed) FBR entry */ - next->addr_hi = rx_local->Fbr[0]->PAHigh[bi]; - next->addr_lo = rx_local->Fbr[0]->PALow[bi]; - next->word2.value = bi; + next->addr_hi = rx_local->fbr[0]->bus_high[bi]; + next->addr_lo = rx_local->fbr[0]->bus_low[bi]; + next->word2 = bi; writel(bump_fbr(&rx_local->local_Fbr0_full, rx_local->Fbr0NumEntries - 1), diff --git a/drivers/staging/et131x/et1310_rx.h b/drivers/staging/et131x/et1310_rx.h index 69514593612..ca84a9146d6 100644 --- a/drivers/staging/et131x/et1310_rx.h +++ b/drivers/staging/et131x/et1310_rx.h @@ -91,120 +91,60 @@ #define ALCATEL_BROADCAST_PKT 0x02000000 /* typedefs for Free Buffer Descriptors */ -typedef union _FBR_WORD2_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 reserved:22; /* bits 10-31 */ - u32 bi:10; /* bits 0-9(Buffer Index) */ -#else - u32 bi:10; /* bits 0-9(Buffer Index) */ - u32 reserved:22; /* bit 10-31 */ -#endif - } bits; -} FBR_WORD2_t, *PFBR_WORD2_t; - -typedef struct _FBR_DESC_t { +struct fbr_desc +{ u32 addr_lo; u32 addr_hi; - FBR_WORD2_t word2; -} FBR_DESC_t, *PFBR_DESC_t; - -/* Typedefs for Packet Status Ring Descriptors */ -typedef union _PKT_STAT_DESC_WORD0_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - /* top 16 bits are from the Alcatel Status Word as enumerated in */ - /* PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2) */ -#if 0 - u32 asw_trunc:1; /* bit 31(Rx frame truncated) */ -#endif - u32 asw_long_evt:1; /* bit 31(Rx long event) */ - u32 asw_VLAN_tag:1; /* bit 30(VLAN tag detected) */ - u32 asw_unsupported_op:1; /* bit 29(unsupported OP code) */ - u32 asw_pause_frame:1; /* bit 28(is a pause frame) */ - u32 asw_control_frame:1; /* bit 27(is a control frame) */ - u32 asw_dribble_nibble:1; /* bit 26(spurious bits after EOP) */ - u32 asw_broadcast:1; /* bit 25(has a broadcast address) */ - u32 asw_multicast:1; /* bit 24(has a multicast address) */ - u32 asw_OK:1; /* bit 23(valid CRC + no code error) */ - u32 asw_too_long:1; /* bit 22(frame length > 1518 bytes) */ - u32 asw_len_chk_err:1; /* bit 21(frame length field incorrect) */ - u32 asw_CRC_err:1; /* bit 20(CRC error) */ - u32 asw_code_err:1; /* bit 19(one or more nibbles signalled as errors) */ - u32 asw_false_carrier_event:1; /* bit 18(bad carrier since last good packet) */ - u32 asw_RX_DV_event:1; /* bit 17(short receive event detected) */ - u32 asw_prev_pkt_dropped:1;/* bit 16(e.g. IFG too small on previous) */ - u32 unused:5; /* bits 11-15 */ - u32 vp:1; /* bit 10(VLAN Packet) */ - u32 jp:1; /* bit 9(Jumbo Packet) */ - u32 ft:1; /* bit 8(Frame Truncated) */ - u32 drop:1; /* bit 7(Drop packet) */ - u32 rxmac_error:1; /* bit 6(RXMAC Error Indicator) */ - u32 wol:1; /* bit 5(WOL Event) */ - u32 tcpp:1; /* bit 4(TCP checksum pass) */ - u32 tcpa:1; /* bit 3(TCP checksum assist) */ - u32 ipp:1; /* bit 2(IP checksum pass) */ - u32 ipa:1; /* bit 1(IP checksum assist) */ - u32 hp:1; /* bit 0(hash pass) */ -#else - u32 hp:1; /* bit 0(hash pass) */ - u32 ipa:1; /* bit 1(IP checksum assist) */ - u32 ipp:1; /* bit 2(IP checksum pass) */ - u32 tcpa:1; /* bit 3(TCP checksum assist) */ - u32 tcpp:1; /* bit 4(TCP checksum pass) */ - u32 wol:1; /* bit 5(WOL Event) */ - u32 rxmac_error:1; /* bit 6(RXMAC Error Indicator) */ - u32 drop:1; /* bit 7(Drop packet) */ - u32 ft:1; /* bit 8(Frame Truncated) */ - u32 jp:1; /* bit 9(Jumbo Packet) */ - u32 vp:1; /* bit 10(VLAN Packet) */ - u32 unused:5; /* bits 11-15 */ - u32 asw_prev_pkt_dropped:1;/* bit 16(e.g. IFG too small on previous) */ - u32 asw_RX_DV_event:1; /* bit 17(short receive event detected) */ - u32 asw_false_carrier_event:1; /* bit 18(bad carrier since last good packet) */ - u32 asw_code_err:1; /* bit 19(one or more nibbles signalled as errors) */ - u32 asw_CRC_err:1; /* bit 20(CRC error) */ - u32 asw_len_chk_err:1; /* bit 21(frame length field incorrect) */ - u32 asw_too_long:1; /* bit 22(frame length > 1518 bytes) */ - u32 asw_OK:1; /* bit 23(valid CRC + no code error) */ - u32 asw_multicast:1; /* bit 24(has a multicast address) */ - u32 asw_broadcast:1; /* bit 25(has a broadcast address) */ - u32 asw_dribble_nibble:1; /* bit 26(spurious bits after EOP) */ - u32 asw_control_frame:1; /* bit 27(is a control frame) */ - u32 asw_pause_frame:1; /* bit 28(is a pause frame) */ - u32 asw_unsupported_op:1; /* bit 29(unsupported OP code) */ - u32 asw_VLAN_tag:1; /* bit 30(VLAN tag detected) */ - u32 asw_long_evt:1; /* bit 31(Rx long event) */ -#if 0 - u32 asw_trunc:1; /* bit 31(Rx frame truncated) */ -#endif -#endif - } bits; -} PKT_STAT_DESC_WORD0_t, *PPKT_STAT_WORD0_t; + u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */ +}; -typedef union _PKT_STAT_DESC_WORD1_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 unused:4; /* bits 28-31 */ - u32 ri:2; /* bits 26-27(Ring Index) */ - u32 bi:10; /* bits 16-25(Buffer Index) */ - u32 length:16; /* bit 0-15(length in bytes) */ -#else - u32 length:16; /* bit 0-15(length in bytes) */ - u32 bi:10; /* bits 16-25(Buffer Index) */ - u32 ri:2; /* bits 26-27(Ring Index) */ - u32 unused:4; /* bits 28-31 */ -#endif - } bits; -} PKT_STAT_DESC_WORD1_t, *PPKT_STAT_WORD1_t; +/* Packet Status Ring Descriptors + * + * Word 0: + * + * top 16 bits are from the Alcatel Status Word as enumerated in + * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2) + * + * 0: hp hash pass + * 1: ipa IP checksum assist + * 2: ipp IP checksum pass + * 3: tcpa TCP checksum assist + * 4: tcpp TCP checksum pass + * 5: wol WOL Event + * 6: rxmac_error RXMAC Error Indicator + * 7: drop Drop packet + * 8: ft Frame Truncated + * 9: jp Jumbo Packet + * 10: vp VLAN Packet + * 11-15: unused + * 16: asw_prev_pkt_dropped e.g. IFG too small on previous + * 17: asw_RX_DV_event short receive event detected + * 18: asw_false_carrier_event bad carrier since last good packet + * 19: asw_code_err one or more nibbles signalled as errors + * 20: asw_CRC_err CRC error + * 21: asw_len_chk_err frame length field incorrect + * 22: asw_too_long frame length > 1518 bytes + * 23: asw_OK valid CRC + no code error + * 24: asw_multicast has a multicast address + * 25: asw_broadcast has a broadcast address + * 26: asw_dribble_nibble spurious bits after EOP + * 27: asw_control_frame is a control frame + * 28: asw_pause_frame is a pause frame + * 29: asw_unsupported_op unsupported OP code + * 30: asw_VLAN_tag VLAN tag detected + * 31: asw_long_evt Rx long event + * + * Word 1: + * 0-15: length length in bytes + * 16-25: bi Buffer Index + * 26-27: ri Ring Index + * 28-31: reserved + */ -typedef struct _PKT_STAT_DESC_t { - PKT_STAT_DESC_WORD0_t word0; - PKT_STAT_DESC_WORD1_t word1; -} PKT_STAT_DESC_t, *PPKT_STAT_DESC_t; +struct pkt_stat_desc { + u32 word0; + u32 word1; +}; /* Typedefs for the RX DMA status word */ @@ -223,59 +163,38 @@ typedef struct _PKT_STAT_DESC_t { * RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word * which contains the Packet Status Ring available offset. + * + * bit 0-15 reserved + * bit 16-27 PSRoffset + * bit 28 PSRwrap + * bit 29-31 unused */ -#define RXSTAT1_OFFSET 16 -#define RXSTAT1_MASK 0xFFF -#define RXSTAT1_WRAP 0x10000000 - -typedef union _rxstat_word1_t { - u32 value; - struct { -#ifdef _BIT_FIELDS_HTOL - u32 PSRunused:3; /* bits 29-31 */ - u32 PSRwrap:1; /* bit 28 */ - u32 PSRoffset:12; /* bits 16-27 */ - u32 reserved:16; /* bits 0-15 */ -#else - u32 reserved:16; /* bits 0-15 */ - u32 PSRoffset:12; /* bits 16-27 */ - u32 PSRwrap:1; /* bit 28 */ - u32 PSRunused:3; /* bits 29-31 */ -#endif - } bits; -} RXSTAT_WORD1_t, *PRXSTAT_WORD1_t; - /* - * RX_STATUS_BLOCK_t is sructure representing the status of the Rx DMA engine - * it sits in free memory, and is pointed to by 0x101c / 0x1020 + * struct rx_status_block is a structure representing the status of the Rx + * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020 */ -typedef struct _rx_status_block_t { +struct rx_status_block { u32 Word0; - RXSTAT_WORD1_t Word1; -} RX_STATUS_BLOCK_t, *PRX_STATUS_BLOCK_t; + u32 Word1; +}; /* * Structure for look-up table holding free buffer ring pointers */ -typedef struct _FbrLookupTable { - void *Va[MAX_DESC_PER_RING_RX]; - void *Buffer1[MAX_DESC_PER_RING_RX]; - void *Buffer2[MAX_DESC_PER_RING_RX]; - u32 PAHigh[MAX_DESC_PER_RING_RX]; - u32 PALow[MAX_DESC_PER_RING_RX]; -} FBRLOOKUPTABLE, *PFBRLOOKUPTABLE; - -typedef enum { - ONE_PACKET_INTERRUPT, - FOUR_PACKET_INTERRUPT -} eRX_INTERRUPT_STATE_t, *PeRX_INTERRUPT_STATE_t; +struct fbr_lookup { + void *virt[MAX_DESC_PER_RING_RX]; + void *buffer1[MAX_DESC_PER_RING_RX]; + void *buffer2[MAX_DESC_PER_RING_RX]; + u32 bus_high[MAX_DESC_PER_RING_RX]; + u32 bus_low[MAX_DESC_PER_RING_RX]; +}; /* - * RX_RING_t is sructure representing the adaptor's local reference(s) to the - * rings + * struct rx_ring is the ssructure representing the adaptor's local + * reference(s) to the rings */ -typedef struct _rx_ring_t { +struct rx_ring { #ifdef USE_FBR0 void *pFbr0RingVa; dma_addr_t pFbr0RingPa; @@ -293,7 +212,7 @@ typedef struct _rx_ring_t { dma_addr_t Fbr1MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS]; uint64_t Fbr1Realpa; uint64_t Fbr1offset; - FBRLOOKUPTABLE *Fbr[2]; + struct fbr_lookup *fbr[2]; /* One per ring */ u32 local_Fbr1_full; u32 Fbr1NumEntries; u32 Fbr1BufferSize; @@ -303,8 +222,8 @@ typedef struct _rx_ring_t { u32 local_psr_full; u32 PsrNumEntries; - void *pRxStatusVa; - dma_addr_t pRxStatusPa; + struct rx_status_block *rx_status_block; + dma_addr_t rx_status_bus; struct list_head RecvBufferPool; @@ -320,30 +239,6 @@ typedef struct _rx_ring_t { /* lookaside lists */ struct kmem_cache *RecvLookaside; -} RX_RING_t, *PRX_RING_t; - -/* Forward reference of RFD */ -struct _MP_RFD; - -/* Forward declaration of the private adapter structure */ -struct et131x_adapter; - -/* PROTOTYPES for Initialization */ -int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter); -void et131x_rx_dma_memory_free(struct et131x_adapter *adapter); -int et131x_rfd_resources_alloc(struct et131x_adapter *adapter, - struct _MP_RFD *pMpRfd); -void et131x_rfd_resources_free(struct et131x_adapter *adapter, - struct _MP_RFD *pMpRfd); -int et131x_init_recv(struct et131x_adapter *adapter); - -void ConfigRxDmaRegs(struct et131x_adapter *adapter); -void SetRxDmaTimer(struct et131x_adapter *adapter); -void et131x_rx_dma_disable(struct et131x_adapter *adapter); -void et131x_rx_dma_enable(struct et131x_adapter *adapter); - -void et131x_reset_recv(struct et131x_adapter *adapter); - -void et131x_handle_recv_interrupt(struct et131x_adapter *adapter); +}; #endif /* __ET1310_RX_H__ */ diff --git a/drivers/staging/et131x/et1310_tx.c b/drivers/staging/et131x/et1310_tx.c index 977e8b34e7a..b6ff20f47de 100644 --- a/drivers/staging/et131x/et1310_tx.c +++ b/drivers/staging/et131x/et1310_tx.c @@ -84,15 +84,9 @@ #include <linux/ioport.h> #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" - #include "et131x_adapter.h" -#include "et131x_initpci.h" -#include "et131x_isr.h" - #include "et1310_tx.h" - +#include "et131x.h" static inline void et131x_free_send_packet(struct et131x_adapter *etdev, struct tcb *tcb); @@ -200,7 +194,7 @@ void et131x_tx_dma_memory_free(struct et131x_adapter *adapter) */ void ConfigTxDmaRegs(struct et131x_adapter *etdev) { - struct _TXDMA_t __iomem *txdma = &etdev->regs->txdma; + struct txdma_regs __iomem *txdma = &etdev->regs->txdma; /* Load the hardware with the start of the transmit descriptor ring. */ writel((u32) ((u64)etdev->tx_ring.tx_desc_ring_pa >> 32), diff --git a/drivers/staging/et131x/et1310_tx.h b/drivers/staging/et131x/et1310_tx.h index 4f0ea81978f..82d06e9870d 100644 --- a/drivers/staging/et131x/et1310_tx.h +++ b/drivers/staging/et131x/et1310_tx.h @@ -147,18 +147,4 @@ struct tx_ring { int since_irq; }; -/* Forward declaration of the private adapter structure */ -struct et131x_adapter; - -/* PROTOTYPES for et1310_tx.c */ -int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter); -void et131x_tx_dma_memory_free(struct et131x_adapter *adapter); -void ConfigTxDmaRegs(struct et131x_adapter *adapter); -void et131x_init_send(struct et131x_adapter *adapter); -void et131x_tx_dma_disable(struct et131x_adapter *adapter); -void et131x_tx_dma_enable(struct et131x_adapter *adapter); -void et131x_handle_send_interrupt(struct et131x_adapter *adapter); -void et131x_free_busy_send_packets(struct et131x_adapter *adapter); -int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev); - #endif /* __ET1310_TX_H__ */ diff --git a/drivers/staging/et131x/et131x.h b/drivers/staging/et131x/et131x.h new file mode 100644 index 00000000000..a8abfe6ca81 --- /dev/null +++ b/drivers/staging/et131x/et131x.h @@ -0,0 +1,153 @@ +/* + * Merged from files + * + * Copyright © 2005 Agere Systems Inc. + * All rights reserved. + * http://www.agere.com + * + * SOFTWARE LICENSE + * + * This software is provided subject to the following terms and conditions, + * which you should read carefully before using the software. Using this + * software indicates your acceptance of these terms and conditions. If you do + * not agree with these terms and conditions, do not use the software. + * + * Copyright © 2005 Agere Systems Inc. + * All rights reserved. + * + * Redistribution and use in source or binary forms, with or without + * modifications, are permitted provided that the following conditions are met: + * + * . Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following Disclaimer as comments in the code as + * well as in the documentation and/or other materials provided with the + * distribution. + * + * . Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following Disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * . Neither the name of Agere Systems Inc. nor the names of the contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * Disclaimer + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY + * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN + * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * + */ + +/* et131x_eeprom.c */ +int et131x_init_eeprom(struct et131x_adapter *etdev); + +/* et131x_initpci.c */ +void ConfigGlobalRegs(struct et131x_adapter *pAdapter); +void ConfigMMCRegs(struct et131x_adapter *pAdapter); +void et131x_enable_interrupts(struct et131x_adapter *adapter); +void et131x_disable_interrupts(struct et131x_adapter *adapter); +void et131x_align_allocated_memory(struct et131x_adapter *adapter, + u64 *phys_addr, + u64 *offset, u64 mask); + +int et131x_adapter_setup(struct et131x_adapter *adapter); +int et131x_adapter_memory_alloc(struct et131x_adapter *adapter); +void et131x_adapter_memory_free(struct et131x_adapter *adapter); +void et131x_hwaddr_init(struct et131x_adapter *adapter); +void et131x_soft_reset(struct et131x_adapter *adapter); + +/* et131x_isr.c */ +irqreturn_t et131x_isr(int irq, void *dev_id); +void et131x_isr_handler(struct work_struct *work); + +/* et1310_mac.c */ +void ConfigMACRegs1(struct et131x_adapter *adapter); +void ConfigMACRegs2(struct et131x_adapter *adapter); +void ConfigRxMacRegs(struct et131x_adapter *adapter); +void ConfigTxMacRegs(struct et131x_adapter *adapter); +void ConfigMacStatRegs(struct et131x_adapter *adapter); +void ConfigFlowControl(struct et131x_adapter *adapter); +void UpdateMacStatHostCounters(struct et131x_adapter *adapter); +void HandleMacStatInterrupt(struct et131x_adapter *adapter); +void SetupDeviceForMulticast(struct et131x_adapter *adapter); +void SetupDeviceForUnicast(struct et131x_adapter *adapter); + +/* et131x_netdev.c */ +struct net_device *et131x_device_alloc(void); + +/* et131x_pm.c */ +void EnablePhyComa(struct et131x_adapter *adapter); +void DisablePhyComa(struct et131x_adapter *adapter); + +/* et131x_phy.c */ +void ET1310_PhyInit(struct et131x_adapter *adapter); +void ET1310_PhyReset(struct et131x_adapter *adapter); +void ET1310_PhyPowerDown(struct et131x_adapter *adapter, bool down); +void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *adapter, + u16 duplex); +void ET1310_PhyAccessMiBit(struct et131x_adapter *adapter, + u16 action, + u16 regnum, u16 bitnum, u8 *value); + +int et131x_xcvr_find(struct et131x_adapter *adapter); +void et131x_setphy_normal(struct et131x_adapter *adapter); + +/* static inline function does not work because et131x_adapter is not always + * defined + */ +int PhyMiRead(struct et131x_adapter *adapter, u8 xcvrAddr, + u8 xcvrReg, u16 *value); +#define MiRead(adapter, xcvrReg, value) \ + PhyMiRead((adapter), (adapter)->Stats.xcvr_addr, (xcvrReg), (value)) + +int32_t MiWrite(struct et131x_adapter *adapter, + u8 xcvReg, u16 value); +void et131x_Mii_check(struct et131x_adapter *pAdapter, + MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints); + +/* This last is not strictly required (the driver could call the TPAL + * version instead), but this sets the adapter up correctly, and calls the + * access routine indirectly. This protects the driver from changes in TPAL. + */ +void SetPhy_10BaseTHalfDuplex(struct et131x_adapter *adapter); + + +/* et1310_rx.c */ +int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter); +void et131x_rx_dma_memory_free(struct et131x_adapter *adapter); +int et131x_rfd_resources_alloc(struct et131x_adapter *adapter, + struct _MP_RFD *pMpRfd); +void et131x_rfd_resources_free(struct et131x_adapter *adapter, + struct _MP_RFD *pMpRfd); +int et131x_init_recv(struct et131x_adapter *adapter); + +void ConfigRxDmaRegs(struct et131x_adapter *adapter); +void SetRxDmaTimer(struct et131x_adapter *adapter); +void et131x_rx_dma_disable(struct et131x_adapter *adapter); +void et131x_rx_dma_enable(struct et131x_adapter *adapter); + +void et131x_reset_recv(struct et131x_adapter *adapter); + +void et131x_handle_recv_interrupt(struct et131x_adapter *adapter); + +/* et131x_tx.c */ +int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter); +void et131x_tx_dma_memory_free(struct et131x_adapter *adapter); +void ConfigTxDmaRegs(struct et131x_adapter *adapter); +void et131x_init_send(struct et131x_adapter *adapter); +void et131x_tx_dma_disable(struct et131x_adapter *adapter); +void et131x_tx_dma_enable(struct et131x_adapter *adapter); +void et131x_handle_send_interrupt(struct et131x_adapter *adapter); +void et131x_free_busy_send_packets(struct et131x_adapter *adapter); +int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev); + diff --git a/drivers/staging/et131x/et131x_adapter.h b/drivers/staging/et131x/et131x_adapter.h index 3f7f37a56b6..64a678fcb60 100644 --- a/drivers/staging/et131x/et131x_adapter.h +++ b/drivers/staging/et131x/et131x_adapter.h @@ -77,38 +77,11 @@ */ #define NUM_TRAFFIC_CLASSES 1 -/* - * There are three ways of counting errors - if there are more than X errors - * in Y packets (represented by the "SAMPLE" macros), if there are more than - * N errors in a S mSec time period (the "PERIOD" macros), or if there are - * consecutive packets with errors (CONSEC_ERRORED_THRESH). This last covers - * for "Bursty" errors, and the errored packets may well not be contiguous, - * but several errors where the packet counter has changed by less than a - * small amount will cause this count to increment. - */ -#define TX_PACKETS_IN_SAMPLE 10000 -#define TX_MAX_ERRORS_IN_SAMPLE 50 - #define TX_ERROR_PERIOD 1000 -#define TX_MAX_ERRORS_IN_PERIOD 10 - -#define LINK_DETECTION_TIMER 5000 - -#define TX_CONSEC_RANGE 5 -#define TX_CONSEC_ERRORED_THRESH 10 #define LO_MARK_PERCENT_FOR_PSR 15 #define LO_MARK_PERCENT_FOR_RX 15 -/* Counters for error rate monitoring */ -typedef struct _MP_ERR_COUNTERS { - u32 PktCountTxPackets; - u32 PktCountTxErrors; - u32 TimerBasedTxErrors; - u32 PktCountLastError; - u32 ErredConsecPackets; -} MP_ERR_COUNTERS, *PMP_ERR_COUNTERS; - /* RFD (Receive Frame Descriptor) */ typedef struct _MP_RFD { struct list_head list_node; @@ -174,6 +147,20 @@ typedef struct _ce_stats_t { u32 InterruptStatus; } CE_STATS_t, *PCE_STATS_t; +typedef struct _MP_POWER_MGMT { + /* variable putting the phy into coma mode when boot up with no cable + * plugged in after 5 seconds + */ + u8 TransPhyComaModeOnBoot; + + /* Next two used to save power information at power down. This + * information will be used during power up to set up parts of Power + * Management in JAGCore + */ + u16 PowerDownSpeed; + u8 PowerDownDuplex; +} MP_POWER_MGMT, *PMP_POWER_MGMT; + /* The private adapter structure */ struct et131x_adapter { struct net_device *netdev; @@ -248,7 +235,7 @@ struct et131x_adapter { struct tx_ring tx_ring; /* Rx Memory Variables */ - RX_RING_t RxRing; + struct rx_ring rx_ring; /* Loopback specifics */ u8 ReplicaPhyLoopbk; /* Replica Enable */ diff --git a/drivers/staging/et131x/et131x_config.h b/drivers/staging/et131x/et131x_config.h deleted file mode 100644 index 642c0f6dd6f..00000000000 --- a/drivers/staging/et131x/et131x_config.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Agere Systems Inc. - * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * http://www.agere.com - * - *------------------------------------------------------------------------------ - * - * et131x_config.h - Defines, structs, enums, prototypes, etc. to support - * et131x_config.c - * - *------------------------------------------------------------------------------ - * - * SOFTWARE LICENSE - * - * This software is provided subject to the following terms and conditions, - * which you should read carefully before using the software. Using this - * software indicates your acceptance of these terms and conditions. If you do - * not agree with these terms and conditions, do not use the software. - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * - * Redistribution and use in source or binary forms, with or without - * modifications, are permitted provided that the following conditions are met: - * - * . Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following Disclaimer as comments in the code as - * well as in the documentation and/or other materials provided with the - * distribution. - * - * . Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following Disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * . Neither the name of Agere Systems Inc. nor the names of the contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * Disclaimer - * - * THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY - * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN - * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * - */ - -#ifndef __ET131X_CONFIG_H__ -#define __ET131X_CONFIG_H__ - -/* Forward declaration of the private adapter structure */ -struct et131x_adapter; - -void et131x_config_parse(struct et131x_adapter *adapter); - -#endif /* __ET131X_CONFIG_H__ */ diff --git a/drivers/staging/et131x/et131x_initpci.c b/drivers/staging/et131x/et131x_initpci.c index 0892b6a538d..5ad7e5a6f63 100644 --- a/drivers/staging/et131x/et131x_initpci.c +++ b/drivers/staging/et131x/et131x_initpci.c @@ -87,20 +87,16 @@ #include <linux/random.h> #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" #include "et131x_adapter.h" -#include "et131x_netdev.h" -#include "et131x_config.h" -#include "et131x_isr.h" #include "et1310_address_map.h" #include "et1310_tx.h" #include "et1310_rx.h" -#include "et1310_mac.h" -#include "et1310_eeprom.h" +#include "et131x.h" +#define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */ +#define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */ /* Defines for Parameter Default/Min/Max vaules */ #define PARM_SPEED_DUPLEX_MIN 0 @@ -327,7 +323,7 @@ void et131x_link_detection_handler(unsigned long data) */ void ConfigGlobalRegs(struct et131x_adapter *etdev) { - struct _GLOBAL_t __iomem *regs = &etdev->regs->global; + struct global_regs __iomem *regs = &etdev->regs->global; writel(0, ®s->rxq_start_addr); writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr); diff --git a/drivers/staging/et131x/et131x_initpci.h b/drivers/staging/et131x/et131x_initpci.h deleted file mode 100644 index 7269569a874..00000000000 --- a/drivers/staging/et131x/et131x_initpci.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Agere Systems Inc. - * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * http://www.agere.com - * - *------------------------------------------------------------------------------ - * - * et131x_initpci.h - Header which includes common data and function prototypes - * related to the driver's PCI (and PCI Express) information. - * - *------------------------------------------------------------------------------ - * - * SOFTWARE LICENSE - * - * This software is provided subject to the following terms and conditions, - * which you should read carefully before using the software. Using this - * software indicates your acceptance of these terms and conditions. If you do - * not agree with these terms and conditions, do not use the software. - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * - * Redistribution and use in source or binary forms, with or without - * modifications, are permitted provided that the following conditions are met: - * - * . Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following Disclaimer as comments in the code as - * well as in the documentation and/or other materials provided with the - * distribution. - * - * . Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following Disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * . Neither the name of Agere Systems Inc. nor the names of the contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * Disclaimer - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY - * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN - * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * - */ - -#ifndef __ET131X_INITPCI_H__ -#define __ET131X_INITPCI_H__ - -/* Function Prototypes */ -void et131x_align_allocated_memory(struct et131x_adapter *adapter, - u64 *phys_addr, - u64 *offset, u64 mask); - -int et131x_adapter_setup(struct et131x_adapter *adapter); -int et131x_adapter_memory_alloc(struct et131x_adapter *adapter); -void et131x_adapter_memory_free(struct et131x_adapter *adapter); -void et131x_hwaddr_init(struct et131x_adapter *adapter); -void et131x_soft_reset(struct et131x_adapter *adapter); - -#endif /* __ET131X_INITPCI_H__ */ diff --git a/drivers/staging/et131x/et131x_isr.c b/drivers/staging/et131x/et131x_isr.c index f6d452dd14e..8b6e0b7ec56 100644 --- a/drivers/staging/et131x/et131x_isr.c +++ b/drivers/staging/et131x/et131x_isr.c @@ -85,11 +85,27 @@ #include <linux/ioport.h> #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" -#include "et1310_mac.h" - #include "et131x_adapter.h" +#include "et131x.h" + +/* + * For interrupts, normal running is: + * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt, + * watchdog_interrupt & txdma_xfer_done + * + * In both cases, when flow control is enabled for either Tx or bi-direction, + * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the + * buffer rings are running low. + */ +#define INT_MASK_DISABLE 0xffffffff + +/* NOTE: Masking out MAC_STAT Interrupt for now... + * #define INT_MASK_ENABLE 0xfff6bf17 + * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7 + */ +#define INT_MASK_ENABLE 0xfffebf17 +#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7 + /** * et131x_enable_interrupts - enable interrupt @@ -185,7 +201,7 @@ irqreturn_t et131x_isr(int irq, void *dev_id) if (++tcb->stale > 1) status |= ET_INTR_TXDMA_ISR; - if (adapter->RxRing.UnfinishedReceives) + if (adapter->rx_ring.UnfinishedReceives) status |= ET_INTR_RXDMA_XFR_DONE; else if (tcb == NULL) writel(0, &adapter->regs->global.watchdog_timer); @@ -390,7 +406,7 @@ void et131x_isr_handler(struct work_struct *work) /* Let's move on to the TxMac */ if (status & ET_INTR_TXMAC) { - u32 err = readl(&iomem->txmac.err.value); + u32 err = readl(&iomem->txmac.err); /* * When any of the errors occur and TXMAC generates @@ -425,12 +441,12 @@ void et131x_isr_handler(struct work_struct *work) dev_warn(&etdev->pdev->dev, "RXMAC interrupt, error 0x%08x. Requesting reset\n", - readl(&iomem->rxmac.err_reg.value)); + readl(&iomem->rxmac.err_reg)); dev_warn(&etdev->pdev->dev, "Enable 0x%08x, Diag 0x%08x\n", - readl(&iomem->rxmac.ctrl.value), - readl(&iomem->rxmac.rxq_diag.value)); + readl(&iomem->rxmac.ctrl), + readl(&iomem->rxmac.rxq_diag)); /* * If we are debugging, we want to see this error, diff --git a/drivers/staging/et131x/et131x_isr.h b/drivers/staging/et131x/et131x_isr.h deleted file mode 100644 index 906d57727e2..00000000000 --- a/drivers/staging/et131x/et131x_isr.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Agere Systems Inc. - * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * http://www.agere.com - * - *------------------------------------------------------------------------------ - * - * et131x_isr.h - Defines, structs, enums, prototypes, etc. pertaining to the - * ISR processing code. - * - *------------------------------------------------------------------------------ - * - * SOFTWARE LICENSE - * - * This software is provided subject to the following terms and conditions, - * which you should read carefully before using the software. Using this - * software indicates your acceptance of these terms and conditions. If you do - * not agree with these terms and conditions, do not use the software. - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * - * Redistribution and use in source or binary forms, with or without - * modifications, are permitted provided that the following conditions are met: - * - * . Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following Disclaimer as comments in the code as - * well as in the documentation and/or other materials provided with the - * distribution. - * - * . Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following Disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * . Neither the name of Agere Systems Inc. nor the names of the contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * Disclaimer - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY - * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN - * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * - */ - -#ifndef __ET131X_ISR_H__ -#define __ET131X_ISR_H__ - -irqreturn_t et131x_isr(int irq, void *dev_id); -void et131x_isr_handler(struct work_struct *work); - -#endif /* __ET131X_ISR_H__ */ diff --git a/drivers/staging/et131x/et131x_netdev.c b/drivers/staging/et131x/et131x_netdev.c index edb78ae9e59..40f8954dde4 100644 --- a/drivers/staging/et131x/et131x_netdev.c +++ b/drivers/staging/et131x/et131x_netdev.c @@ -85,14 +85,9 @@ #include <linux/ioport.h> #include "et1310_phy.h" -#include "et1310_pm.h" -#include "et1310_jagcore.h" -#include "et1310_mac.h" #include "et1310_tx.h" - #include "et131x_adapter.h" -#include "et131x_isr.h" -#include "et131x_initpci.h" +#include "et131x.h" struct net_device_stats *et131x_stats(struct net_device *netdev); int et131x_open(struct net_device *netdev); @@ -339,66 +334,64 @@ int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf, int cmd) * et131x_set_packet_filter - Configures the Rx Packet filtering on the device * @adapter: pointer to our private adapter structure * + * FIXME: lot of dups with MAC code + * * Returns 0 on success, errno on failure */ int et131x_set_packet_filter(struct et131x_adapter *adapter) { int status = 0; uint32_t filter = adapter->PacketFilter; - RXMAC_CTRL_t ctrl; - RXMAC_PF_CTRL_t pf_ctrl; + u32 ctrl; + u32 pf_ctrl; - ctrl.value = readl(&adapter->regs->rxmac.ctrl.value); - pf_ctrl.value = readl(&adapter->regs->rxmac.pf_ctrl.value); + ctrl = readl(&adapter->regs->rxmac.ctrl); + pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl); /* Default to disabled packet filtering. Enable it in the individual * case statements that require the device to filter something */ - ctrl.bits.pkt_filter_disable = 1; + ctrl |= 0x04; /* Set us to be in promiscuous mode so we receive everything, this * is also true when we get a packet filter of 0 */ - if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0) { - pf_ctrl.bits.filter_broad_en = 0; - pf_ctrl.bits.filter_multi_en = 0; - pf_ctrl.bits.filter_uni_en = 0; - } else { + if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0) + pf_ctrl &= ~7; /* Clear filter bits */ + else { /* * Set us up with Multicast packet filtering. Three cases are * possible - (1) we have a multi-cast list, (2) we receive ALL * multicast entries or (3) we receive none. */ - if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST) { - pf_ctrl.bits.filter_multi_en = 0; - } else { + if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST) + pf_ctrl &= ~2; /* Multicast filter bit */ + else { SetupDeviceForMulticast(adapter); - pf_ctrl.bits.filter_multi_en = 1; - ctrl.bits.pkt_filter_disable = 0; + pf_ctrl |= 2; + ctrl &= ~0x04; } /* Set us up with Unicast packet filtering */ if (filter & ET131X_PACKET_TYPE_DIRECTED) { SetupDeviceForUnicast(adapter); - pf_ctrl.bits.filter_uni_en = 1; - ctrl.bits.pkt_filter_disable = 0; + pf_ctrl |= 4; + ctrl &= ~0x04; } /* Set us up with Broadcast packet filtering */ if (filter & ET131X_PACKET_TYPE_BROADCAST) { - pf_ctrl.bits.filter_broad_en = 1; - ctrl.bits.pkt_filter_disable = 0; - } else { - pf_ctrl.bits.filter_broad_en = 0; - } + pf_ctrl |= 1; /* Broadcast filter bit */ + ctrl &= ~0x04; + } else + pf_ctrl &= ~1; /* Setup the receive mac configuration registers - Packet * Filter control + the enable / disable for packet filter * in the control reg. */ - writel(pf_ctrl.value, - &adapter->regs->rxmac.pf_ctrl.value); - writel(ctrl.value, &adapter->regs->rxmac.ctrl.value); + writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl); + writel(ctrl, &adapter->regs->rxmac.ctrl); } return status; } @@ -675,12 +668,8 @@ int et131x_set_mac_addr(struct net_device *netdev, void *new_mac) memcpy(netdev->dev_addr, address->sa_data, netdev->addr_len); - printk(KERN_INFO - "%s: Setting MAC address to %02x:%02x:%02x:%02x:%02x:%02x\n", - netdev->name, - netdev->dev_addr[0], netdev->dev_addr[1], - netdev->dev_addr[2], netdev->dev_addr[3], - netdev->dev_addr[4], netdev->dev_addr[5]); + printk(KERN_INFO "%s: Setting MAC address to %pM\n", + netdev->name, netdev->dev_addr); /* Free Rx DMA memory */ et131x_adapter_memory_free(adapter); diff --git a/drivers/staging/et131x/et131x_netdev.h b/drivers/staging/et131x/et131x_netdev.h deleted file mode 100644 index 1eb4a922c01..00000000000 --- a/drivers/staging/et131x/et131x_netdev.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Agere Systems Inc. - * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * http://www.agere.com - * - *------------------------------------------------------------------------------ - * - * et131x_netdev.h - Defines, structs, enums, prototypes, etc. related to the - * driver's net_device support. - * - *------------------------------------------------------------------------------ - * - * SOFTWARE LICENSE - * - * This software is provided subject to the following terms and conditions, - * which you should read carefully before using the software. Using this - * software indicates your acceptance of these terms and conditions. If you do - * not agree with these terms and conditions, do not use the software. - * - * Copyright © 2005 Agere Systems Inc. - * All rights reserved. - * - * Redistribution and use in source or binary forms, with or without - * modifications, are permitted provided that the following conditions are met: - * - * . Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following Disclaimer as comments in the code as - * well as in the documentation and/or other materials provided with the - * distribution. - * - * . Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following Disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * . Neither the name of Agere Systems Inc. nor the names of the contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * Disclaimer - * - * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY - * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN - * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - * - */ - -#ifndef __ET131X_NETDEV_H__ -#define __ET131X_NETDEV_H__ - -struct net_device *et131x_device_alloc(void); - -#endif /* __ET131X_NETDEV_H__ */ diff --git a/drivers/staging/et131x/et131x_version.h b/drivers/staging/et131x/et131x_version.h index 568f6c8c34f..2aa9bda44ac 100644 --- a/drivers/staging/et131x/et131x_version.h +++ b/drivers/staging/et131x/et131x_version.h @@ -62,20 +62,13 @@ #define DRIVER_LICENSE "Dual BSD/GPL" #define DRIVER_DEVICE_STRING "ET1310" #define DRIVER_NAME "et131x" -#define DRIVER_MAJOR_VERSION 1 -#define DRIVER_MINOR_VERSION 2 -#define DRIVER_PATCH_VERSION 3 -#define DRIVER_VERSION_STRING "1.2.3" +#define DRIVER_VERSION_STRING "1.2.3-lk" #define DRIVER_VENDOR "Agere Systems, http://www.agere.com" #define DRIVER_DESC "10/100/1000 Base-T Ethernet Driver" -#define STRUCT_MODULE "net" /* blux: missed by the kernel */ - #define DRIVER_INFO DRIVER_DESC " for the "\ DRIVER_DEVICE_STRING ", v" \ DRIVER_VERSION_STRING " by " \ DRIVER_VENDOR -#define DRIVER_NAME_EXT "et131x.ko" - #endif /* __ET131X_VERSION_H__ */ |