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authorMatthew Wilcox <matthew@wil.cx>2006-10-10 08:01:20 -0600
committerGreg Kroah-Hartman <gregkh@suse.de>2006-12-01 14:36:57 -0800
commitebf5a24829def5d066922ceebde61dd57fdc6b1e (patch)
tree5df978f750d554f2fd2cdd6f5694be943fd80e9f /drivers
parent3efe2d84c8d909567c7976a7106114127b8c3470 (diff)
PCI: Use pci_generic_prep_mwi on sparc64
The setting of the CACHE_LINE_SIZE register in sparc64's pci initialisation code isn't quite adequate as the device may have incompatible requirements. The generic code tests for this, so switch sparc64 over to using it. Since sparc64 has different L1 cache line size and PCI cache line size, it would need to override the generic code like i386 and ia64 do. We know what the cache line size is at compile time though, so introduce a new optional constant PCI_CACHE_LINE_BYTES. Signed-off-by: Matthew Wilcox <matthew@wil.cx> Signed-off-by: David Miller <davem@davemloft.net> Acked-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pci/pci.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 0eaf381ae93..bc88c30a418 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -876,8 +876,14 @@ pci_set_master(struct pci_dev *dev)
}
#ifndef HAVE_ARCH_PCI_MWI
+
+#ifndef PCI_CACHE_LINE_BYTES
+#define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
+#endif
+
/* This can be overridden by arch code. */
-u8 pci_cache_line_size = L1_CACHE_BYTES >> 2;
+/* Don't forget this is measured in 32-bit words, not bytes */
+u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
/**
* pci_generic_prep_mwi - helper function for pci_set_mwi