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authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2006-01-12 16:50:46 -0800
committerJeff Garzik <jgarzik@pobox.com>2006-01-17 07:44:49 -0500
commit526f99572e9f18f42c8da2c9adafbe64482c0737 (patch)
treeb6b76704aa4ca03d3b66eaedb34b3d77237dc7a0 /drivers
parent492731632cce0a7c8817376e1316f0af093830c4 (diff)
[PATCH] e1000: Fix PHY reset when blocked
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: John Ronciak <john.ronciak@intel.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/e1000/e1000_hw.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 45fa386d212..bb9d00e0dc1 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -838,6 +838,11 @@ e1000_setup_link(struct e1000_hw *hw)
DEBUGFUNC("e1000_setup_link");
+ /* In the case of the phy reset being blocked, we already have a link.
+ * We do not have to set it up again. */
+ if (e1000_check_phy_reset_block(hw))
+ return E1000_SUCCESS;
+
/* Read and store word 0x0F of the EEPROM. This word contains bits
* that determine the hardware's default PAUSE (flow control) mode,
* a bit that determines whether the HW defaults to enabling or