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authorDhananjay Phadke <dhananjay@netxen.com>2009-04-07 22:50:48 +0000
committerDavid S. Miller <davem@davemloft.net>2009-04-08 15:58:31 -0700
commitea7eaa39ffadffaa8f1dd1a1f85fa38bf8ae9d39 (patch)
tree4ab24f8e5f47b86933935cec624c4592da78acaf /drivers
parenta92e9e65f0068a291a677c627a747fae1f230284 (diff)
netxen: cache align register map table
Aligning register offset translation table imporves performance on rx side. Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/netxen/netxen_nic_hw.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
index 9439f89869d..3bb2b8c74d9 100644
--- a/drivers/net/netxen/netxen_nic_hw.c
+++ b/drivers/net/netxen/netxen_nic_hw.c
@@ -89,7 +89,8 @@ static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
}
#define CRB_WIN_LOCK_TIMEOUT 100000000
-static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
+static crb_128M_2M_block_map_t
+crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
{{{0, 0, 0, 0} } }, /* 0: PCI */
{{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
{1, 0x0110000, 0x0120000, 0x130000},