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| author | Jeff Garzik <jgarzik@pobox.com> | 2005-11-11 05:51:24 -0500 |
|---|---|---|
| committer | Jeff Garzik <jgarzik@pobox.com> | 2005-11-11 05:51:24 -0500 |
| commit | 3b621ee5df437d3f332a635ab6421aaa61a7dc2b (patch) | |
| tree | c4a5236cee8eb7418770802313d36a55f1cc0b1e /include/asm-arm/arch-realview/entry-macro.S | |
| parent | 7211bb9b64f17b23834d91fc3d0c1d78671ee9a8 (diff) | |
| parent | 5e04e7fe774794b837e1d3897e6b96ae2d06679a (diff) | |
Merge branch 'master'
Diffstat (limited to 'include/asm-arm/arch-realview/entry-macro.S')
| -rw-r--r-- | include/asm-arm/arch-realview/entry-macro.S | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S index 2712ba77bb3..6288fad0dc4 100644 --- a/include/asm-arm/arch-realview/entry-macro.S +++ b/include/asm-arm/arch-realview/entry-macro.S @@ -47,3 +47,28 @@ cmpcs \irqnr, \irqnr .endm + + /* We assume that irqstat (the raw value of the IRQ acknowledge + * register) is preserved from the macro above. + * If there is an IPI, we immediately signal end of interrupt on the + * controller, since this requires the original irqstat value which + * we won't easily be able to recreate later. + */ + + .macro test_for_ipi, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + cmp \irqnr, #16 + strcc \irqstat, [\base, #GIC_CPU_EOI] + cmpcs \irqnr, \irqnr + .endm + + /* As above, this assumes that irqstat and base are preserved.. */ + + .macro test_for_ltirq, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + mov \tmp, #0 + cmp \irqnr, #29 + moveq \tmp, #1 + streq \irqstat, [\base, #GIC_CPU_EOI] + cmp \tmp, #0 + .endm |