diff options
| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-24 17:48:14 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-24 17:48:14 -0700 |
| commit | dfd8317d3340f03bc06eba6b58f0ec0861da4a13 (patch) | |
| tree | 43bd5c93ad045355687c26beb0983fcf6ca18a6b /include/asm-arm/arch-s3c2410/regs-clock.h | |
| parent | 83626b01275d0228516b4d97da008328fc37c934 (diff) | |
| parent | c0897856553d45aee1780bed455b7c2e888dd64b (diff) | |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (25 commits)
[ARM] 3648/1: Update struct ucontext layout for coprocessor registers
[ARM] Add identifying number for non-rt sigframe
[ARM] Gather common sigframe saving code into setup_sigframe()
[ARM] Gather common sigframe restoration code into restore_sigframe()
[ARM] Re-use sigframe within rt_sigframe
[ARM] Merge sigcontext and sigmask members of sigframe
[ARM] Replace extramask with a full copy of the sigmask
[ARM] Remove rt_sigframe puc and pinfo pointers
[ARM] 3647/1: S3C24XX: add Osiris to the list of simtec pm machines
[ARM] 3645/1: S3C2412: irq support for external interrupts
[ARM] 3643/1: S3C2410: Add new usb clocks
[ARM] 3642/1: S3C24XX: Add machine SMDK2413
[ARM] 3641/1: S3C2412: Fixup gpio register naming
[ARM] 3640/1: S3C2412: Use S3C24XX_DCLKCON instead of S3C2410_DCLKCON
[ARM] 3639/1: S3C2412: serial port support
[ARM] 3638/1: S3C2412: core clocks
[ARM] 3637/1: S3C24XX: Add mpll clock, and set as fclk parent
[ARM] 3636/1: S3C2412: Add selection of CPU_ARM926
[ARM] 3635/1: S3C24XX: Add S3C2412 core cpu support
[ARM] 3633/1: S3C24XX: s3c2410 gpio bugfix - wrong pin nos
...
Diffstat (limited to 'include/asm-arm/arch-s3c2410/regs-clock.h')
| -rw-r--r-- | include/asm-arm/arch-s3c2410/regs-clock.h | 63 |
1 files changed, 62 insertions, 1 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h index 6c92faffe98..a7c61feb843 100644 --- a/include/asm-arm/arch-s3c2410/regs-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-clock.h @@ -1,6 +1,6 @@ /* linux/include/asm/arch-s3c2410/regs-clock.h * - * Copyright (c) 2003,2004,2005 Simtec Electronics <linux@simtec.co.uk> + * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk> * http://armlinux.simtec.co.uk/ * * This program is free software; you can redistribute it and/or modify @@ -140,5 +140,66 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) #endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */ +#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) + +#define S3C2412_OSCSET S3C2410_CLKREG(0x18) +#define S3C2412_CLKSRC S3C2410_CLKREG(0x1C) + +#define S3C2412_PLLCON_OFF (1<<20) + +#define S3C2412_CLKDIVN_PDIVN (1<<2) +#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0) +#define S3C2421_CLKDIVN_ARMDIVN (1<<3) +#define S3C2412_CLKDIVN_USB48DIV (1<<6) +#define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8) +#define S3C2412_CLKDIVN_UARTDIV_SHIFT (8) +#define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12) +#define S3C2412_CLKDIVN_I2SDIV_SHIFT (12) +#define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16) +#define S3C2412_CLKDIVN_CAMDIV_SHIFT (16) + +#define S3C2412_CLKCON_WDT (1<<28) +#define S3C2412_CLKCON_SPI (1<<27) +#define S3C2412_CLKCON_IIS (1<<26) +#define S3C2412_CLKCON_IIC (1<<25) +#define S3C2412_CLKCON_ADC (1<<24) +#define S3C2412_CLKCON_RTC (1<<23) +#define S3C2412_CLKCON_GPIO (1<<22) +#define S3C2412_CLKCON_UART2 (1<<21) +#define S3C2412_CLKCON_UART1 (1<<20) +#define S3C2412_CLKCON_UART0 (1<<19) +#define S3C2412_CLKCON_SDI (1<<18) +#define S3C2412_CLKCON_PWMT (1<<17) +#define S3C2412_CLKCON_USBD (1<<16) +#define S3C2412_CLKCON_CAMCLK (1<<15) +#define S3C2412_CLKCON_UARTCLK (1<<14) +/* missing 13 */ +#define S3C2412_CLKCON_USB_HOST48 (1<<12) +#define S3C2412_CLKCON_USB_DEV48 (1<<11) +#define S3C2412_CLKCON_HCLKdiv2 (1<<10) +#define S3C2412_CLKCON_HCLKx2 (1<<9) +#define S3C2412_CLKCON_SDRAM (1<<8) +/* missing 7 */ +#define S3C2412_CLKCON_USBH S3C2410_CLKCON_USBH +#define S3C2412_CLKCON_LCDC S3C2410_CLKCON_LCDC +#define S3C2412_CLKCON_NAND S3C2410_CLKCON_NAND +#define S3C2412_CLKCON_DMA3 (1<<3) +#define S3C2412_CLKCON_DMA2 (1<<2) +#define S3C2412_CLKCON_DMA1 (1<<1) +#define S3C2412_CLKCON_DMA0 (1<<0) + +/* clock sourec controls */ + +#define S3C2412_CLKSRC_EXTCLKDIV_MASK (7 << 0) +#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT (0) +#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV (1<<3) +#define S3C2412_CLKSRC_MSYSCLK_MPLL (1<<4) +#define S3C2412_CLKSRC_USYSCLK_UPLL (1<<5) +#define S3C2412_CLKSRC_UARTCLK_MPLL (1<<8) +#define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9) +#define S3C2412_CLKSRC_USBCLK_HCLK (1<<10) +#define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11) + +#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */ #endif /* __ASM_ARM_REGS_CLOCK */ |