diff options
author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-24 17:48:14 -0700 |
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committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-24 17:48:14 -0700 |
commit | dfd8317d3340f03bc06eba6b58f0ec0861da4a13 (patch) | |
tree | 43bd5c93ad045355687c26beb0983fcf6ca18a6b /include/asm-arm/arch-s3c2410/regs-gpioj.h | |
parent | 83626b01275d0228516b4d97da008328fc37c934 (diff) | |
parent | c0897856553d45aee1780bed455b7c2e888dd64b (diff) |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (25 commits)
[ARM] 3648/1: Update struct ucontext layout for coprocessor registers
[ARM] Add identifying number for non-rt sigframe
[ARM] Gather common sigframe saving code into setup_sigframe()
[ARM] Gather common sigframe restoration code into restore_sigframe()
[ARM] Re-use sigframe within rt_sigframe
[ARM] Merge sigcontext and sigmask members of sigframe
[ARM] Replace extramask with a full copy of the sigmask
[ARM] Remove rt_sigframe puc and pinfo pointers
[ARM] 3647/1: S3C24XX: add Osiris to the list of simtec pm machines
[ARM] 3645/1: S3C2412: irq support for external interrupts
[ARM] 3643/1: S3C2410: Add new usb clocks
[ARM] 3642/1: S3C24XX: Add machine SMDK2413
[ARM] 3641/1: S3C2412: Fixup gpio register naming
[ARM] 3640/1: S3C2412: Use S3C24XX_DCLKCON instead of S3C2410_DCLKCON
[ARM] 3639/1: S3C2412: serial port support
[ARM] 3638/1: S3C2412: core clocks
[ARM] 3637/1: S3C24XX: Add mpll clock, and set as fclk parent
[ARM] 3636/1: S3C2412: Add selection of CPU_ARM926
[ARM] 3635/1: S3C24XX: Add S3C2412 core cpu support
[ARM] 3633/1: S3C24XX: s3c2410 gpio bugfix - wrong pin nos
...
Diffstat (limited to 'include/asm-arm/arch-s3c2410/regs-gpioj.h')
-rw-r--r-- | include/asm-arm/arch-s3c2410/regs-gpioj.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-gpioj.h b/include/asm-arm/arch-s3c2410/regs-gpioj.h index 3ad2324acc3..18edae50d0b 100644 --- a/include/asm-arm/arch-s3c2410/regs-gpioj.h +++ b/include/asm-arm/arch-s3c2410/regs-gpioj.h @@ -32,6 +32,11 @@ #define S3C2440_GPJDAT S3C2410_GPIOREG(0xd4) #define S3C2440_GPJUP S3C2410_GPIOREG(0xd8) +#define S3C2413_GPJCON S3C2410_GPIOREG(0x80) +#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84) +#define S3C2413_GPJUP S3C2410_GPIOREG(0x88) +#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C) + #define S3C2440_GPJ0 S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0) #define S3C2440_GPJ0_INP (0x00 << 0) #define S3C2440_GPJ0_OUTP (0x01 << 0) |