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authorHaavard Skinnemoen <hskinnemoen@atmel.com>2007-01-30 11:16:16 +0100
committerHaavard Skinnemoen <hskinnemoen@atmel.com>2007-02-09 15:01:58 +0100
commit7f9f4678637f9ee1a999cc0870c4668f32e1a7eb (patch)
tree557c08cbc47b9936c3a8c2f550bb3acd8781332e /include/asm-avr32/arch-at32ap
parente7f70b8cc69b1bcc56ed8d70f8e3671ec3956374 (diff)
[AVR32] Add PIOE device and reserve SDRAM pins
The PIOE device was left out before because it muxes SDRAM pins (and is therefore a bit dangerous to mess with) and because no existing drivers had any use for it. It is needed for CompactFlash, however, and now that we have a way to protect the SDRAM pins, it can be safely added. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Diffstat (limited to 'include/asm-avr32/arch-at32ap')
-rw-r--r--include/asm-avr32/arch-at32ap/at32ap7000.h2
-rw-r--r--include/asm-avr32/arch-at32ap/irq.h2
2 files changed, 3 insertions, 1 deletions
diff --git a/include/asm-avr32/arch-at32ap/at32ap7000.h b/include/asm-avr32/arch-at32ap/at32ap7000.h
index ba85e04553d..3914d7b94ff 100644
--- a/include/asm-avr32/arch-at32ap/at32ap7000.h
+++ b/include/asm-avr32/arch-at32ap/at32ap7000.h
@@ -24,10 +24,12 @@
#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
+#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
#define GPIO_PIN_PA(N) (GPIO_PIOA_BASE + (N))
#define GPIO_PIN_PB(N) (GPIO_PIOB_BASE + (N))
#define GPIO_PIN_PC(N) (GPIO_PIOC_BASE + (N))
#define GPIO_PIN_PD(N) (GPIO_PIOD_BASE + (N))
+#define GPIO_PIN_PE(N) (GPIO_PIOE_BASE + (N))
#endif /* __ASM_ARCH_AT32AP7000_H__ */
diff --git a/include/asm-avr32/arch-at32ap/irq.h b/include/asm-avr32/arch-at32ap/irq.h
index f8f7f4571e4..5adffab9a57 100644
--- a/include/asm-avr32/arch-at32ap/irq.h
+++ b/include/asm-avr32/arch-at32ap/irq.h
@@ -7,7 +7,7 @@
#define AT32_EXTINT(n) (EIM_IRQ_BASE + (n))
#define GPIO_IRQ_BASE (EIM_IRQ_BASE + NR_EIM_IRQS)
-#define NR_GPIO_IRQS (4 * 32)
+#define NR_GPIO_IRQS (5 * 32)
#define NR_IRQS (GPIO_IRQ_BASE + NR_GPIO_IRQS)