Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (85 commits)
  Blackfin char driver for Blackfin on-chip OTP memory (v3)
  Blackfin Serial Driver: fix bug - use mod_timer to replace only add_timer.
  Blackfin Serial Driver: the uart break anomaly has been given its own number, so switch to it
  Blackfin Serial Driver: use BFIN_UART_NR_PORTS to help SIR driver in uart port.
  Blackfin Serial Driver: Fix bug - kernel hangs when accessing uart 0 on bf537 when booting u-boot and linux on uart 1
  Blackfin Serial Driver: punt unused lsr variable
  Blackfin Serial Driver: Enable IR function when user application (irattach /dev/ttyBFx -s) call TIOCSETD ioctl with line discipline N_IRDA
  [Blackfin] arch: add include/boot .gitignore files
  [Blackfin] arch: Functional power management support: Add support for cpu frequency scaling
  [Blackfin] arch: Functional power management support: Remove broken cpu frequency scaling drivers
  [Blackfin] arch: Equalize include files: Add PLL_DIV Masks
  [Blackfin] arch: Add a warning about the value of CLKIN.
  [Blackfin] arch: take DDR DEVWD into consideration as well for BF548
  [Blackfin] arch: Remove the circular buffering mechanism for exceptions
  [Blackfin] arch: lose unnecessary dependency on CONFIG_BFIN_ICACHE for MPU
  [Blackfin] arch: fix bug - before assign new channel to the map register, need clear the bits first.
  [Blackfin] arch: add Blackfin on-chip SIR IrDA driver support
  [Blackfin] arch: BF54x memsizes are in mbits, not mbytes
  [Blackfin] arch: try to remove condition that causes double fault, by checking current before it gets dereferenced
  [Blackfin] arch: Update anomaly list.
  ...

1 files changed, 55 insertions, 35 deletions

diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
index 3f4de5d9d4c..9dbdbec8ea1 100644
--- a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
+++ b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
@@ -29,18 +29,71 @@
  */
 
 #ifndef _CDEF_BF52X_H
+#define _CDEF_BF52X_H
+
+#include <asm/system.h>
+#include <asm/blackfin.h>
 
 #include "defBF52x_base.h"
 
+/* Include core specific register pointer definitions 								*/
+#include <asm/mach-common/cdef_LPBlackfin.h>
+
 /* ==== begin from cdefBF534.h ==== */
 
 /* Clock and System Control	(0xFFC00000 - 0xFFC000FF)								*/
 #define bfin_read_PLL_CTL()			bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)			bfin_write16(PLL_CTL, val)
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+	unsigned long flags, iwr0, iwr1;
+
+	if (val == bfin_read_PLL_CTL())
+		return;
+
+	local_irq_save(flags);
+	/* Enable the PLL Wakeup bit in SIC IWR */
+	iwr0 = bfin_read32(SIC_IWR0);
+	iwr1 = bfin_read32(SIC_IWR1);
+	/* Only allow PPL Wakeup) */
+	bfin_write32(SIC_IWR0, IWR_ENABLE(0));
+	bfin_write32(SIC_IWR1, 0);
+
+	bfin_write16(PLL_CTL, val);
+	SSYNC();
+	asm("IDLE;");
+
+	bfin_write32(SIC_IWR0, iwr0);
+	bfin_write32(SIC_IWR1, iwr1);
+	local_irq_restore(flags);
+}
 #define bfin_read_PLL_DIV()			bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)			bfin_write16(PLL_DIV, val)
 #define bfin_read_VR_CTL()			bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)			bfin_write16(VR_CTL, val)
+/* Writing to VR_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_VR_CTL(unsigned int val)
+{
+	unsigned long flags, iwr0, iwr1;
+
+	if (val == bfin_read_VR_CTL())
+		return;
+
+	local_irq_save(flags);
+	/* Enable the PLL Wakeup bit in SIC IWR */
+	iwr0 = bfin_read32(SIC_IWR0);
+	iwr1 = bfin_read32(SIC_IWR1);
+	/* Only allow PPL Wakeup) */
+	bfin_write32(SIC_IWR0, IWR_ENABLE(0));
+	bfin_write32(SIC_IWR1, 0);
+
+	bfin_write16(VR_CTL, val);
+	SSYNC();
+	asm("IDLE;");
+
+	bfin_write32(SIC_IWR0, iwr0);
+	bfin_write32(SIC_IWR1, iwr1);
+	local_irq_restore(flags);
+}
 #define bfin_read_PLL_STAT()			bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)		bfin_write16(PLL_STAT, val)
 #define bfin_read_PLL_LOCKCNT()			bfin_read16(PLL_LOCKCNT)
@@ -873,39 +926,6 @@
 
 
 /* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF)								*/
-#define bfin_read_TWI_CLKDIV()			bfin_read16(TWI_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val)		bfin_write16(TWI_CLKDIV, val)
-#define bfin_read_TWI_CONTROL()			bfin_read16(TWI_CONTROL)
-#define bfin_write_TWI_CONTROL(val)		bfin_write16(TWI_CONTROL, val)
-#define bfin_read_TWI_SLAVE_CTL()		bfin_read16(TWI_SLAVE_CTL)
-#define bfin_write_TWI_SLAVE_CTL(val)		bfin_write16(TWI_SLAVE_CTL, val)
-#define bfin_read_TWI_SLAVE_STAT()		bfin_read16(TWI_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val)		bfin_write16(TWI_SLAVE_STAT, val)
-#define bfin_read_TWI_SLAVE_ADDR()		bfin_read16(TWI_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val)		bfin_write16(TWI_SLAVE_ADDR, val)
-#define bfin_read_TWI_MASTER_CTL()		bfin_read16(TWI_MASTER_CTL)
-#define bfin_write_TWI_MASTER_CTL(val)		bfin_write16(TWI_MASTER_CTL, val)
-#define bfin_read_TWI_MASTER_STAT()		bfin_read16(TWI_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val)		bfin_write16(TWI_MASTER_STAT, val)
-#define bfin_read_TWI_MASTER_ADDR()		bfin_read16(TWI_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val)		bfin_write16(TWI_MASTER_ADDR, val)
-#define bfin_read_TWI_INT_STAT()		bfin_read16(TWI_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val)		bfin_write16(TWI_INT_STAT, val)
-#define bfin_read_TWI_INT_MASK()		bfin_read16(TWI_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val)		bfin_write16(TWI_INT_MASK, val)
-#define bfin_read_TWI_FIFO_CTL()		bfin_read16(TWI_FIFO_CTL)
-#define bfin_write_TWI_FIFO_CTL(val)		bfin_write16(TWI_FIFO_CTL, val)
-#define bfin_read_TWI_FIFO_STAT()		bfin_read16(TWI_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val)		bfin_write16(TWI_FIFO_STAT, val)
-#define bfin_read_TWI_XMT_DATA8()		bfin_read16(TWI_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val)		bfin_write16(TWI_XMT_DATA8, val)
-#define bfin_read_TWI_XMT_DATA16()		bfin_read16(TWI_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val)		bfin_write16(TWI_XMT_DATA16, val)
-#define bfin_read_TWI_RCV_DATA8()		bfin_read16(TWI_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val)		bfin_write16(TWI_RCV_DATA8, val)
-#define bfin_read_TWI_RCV_DATA16()		bfin_read16(TWI_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val)		bfin_write16(TWI_RCV_DATA16, val)
-
 
 /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)								*/
 #define bfin_read_PORTGIO()			bfin_read16(PORTGIO)