diff options
| author | Michael Hennerich <michael.hennerich@analog.com> | 2008-04-24 07:32:41 +0800 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2008-04-24 07:32:41 +0800 |
| commit | a81501af19830ff43688781edad7e9c0cbd668af (patch) | |
| tree | 856be99eb74bfc5e6cf20369b633107d8d4170f6 /include/asm-blackfin/mach-bf533 | |
| parent | 4bea8b20fded93871c872bb4a0d7c23345318184 (diff) | |
[Blackfin] arch: Prevent potential Core Hang situation
If the new value written to the PLL_CTL or VR_CTL register is the
same as the previous value, the PLL wake-up will occur immediately
(PLL is already locked), but the core and system clock will be
bypassed for the PLL_LOCKCNT duration. For this interval, code will
execute at the CLKIN rate instead of at the expected CCLK rate.
Software should guard against this condition by comparing the
current value to the new value before writing the new value.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf533')
| -rw-r--r-- | include/asm-blackfin/mach-bf533/cdefBF532.h | 31 |
1 files changed, 27 insertions, 4 deletions
diff --git a/include/asm-blackfin/mach-bf533/cdefBF532.h b/include/asm-blackfin/mach-bf533/cdefBF532.h index c803e14b529..154655452d4 100644 --- a/include/asm-blackfin/mach-bf533/cdefBF532.h +++ b/include/asm-blackfin/mach-bf533/cdefBF532.h @@ -43,7 +43,27 @@ /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val) +/* Writing to PLL_CTL initiates a PLL relock sequence. */ +static __inline__ void bfin_write_PLL_CTL(unsigned int val) +{ + unsigned long flags, iwr; + + if (val == bfin_read_PLL_CTL()) + return; + + local_irq_save(flags); + /* Enable the PLL Wakeup bit in SIC IWR */ + iwr = bfin_read32(SIC_IWR); + /* Only allow PPL Wakeup) */ + bfin_write32(SIC_IWR, IWR_ENABLE(0)); + + bfin_write16(PLL_CTL, val); + SSYNC(); + asm("IDLE;"); + + bfin_write32(SIC_IWR, iwr); + local_irq_restore(flags); +} #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) @@ -57,6 +77,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) { unsigned long flags, iwr; + if (val == bfin_read_VR_CTL()) + return; + + local_irq_save(flags); /* Enable the PLL Wakeup bit in SIC IWR */ iwr = bfin_read32(SIC_IWR); /* Only allow PPL Wakeup) */ @@ -64,11 +88,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) bfin_write16(VR_CTL, val); SSYNC(); - - local_irq_save(flags); asm("IDLE;"); - local_irq_restore(flags); + bfin_write32(SIC_IWR, iwr); + local_irq_restore(flags); } /* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ |