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authorSonic Zhang <sonic.zhang@analog.com>2008-04-25 03:28:10 +0800
committerBryan Wu <cooloney@kernel.org>2008-04-25 03:28:10 +0800
commit4d555630704d3f6c0257dde3e622f9295f221c8b (patch)
tree8b53f8f2acf44ca00dfe159a79b7c4ed5880795f /include/asm-blackfin/mach-bf561
parent18628e4375264edb53e6d9aaaf91f1a480019304 (diff)
[Blackfin] arch: Update anomaly list.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf561')
-rw-r--r--include/asm-blackfin/mach-bf561/anomaly.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
index 0c1d4619393..82157caa96a 100644
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -7,7 +7,7 @@
*/
/* This file shoule be up to date with:
- * - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List
+ * - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
@@ -256,10 +256,14 @@
#define ANOMALY_05000357 (1)
/* Conflicting Column Address Widths Causes SDRAM Errors */
#define ANOMALY_05000362 (1)
+/* UART Break Signal Issues */
+#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000158 (0)