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authorMike Frysinger <michael.frysinger@analog.com>2007-07-25 11:56:01 +0800
committerBryan Wu <bryan.wu@analog.com>2007-07-25 11:56:01 +0800
commit60e9356d770ca3622fe5e84680b78fc376e53fbf (patch)
treea63ed7658206e9320400c34b4edcd414acf9ac76 /include/asm-blackfin
parent1aafd9091226a02b481298315f959f777294684e (diff)
Blackfin arch: update BF54x anomaly list
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Roy Huang <roy.huang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin')
-rw-r--r--include/asm-blackfin/mach-bf548/anomaly.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
index 952f03e140f..37e0bd22b64 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -27,6 +27,8 @@
#define ANOMALY_05000265 (1)
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1)
+/* False Hardware Error Exception when ISR context is not restored */
+#define ANOMALY_05000281 (1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
@@ -59,6 +61,7 @@
#define ANOMALY_05000183 (0)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000244 (0)
+#define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)