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authorMikael Starvik <mikael.starvik@axis.com>2005-07-27 11:44:34 -0700
committerLinus Torvalds <torvalds@g5.osdl.org>2005-07-27 16:25:59 -0700
commit7e9204265b4ec6680fad9abc7a78b94087983916 (patch)
tree50ff709f7d37193bb56599a4e1646509d8e353ff /include/asm-cris/arch-v10
parent059163cabc01a15b9e2cf10e5de5b6dc06e0da1f (diff)
[PATCH] CRIS update: drivers
Updates to device drivers. * Use I/O and DMA allocators. * Use wait_event_interruptible instead of interrutiple_sleep_on. * Added spinlocks SMP. * Changed restore_flags to local_irq_restore etc. * Updated IDE driver include to fit 2.6.12. Signed-off-by: Mikael Starvik <starvik@axis.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-cris/arch-v10')
-rw-r--r--include/asm-cris/arch-v10/ide.h99
1 files changed, 99 insertions, 0 deletions
diff --git a/include/asm-cris/arch-v10/ide.h b/include/asm-cris/arch-v10/ide.h
new file mode 100644
index 00000000000..8cf2d7cb22a
--- /dev/null
+++ b/include/asm-cris/arch-v10/ide.h
@@ -0,0 +1,99 @@
+/*
+ * linux/include/asm-cris/ide.h
+ *
+ * Copyright (C) 2000, 2001, 2002 Axis Communications AB
+ *
+ * Authors: Bjorn Wesen
+ *
+ */
+
+/*
+ * This file contains the ETRAX 100LX specific IDE code.
+ */
+
+#ifndef __ASMCRIS_IDE_H
+#define __ASMCRIS_IDE_H
+
+#ifdef __KERNEL__
+
+#include <asm/arch/svinto.h>
+#include <asm/io.h>
+#include <asm-generic/ide_iops.h>
+
+
+/* ETRAX 100 can support 4 IDE busses on the same pins (serialized) */
+
+#define MAX_HWIFS 4
+
+extern __inline__ int ide_default_irq(unsigned long base)
+{
+ /* all IDE busses share the same IRQ, number 4.
+ * this has the side-effect that ide-probe.c will cluster our 4 interfaces
+ * together in a hwgroup, and will serialize accesses. this is good, because
+ * we can't access more than one interface at the same time on ETRAX100.
+ */
+ return 4;
+}
+
+extern __inline__ unsigned long ide_default_io_base(int index)
+{
+ /* we have no real I/O base address per interface, since all go through the
+ * same register. but in a bitfield in that register, we have the i/f number.
+ * so we can use the io_base to remember that bitfield.
+ */
+ static const unsigned long io_bases[MAX_HWIFS] = {
+ IO_FIELD(R_ATA_CTRL_DATA, sel, 0),
+ IO_FIELD(R_ATA_CTRL_DATA, sel, 1),
+ IO_FIELD(R_ATA_CTRL_DATA, sel, 2),
+ IO_FIELD(R_ATA_CTRL_DATA, sel, 3)
+ };
+ return io_bases[index];
+}
+
+/* this is called once for each interface, to setup the port addresses. data_port is the result
+ * of the ide_default_io_base call above. ctrl_port will be 0, but that is don't care for us.
+ */
+
+extern __inline__ void ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port, unsigned long ctrl_port, int *irq)
+{
+ int i;
+
+ /* fill in ports for ATA addresses 0 to 7 */
+
+ for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
+ hw->io_ports[i] = data_port |
+ IO_FIELD(R_ATA_CTRL_DATA, addr, i) |
+ IO_STATE(R_ATA_CTRL_DATA, cs0, active);
+ }
+
+ /* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */
+
+ hw->io_ports[IDE_CONTROL_OFFSET] = data_port |
+ IO_FIELD(R_ATA_CTRL_DATA, addr, 6) |
+ IO_STATE(R_ATA_CTRL_DATA, cs1, active);
+
+ /* whats this for ? */
+
+ hw->io_ports[IDE_IRQ_OFFSET] = 0;
+}
+
+extern __inline__ void ide_init_default_hwifs(void)
+{
+ hw_regs_t hw;
+ int index;
+
+ for(index = 0; index < MAX_HWIFS; index++) {
+ ide_init_hwif_ports(&hw, ide_default_io_base(index), 0, NULL);
+ hw.irq = ide_default_irq(ide_default_io_base(index));
+ ide_register_hw(&hw, NULL);
+ }
+}
+
+/* some configuration options we don't need */
+
+#undef SUPPORT_VLB_SYNC
+#define SUPPORT_VLB_SYNC 0
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASMCRIS_IDE_H */