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authorStephane Eranian <eranian@hpl.hp.com>2006-12-07 02:14:11 +0100
committerAndi Kleen <andi@basil.nowhere.org>2006-12-07 02:14:11 +0100
commit538f188e03c821c93b355c9fc346806cdd34e286 (patch)
tree4fa4a37d35444a51a30722a2af8f8f57ea11449d /include/asm-i386
parentee58fad51a2a767cb2567706ace967705233d881 (diff)
[PATCH] i386: i386 add Intel BTS cpufeature bit and detection (take 2)
Here is a small patch for i386 which adds a cpufeature flag and detection code for Intel's Branch Trace Store (BTS) feature. This feature can be found on Intel P4 and Core 2 processors among others. It can also be used by perfmon. changelog: - add CPU_FEATURE_BTS - add Branch Trace Store detection signed-off-by: stephane eranian <eranian@hpl.hp.com> Signed-off-by: Andi Kleen <ak@suse.de>
Diffstat (limited to 'include/asm-i386')
-rw-r--r--include/asm-i386/cpufeature.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h
index 4c83e059228..3f92b94e0d7 100644
--- a/include/asm-i386/cpufeature.h
+++ b/include/asm-i386/cpufeature.h
@@ -74,6 +74,7 @@
#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */
#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
+#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
@@ -138,6 +139,7 @@
#define cpu_has_ds boot_cpu_has(X86_FEATURE_DS)
#define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS)
#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH)
+#define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS)
#endif /* __ASM_I386_CPUFEATURE_H */