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| author | David Woodhouse <dwmw2@infradead.org> | 2006-05-03 13:30:35 +0100 |
|---|---|---|
| committer | David Woodhouse <dwmw2@infradead.org> | 2006-05-03 13:30:35 +0100 |
| commit | edc4ff7c08e9885c40e60c4fb39fa42cc91a0602 (patch) | |
| tree | f375d28043dd4457428a841167dc93d760ba9a46 /include/asm-mips/cpu-info.h | |
| parent | cbb9a56177b16294ed347ba7fcb1c66c8adb5dc4 (diff) | |
| parent | e17df688f7064dae1417ce425dd1e4b71d24d63b (diff) | |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'include/asm-mips/cpu-info.h')
| -rw-r--r-- | include/asm-mips/cpu-info.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h index 140be1c67da..6572ac70366 100644 --- a/include/asm-mips/cpu-info.h +++ b/include/asm-mips/cpu-info.h @@ -73,6 +73,16 @@ struct cpuinfo_mips { struct cache_desc dcache; /* Primary D or combined I/D cache */ struct cache_desc scache; /* Secondary cache */ struct cache_desc tcache; /* Tertiary/split secondary cache */ +#if defined(CONFIG_MIPS_MT_SMTC) + /* + * In the MIPS MT "SMTC" model, each TC is considered + * to be a "CPU" for the purposes of scheduling, but + * exception resources, ASID spaces, etc, are common + * to all TCs within the same VPE. + */ + int vpe_id; /* Virtual Processor number */ + int tc_id; /* Thread Context number */ +#endif /* CONFIG_MIPS_MT */ void *data; /* Additional data */ } __attribute__((aligned(SMP_CACHE_BYTES))); |