diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-10-11 09:19:02 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-10-11 09:19:02 -0700 |
commit | 835a1c092432b3293ba6c4dec45ee6869c6f61fd (patch) | |
tree | a48582e4e4de3a8924b700c5ccaae78cd299cd73 /include/asm-mips/smtc.h | |
parent | d3570a5a7b8d0604fa012129f92637dc1534f62c (diff) | |
parent | 9609e74093abd9f61fb1d20a8915a8ea87c77d5a (diff) |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (49 commits)
MIPS: RB532: provide GPIO_BUILTIN_NR and irq_to_gpio/gpio_to_irq
MIPS: Move ptrace prototypes to ptrace.h
MIPS: Ptrace support for HARDWARE_WATCHPOINTS
MIPS: Scheduler support for HARDWARE_WATCHPOINTS.
MIPS: Watch exception handling for HARDWARE_WATCHPOINTS.
MIPS: Probe watch registers and report configuration.
MIPS: Add HARDWARE_WATCHPOINTS definitions and support code.
MIPS: Add HARDWARE_WATCHPOINTS configure option.
MIPS: Replace use of <asm-generic/uaccess.h> with native implementations.
MIPS: TXx9: Add TX4939 ATA support (v2)
MIPS: Rewrite spinlocks to ticket locks.
MIPS: IP checksums: Optimize adjust of sum on buffers of odd alignment.
MIPS: IP checksums: Remove unncessary .set pseudos
MIPS: IP checksums: Remove unncessary folding of sum to 16 bit.
MIPS: Move headfiles to new location below arch/mips/include
MIPS: Alchemy: rename directory
MIPS: Optimize get_user and put_user for 64-bit
MIPS: TXx9: Implement prom_free_prom_memory
MIPS: TXx9: Add RBTX4939 board support
MIPS: TXx9: Add TX4939 SoC support
...
Diffstat (limited to 'include/asm-mips/smtc.h')
-rw-r--r-- | include/asm-mips/smtc.h | 71 |
1 files changed, 0 insertions, 71 deletions
diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h deleted file mode 100644 index ea60bf08dcb..00000000000 --- a/include/asm-mips/smtc.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef _ASM_SMTC_MT_H -#define _ASM_SMTC_MT_H - -/* - * Definitions for SMTC multitasking on MIPS MT cores - */ - -#include <asm/mips_mt.h> -#include <asm/smtc_ipi.h> - -/* - * System-wide SMTC status information - */ - -extern unsigned int smtc_status; - -#define SMTC_TLB_SHARED 0x00000001 -#define SMTC_MTC_ACTIVE 0x00000002 - -/* - * TLB/ASID Management information - */ - -#define MAX_SMTC_TLBS 2 -#define MAX_SMTC_ASIDS 256 -#if NR_CPUS <= 8 -typedef char asiduse; -#else -#if NR_CPUS <= 16 -typedef short asiduse; -#else -typedef long asiduse; -#endif -#endif - -extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; - -struct mm_struct; -struct task_struct; - -void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu); -void self_ipi(struct smtc_ipi *); -void smtc_flush_tlb_asid(unsigned long asid); -extern int smtc_build_cpu_map(int startslot); -extern void smtc_prepare_cpus(int cpus); -extern void smtc_smp_finish(void); -extern void smtc_boot_secondary(int cpu, struct task_struct *t); -extern void smtc_cpus_done(void); - - -/* - * Sharing the TLB between multiple VPEs means that the - * "random" index selection function is not allowed to - * select the current value of the Index register. To - * avoid additional TLB pressure, the Index registers - * are "parked" with an non-Valid value. - */ - -#define PARKED_INDEX ((unsigned int)0x80000000) - -/* - * Define low-level interrupt mask for IPIs, if necessary. - * By default, use SW interrupt 1, which requires no external - * hardware support, but which works only for single-core - * MIPS MT systems. - */ -#ifndef MIPS_CPU_IPI_IRQ -#define MIPS_CPU_IPI_IRQ 1 -#endif - -#endif /* _ASM_SMTC_MT_H */ |