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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2007-11-25 11:47:56 +0100
committerRalf Baechle <ralf@linux-mips.org>2008-01-29 10:14:58 +0000
commit930bff882296c02ca81db108672ef4ca06c37db5 (patch)
tree53288137d4f7cc02d8ca417edb2b25221c3007cd /include/asm-mips
parent2064ba23e58daa929eec6f5e7a2abc24574a95b9 (diff)
[MIPS] IP28: added cache barrier to assembly routines
IP28 needs special treatment to avoid speculative accesses. gcc takes care for .c code, but for assembly code we need to do it manually. This is taken from Peter Fuersts IP28 patches. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/asm.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h
index 12e17581b82..608cfcfbb3e 100644
--- a/include/asm-mips/asm.h
+++ b/include/asm-mips/asm.h
@@ -398,4 +398,12 @@ symbol = value
#define SSNOP sll zero, zero, 1
+#ifdef CONFIG_SGI_IP28
+/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
+#include <asm/cacheops.h>
+#define R10KCBARRIER(addr) cache Cache_Barrier, addr;
+#else
+#define R10KCBARRIER(addr)
+#endif
+
#endif /* __ASM_ASM_H */