diff options
| author | Olof Johansson <olof@lixom.net> | 2007-10-16 00:58:59 +1000 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2007-10-17 22:30:09 +1000 |
| commit | f66bce5e6aa1388289c04496c3fcae7bebf5f905 (patch) | |
| tree | 7e788739a51947f1caff47f9b5226cad739e3805 /include/asm-powerpc | |
| parent | 8129535b6bcf40be62af2ae6b9234494f39725dd (diff) | |
[POWERPC] Add 1TB workaround for PA6T
PA6T has a bug where the slbie instruction does not honor the large
segment bit. As a result, we have to always use slbia when switching
context.
We don't have to worry about changing the slbie's during fault processing,
since they should never be replacing one VSID with another using the
same ESID. I.e. there's no risk for inserting duplicate entries due to a
failed slbie of the old entry. So as long as we clear it out on context
switch we should be fine.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc')
| -rw-r--r-- | include/asm-powerpc/cputable.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h index ae093ef6836..9d74338e3de 100644 --- a/include/asm-powerpc/cputable.h +++ b/include/asm-powerpc/cputable.h @@ -165,6 +165,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, #define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000) #define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000) #define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000) +#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000) #ifndef __ASSEMBLY__ @@ -367,7 +368,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \ - CPU_FTR_PURR | CPU_FTR_REAL_LE) + CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B) #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \ CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2) |