diff options
| author | Gen FUKATSU <fukatsu.gen@jp.panasonic.com> | 2005-09-30 16:09:17 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2005-09-30 16:09:17 +0100 |
| commit | 217874feed0d3a6543a6b7127782f4a08bffd731 (patch) | |
| tree | 88c9468bea86336ac5cf27fb72252bd3527b7cb3 /include/asm-sparc/contregs.h | |
| parent | a06f5466c4576dcbf838a50a87903b0082774da7 (diff) | |
[ARM] 2940/1: Fix BTB entry flush in arch/arm/mm/cache-v6.S
Patch from Gen FUKATSU
Invalidate BTB entry instruction flushes two instruction
at a time. Therefore this instruction should be done four
times after invalidate instruction cache line.
Signed-off-by: Gen Fukatsu
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-sparc/contregs.h')
0 files changed, 0 insertions, 0 deletions