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authorJames Morris <jmorris@namei.org>2008-08-28 10:47:34 +1000
committerJames Morris <jmorris@namei.org>2008-08-28 10:47:34 +1000
commit86d688984deefa3ae5a802880c11f2b408b5d6cf (patch)
tree7ea5e8189b0a774626d3ed7c3c87df2495a4c4a0 /include/asm-x86/processor.h
parent93c06cbbf9fea5d5be1778febb7fa9ab1a74e5f5 (diff)
parent4c246edd2550304df5b766cc841584b2bb058843 (diff)
Merge branch 'master' into next
Diffstat (limited to 'include/asm-x86/processor.h')
-rw-r--r--include/asm-x86/processor.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h
index 5f58da401b4..4df3e2f6fb5 100644
--- a/include/asm-x86/processor.h
+++ b/include/asm-x86/processor.h
@@ -728,6 +728,29 @@ extern unsigned long boot_option_idle_override;
extern unsigned long idle_halt;
extern unsigned long idle_nomwait;
+/*
+ * on systems with caches, caches must be flashed as the absolute
+ * last instruction before going into a suspended halt. Otherwise,
+ * dirty data can linger in the cache and become stale on resume,
+ * leading to strange errors.
+ *
+ * perform a variety of operations to guarantee that the compiler
+ * will not reorder instructions. wbinvd itself is serializing
+ * so the processor will not reorder.
+ *
+ * Systems without cache can just go into halt.
+ */
+static inline void wbinvd_halt(void)
+{
+ mb();
+ /* check for clflush to determine if wbinvd is legal */
+ if (cpu_has_clflush)
+ asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
+ else
+ while (1)
+ halt();
+}
+
extern void enable_sep_cpu(void);
extern int sysenter_setup(void);