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authorPavel Machek <pavel@ucw.cz>2008-03-03 12:49:09 +0100
committerIngo Molnar <mingo@elte.hu>2008-04-17 17:40:52 +0200
commit0d7a1819e97ef89be5bcbb4b724acb9f6c873c97 (patch)
tree814e51eda64528744fc3aea5f769f430607c2a64 /include/asm-x86
parent3c2047cd32b1a8c782d7efab72707e7daa251625 (diff)
x86: wmb() confusion in system.h
Comment says wmb is a nop, but it is implemented as lock addl below... Should it be compiled to nop if we know we are running on "good" Intel cpu? At least remove confusing comment for now. Signed-off-by: Pavel Machek <pavel@suse.cz> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86')
-rw-r--r--include/asm-x86/system.h11
1 files changed, 1 insertions, 10 deletions
diff --git a/include/asm-x86/system.h b/include/asm-x86/system.h
index 9cff02ffe6c..428d9471497 100644
--- a/include/asm-x86/system.h
+++ b/include/asm-x86/system.h
@@ -296,16 +296,7 @@ void default_idle(void);
*/
#ifdef CONFIG_X86_32
/*
- * For now, "wmb()" doesn't actually do anything, as all
- * Intel CPU's follow what Intel calls a *Processor Order*,
- * in which all writes are seen in the program order even
- * outside the CPU.
- *
- * I expect future Intel CPU's to have a weaker ordering,
- * but I'd also expect them to finally get their act together
- * and add some real memory barriers if so.
- *
- * Some non intel clones support out of order store. wmb() ceases to be a
+ * Some non-Intel clones support out of order store. wmb() ceases to be a
* nop for these.
*/
#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)