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authorChris Zankel <chris@zankel.net>2007-08-22 10:14:51 -0700
committerChris Zankel <chris@zankel.net>2007-08-27 13:54:16 -0700
commit6656920b0b50beacb6cb64cf55273cbb686e436e (patch)
treedab9fdb81821b455a29779de6ca3306dbdf05dbd /include/asm-xtensa/io.h
parentff6fd469885aafa5ec387babcb6537f3c00d6df0 (diff)
[XTENSA] Add support for cache-aliasing
Add support for processors that have cache-aliasing issues, such as the Stretch S5000 processor. Cache-aliasing means that the size of the cache (for one way) is larger than the page size, thus, a page can end up in several places in cache depending on the virtual to physical translation. The method used here is to map a user page temporarily through the auto-refill way 0 and of of the DTLB. We probably will want to revisit this issue and use a better approach with kmap/kunmap. Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'include/asm-xtensa/io.h')
-rw-r--r--include/asm-xtensa/io.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-xtensa/io.h b/include/asm-xtensa/io.h
index 0faa614d969..47c3616ea9a 100644
--- a/include/asm-xtensa/io.h
+++ b/include/asm-xtensa/io.h
@@ -14,6 +14,7 @@
#ifdef __KERNEL__
#include <asm/byteorder.h>
#include <asm/page.h>
+#include <linux/kernel.h>
#include <linux/types.h>