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authorDavid S. Miller <davem@davemloft.net>2005-07-04 13:26:04 -0700
committerDavid S. Miller <davem@davemloft.net>2005-07-04 13:26:04 -0700
commitbb6743f4f0aed5c1f09fa77cd8d3973c31792f4f (patch)
treec4fa3bbc3a0f1bd6a146e8ec1918c2076f8d5730 /include
parent088dd1f81b3577c17c4c4381696bf2105ea0e43a (diff)
[SPARC64]: Do proper DMA IRQ syncing on Tomatillo
This was the main impetus behind adding the PCI IRQ shim. In order to properly order DMA writes wrt. interrupts, you have to write to a PCI controller register, then poll for that bit clearing. There is one bit for each interrupt source, and setting this register bit tells Tomatillo to drain all pending DMA from that device. Furthermore, Tomatillo's with revision less than 4 require us to do a block store due to some memory transaction ordering issues it has on JBUS. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include')
-rw-r--r--include/asm-sparc64/pbm.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-sparc64/pbm.h b/include/asm-sparc64/pbm.h
index 4c15610a2ba..38bbbccb406 100644
--- a/include/asm-sparc64/pbm.h
+++ b/include/asm-sparc64/pbm.h
@@ -145,6 +145,9 @@ struct pci_pbm_info {
/* Physical address base of PBM registers. */
unsigned long pbm_regs;
+ /* Physical address of DMA sync register, if any. */
+ unsigned long sync_reg;
+
/* Opaque 32-bit system bus Port ID. */
u32 portid;