aboutsummaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorYevgeny Petrilin <yevgenyp@mellanox.co.il>2008-08-06 20:14:06 -0700
committerRoland Dreier <rolandd@cisco.com>2008-08-06 20:14:06 -0700
commitf780a9f119caa48088b230836a7fa73d1096de7c (patch)
tree513fb3aa4342a481aa1f4101675ea2e9c41bc28a /include
parent6e86841d05f371b5b9b86ce76c02aaee83352298 (diff)
mlx4_core: Add ethernet fields to CQE struct
Add ethernet-related fields to struct mlx4_cqe so that the mlx4_en ethernet NIC driver can share the same definition. Signed-off-by: Yevgeny Petrilin <yevgenyp@mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/mlx4/cq.h36
1 files changed, 24 insertions, 12 deletions
diff --git a/include/linux/mlx4/cq.h b/include/linux/mlx4/cq.h
index 071cf96cf01..6f65b2c8bb8 100644
--- a/include/linux/mlx4/cq.h
+++ b/include/linux/mlx4/cq.h
@@ -39,17 +39,18 @@
#include <linux/mlx4/doorbell.h>
struct mlx4_cqe {
- __be32 my_qpn;
+ __be32 vlan_my_qpn;
__be32 immed_rss_invalid;
__be32 g_mlpath_rqpn;
- u8 sl;
- u8 reserved1;
+ __be16 sl_vid;
__be16 rlid;
- __be32 ipoib_status;
+ __be16 status;
+ u8 ipv6_ext_mask;
+ u8 badfcs_enc;
__be32 byte_cnt;
__be16 wqe_index;
__be16 checksum;
- u8 reserved2[3];
+ u8 reserved[3];
u8 owner_sr_opcode;
};
@@ -64,6 +65,11 @@ struct mlx4_err_cqe {
};
enum {
+ MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29,
+ MLX4_CQE_QPN_MASK = 0xffffff,
+};
+
+enum {
MLX4_CQE_OWNER_MASK = 0x80,
MLX4_CQE_IS_SEND_MASK = 0x40,
MLX4_CQE_OPCODE_MASK = 0x1f
@@ -86,13 +92,19 @@ enum {
};
enum {
- MLX4_CQE_IPOIB_STATUS_IPV4 = 1 << 22,
- MLX4_CQE_IPOIB_STATUS_IPV4F = 1 << 23,
- MLX4_CQE_IPOIB_STATUS_IPV6 = 1 << 24,
- MLX4_CQE_IPOIB_STATUS_IPV4OPT = 1 << 25,
- MLX4_CQE_IPOIB_STATUS_TCP = 1 << 26,
- MLX4_CQE_IPOIB_STATUS_UDP = 1 << 27,
- MLX4_CQE_IPOIB_STATUS_IPOK = 1 << 28,
+ MLX4_CQE_STATUS_IPV4 = 1 << 6,
+ MLX4_CQE_STATUS_IPV4F = 1 << 7,
+ MLX4_CQE_STATUS_IPV6 = 1 << 8,
+ MLX4_CQE_STATUS_IPV4OPT = 1 << 9,
+ MLX4_CQE_STATUS_TCP = 1 << 10,
+ MLX4_CQE_STATUS_UDP = 1 << 11,
+ MLX4_CQE_STATUS_IPOK = 1 << 12,
+};
+
+enum {
+ MLX4_CQE_LLC = 1,
+ MLX4_CQE_SNAP = 1 << 1,
+ MLX4_CQE_BAD_FCS = 1 << 4,
};
static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,