diff options
| author | Masato Noguchi <Masato.Noguchi@jp.sony.com> | 2007-12-20 16:39:59 +0900 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2007-12-21 19:46:20 +1100 |
| commit | 9476141c185aa131fa8b4b6ccc5c0ccf92300225 (patch) | |
| tree | f3a594fa7c3945d9cd527d6df3cff30d0b2e6ab7 /include | |
| parent | b192541b39ed29ff82f9f2d5427f451e89617f1c (diff) | |
[POWERPC] spufs: don't set reserved bits in spu interrupt status
This changes the spu context switch code to not write to reserved bits
of spu interrupt status register.
The architecture book says the reserved fields should be set to zero.
Signed-off-by: Masato Noguchi <Masato.Noguchi@jp.sony.com>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-powerpc/spu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h index 277460476ae..5ca30e2e263 100644 --- a/include/asm-powerpc/spu.h +++ b/include/asm-powerpc/spu.h @@ -535,11 +535,13 @@ struct spu_priv1 { #define CLASS1_STORAGE_FAULT_INTR 0x2L #define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L #define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L +#define CLASS1_INTR_MASK 0xfL #define CLASS2_MAILBOX_INTR 0x1L #define CLASS2_SPU_STOP_INTR 0x2L #define CLASS2_SPU_HALT_INTR 0x4L #define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L #define CLASS2_MAILBOX_THRESHOLD_INTR 0x10L +#define CLASS2_INTR_MASK 0x1fL u8 pad_0x158_0x180[0x28]; /* 0x158 */ u64 int_route_RW; /* 0x180 */ |