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authorLinus Torvalds <torvalds@g5.osdl.org>2005-08-29 10:34:59 -0700
committerLinus Torvalds <torvalds@g5.osdl.org>2005-08-29 10:34:59 -0700
commit975f957dc408925805dd8f5aa4217b7eeea2d005 (patch)
tree2198bb72323a016d93c7440c9240bac94a5c0016 /include
parent2321fbd2b87539edc1fbfc2e186528a1ef93835f (diff)
parent661299d9d0437a0ff72240f3d60016ac3a361a6e (diff)
Merge HEAD from master.kernel.org:/home/rmk/linux-2.6-serial.git
Diffstat (limited to 'include')
-rw-r--r--include/linux/8250_pci.h39
-rw-r--r--include/linux/serialP.h40
2 files changed, 37 insertions, 42 deletions
diff --git a/include/linux/8250_pci.h b/include/linux/8250_pci.h
index 5f3ab21b339..3209dd46ea7 100644
--- a/include/linux/8250_pci.h
+++ b/include/linux/8250_pci.h
@@ -1,2 +1,37 @@
-int pci_siig10x_fn(struct pci_dev *dev, int enable);
-int pci_siig20x_fn(struct pci_dev *dev, int enable);
+/*
+ * Definitions for PCI support.
+ */
+#define FL_BASE_MASK 0x0007
+#define FL_BASE0 0x0000
+#define FL_BASE1 0x0001
+#define FL_BASE2 0x0002
+#define FL_BASE3 0x0003
+#define FL_BASE4 0x0004
+#define FL_GET_BASE(x) (x & FL_BASE_MASK)
+
+/* Use successive BARs (PCI base address registers),
+ else use offset into some specified BAR */
+#define FL_BASE_BARS 0x0008
+
+/* do not assign an irq */
+#define FL_NOIRQ 0x0080
+
+/* Use the Base address register size to cap number of ports */
+#define FL_REGION_SZ_CAP 0x0100
+
+struct pciserial_board {
+ unsigned int flags;
+ unsigned int num_ports;
+ unsigned int base_baud;
+ unsigned int uart_offset;
+ unsigned int reg_shift;
+ unsigned int first_offset;
+};
+
+struct serial_private;
+
+struct serial_private *
+pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board);
+void pciserial_remove_ports(struct serial_private *priv);
+void pciserial_suspend_ports(struct serial_private *priv);
+void pciserial_resume_ports(struct serial_private *priv);
diff --git a/include/linux/serialP.h b/include/linux/serialP.h
index 2b2f35a64d7..2b9e6b9554d 100644
--- a/include/linux/serialP.h
+++ b/include/linux/serialP.h
@@ -140,44 +140,4 @@ struct rs_multiport_struct {
#define ALPHA_KLUDGE_MCR 0
#endif
-/*
- * Definitions for PCI support.
- */
-#define SPCI_FL_BASE_MASK 0x0007
-#define SPCI_FL_BASE0 0x0000
-#define SPCI_FL_BASE1 0x0001
-#define SPCI_FL_BASE2 0x0002
-#define SPCI_FL_BASE3 0x0003
-#define SPCI_FL_BASE4 0x0004
-#define SPCI_FL_GET_BASE(x) (x & SPCI_FL_BASE_MASK)
-
-#define SPCI_FL_IRQ_MASK (0x0007 << 4)
-#define SPCI_FL_IRQBASE0 (0x0000 << 4)
-#define SPCI_FL_IRQBASE1 (0x0001 << 4)
-#define SPCI_FL_IRQBASE2 (0x0002 << 4)
-#define SPCI_FL_IRQBASE3 (0x0003 << 4)
-#define SPCI_FL_IRQBASE4 (0x0004 << 4)
-#define SPCI_FL_GET_IRQBASE(x) ((x & SPCI_FL_IRQ_MASK) >> 4)
-
-/* Use successive BARs (PCI base address registers),
- else use offset into some specified BAR */
-#define SPCI_FL_BASE_TABLE 0x0100
-
-/* Use successive entries in the irq resource table */
-#define SPCI_FL_IRQ_TABLE 0x0200
-
-/* Use the irq resource table instead of dev->irq */
-#define SPCI_FL_IRQRESOURCE 0x0400
-
-/* Use the Base address register size to cap number of ports */
-#define SPCI_FL_REGION_SZ_CAP 0x0800
-
-/* Do not use irq sharing for this device */
-#define SPCI_FL_NO_SHIRQ 0x1000
-
-/* This is a PNP device */
-#define SPCI_FL_ISPNP 0x2000
-
-#define SPCI_FL_PNPDEFAULT (SPCI_FL_IRQRESOURCE|SPCI_FL_ISPNP)
-
#endif /* _LINUX_SERIAL_H */