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authorAssaf Hoffman <hoffman@marvell.com>2007-10-23 15:14:41 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-01-26 15:03:38 +0000
commite50d64097b6e63278789ee3a4394d127bd6e4254 (patch)
treea33325c4ea814bdcd1ef187559b9ec751ae553e2 /include
parent2fd2b1242810fb4d2ba36548fecc1f005c36770c (diff)
[ARM] Marvell Feroceon CPU core support
The Feroceon is a family of independent ARMv5TE compliant CPU core implementations, supporting a variable depth pipeline and out-of-order execution. The Feroceon is configurable with VFP support, and the later models in the series are superscalar with up to two instructions per clock cycle. This patch adds the initial low-level cache/TLB handling for this core. Signed-off-by: Assaf Hoffman <hoffman@marvell.com> Reviewed-by: Tzachi Perelstein <tzachi@marvell.com> Reviewed-by: Nicolas Pitre <nico@marvell.com> Reviewed-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/cacheflush.h8
-rw-r--r--include/asm-arm/proc-fns.h8
2 files changed, 16 insertions, 0 deletions
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 6c1c968b298..759a97b56ee 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -94,6 +94,14 @@
# endif
#endif
+#if defined(CONFIG_CPU_FEROCEON)
+# ifdef _CACHE
+# define MULTI_CACHE 1
+# else
+# define _CACHE feroceon
+# endif
+#endif
+
#if defined(CONFIG_CPU_V6)
//# ifdef _CACHE
# define MULTI_CACHE 1
diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h
index 5599d4e5e70..a4ce457199d 100644
--- a/include/asm-arm/proc-fns.h
+++ b/include/asm-arm/proc-fns.h
@@ -185,6 +185,14 @@
# define CPU_NAME cpu_xsc3
# endif
# endif
+# ifdef CONFIG_CPU_FEROCEON
+# ifdef CPU_NAME
+# undef MULTI_CPU
+# define MULTI_CPU
+# else
+# define CPU_NAME cpu_feroceon
+# endif
+# endif
# ifdef CONFIG_CPU_V6
# ifdef CPU_NAME
# undef MULTI_CPU