aboutsummaryrefslogtreecommitdiff
path: root/init
diff options
context:
space:
mode:
authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-09-25 14:45:02 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-09-25 14:45:02 +0100
commit90f1e084783be9bbff4861fa8e460b76de2787f4 (patch)
treec7b9b40020c9fd884a63ccb9747f9c473bf8eb14 /init
parent1562f98f918f2de7549edbaaabdb8bece52320f0 (diff)
[ARM] Remove cache type printks
The cache type register found in ARMv5 and later CPUs changes format and meaning depending on the CPU architecture version. Currently, this code: a) doesn't work for everything - Xscale's are identified as 'unknown 5'. b) is not able to tell whether the caches are VIVT or VIPT from the cache type. c) prints rubbish on some ARMv6 and ARMv7+ CPUs. The two solutions to this are: 1. Add yet more code to decode and print the various different register formats. 2. Remove the code altogther. The code only exists to decode and print the cache parameters. Increasing the complexity of it just for the sake of a few prinks isn't worth it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'init')
0 files changed, 0 insertions, 0 deletions