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| author | Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2008-03-24 23:15:50 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-04-28 17:14:26 +0100 |
| commit | 0167509574ef1cdb516906db5e8b6ad5ca64ab61 (patch) | |
| tree | 3047fc8adf04601f529e2d497a36d1a79d4681bc /mm/page_alloc.c | |
| parent | a92b05880d261e9017ef8e7d5b6b01e0e5aa991d (diff) | |
[MIPS] Alchemy: don't unmask timer IRQ early
Defer the unmasking of the count/compare interrupt (IRQ5) till the
clockevent driver initialization:
- only enable the cascaded IRQs 0 thru 4 in arch_init_irq(); kill the
ALLINTS macro -- this change is blessed by AMD as I saw it in their own
patch; :-)
- do not force IRQ5 enabled in plat_time_init() if PM is enabled and there's
no 32 KHz crystal.
Update the copyrights (taking into account my prior changes), also removing
Pete Popov's old email...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'mm/page_alloc.c')
0 files changed, 0 insertions, 0 deletions