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author | Paul Walmsley <paul@pwsan.com> | 2009-06-19 19:08:26 -0600 |
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committer | paul <paul@twilight.(none)> | 2009-06-19 19:09:31 -0600 |
commit | c9812d042a21eb492a36cfabf9f41107f5ecee3d (patch) | |
tree | f9443de1d4534b0b56bd1b0ff56bfc6d78eb698d /net/ax25 | |
parent | 2f135eaf182761bb9a5cbd5138a447b0ad2a1fef (diff) |
OMAP3 clock: add a short delay when lowering CORE clk rate
When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2
divider, add a short delay before returning to SDRAM to allow the SDRC
time to stabilize. Without this delay, the system is prone to random
panics upon re-entering SDRAM.
This time delay varies based on MPU frequency. At 500MHz MPU frequency at
room temperature, 64 loops seems to work okay; so add another 32 loops for
environmental and process variation.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'net/ax25')
0 files changed, 0 insertions, 0 deletions