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-rw-r--r--arch/ppc64/oprofile/common.c7
-rw-r--r--arch/ppc64/oprofile/op_model_power4.c9
2 files changed, 5 insertions, 11 deletions
diff --git a/arch/ppc64/oprofile/common.c b/arch/ppc64/oprofile/common.c
index 4acd1a42493..a376eb2a1f0 100644
--- a/arch/ppc64/oprofile/common.c
+++ b/arch/ppc64/oprofile/common.c
@@ -16,6 +16,7 @@
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/pmc.h>
+#include <asm/cputable.h>
#include "op_impl.h"
@@ -131,7 +132,6 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
case PV_630:
case PV_630p:
model = &op_model_rs64;
- model->num_counters = 8;
ops->cpu_type = "ppc64/power3";
break;
@@ -140,14 +140,12 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
case PV_ICESTAR:
case PV_SSTAR:
model = &op_model_rs64;
- model->num_counters = 8;
ops->cpu_type = "ppc64/rs64";
break;
case PV_POWER4:
case PV_POWER4p:
model = &op_model_power4;
- model->num_counters = 8;
ops->cpu_type = "ppc64/power4";
break;
@@ -155,14 +153,12 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
case PV_970FX:
case PV_970MP:
model = &op_model_power4;
- model->num_counters = 8;
ops->cpu_type = "ppc64/970";
break;
case PV_POWER5:
case PV_POWER5p:
model = &op_model_power4;
- model->num_counters = 6;
ops->cpu_type = "ppc64/power5";
break;
@@ -170,6 +166,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
return -ENODEV;
}
+ model->num_counters = cur_cpu_spec->num_pmcs;
ops->create_files = op_ppc64_create_files;
ops->setup = op_ppc64_setup;
ops->shutdown = op_ppc64_shutdown;
diff --git a/arch/ppc64/oprofile/op_model_power4.c b/arch/ppc64/oprofile/op_model_power4.c
index 3d103d66870..e469610efde 100644
--- a/arch/ppc64/oprofile/op_model_power4.c
+++ b/arch/ppc64/oprofile/op_model_power4.c
@@ -23,7 +23,6 @@
static unsigned long reset_value[OP_MAX_COUNTER];
-static int num_counters;
static int oprofile_running;
static int mmcra_has_sihv;
@@ -45,8 +44,6 @@ static void power4_reg_setup(struct op_counter_config *ctr,
{
int i;
- num_counters = num_ctrs;
-
/*
* SIHV / SIPR bits are only implemented on POWER4+ (GQ) and above.
* However we disable it on all POWER4 until we verify it works
@@ -68,7 +65,7 @@ static void power4_reg_setup(struct op_counter_config *ctr,
backtrace_spinlocks = sys->backtrace_spinlocks;
- for (i = 0; i < num_counters; ++i)
+ for (i = 0; i < cur_cpu_spec->num_pmcs; ++i)
reset_value[i] = 0x80000000UL - ctr[i].count;
/* setup user and kernel profiling */
@@ -121,7 +118,7 @@ static void power4_start(struct op_counter_config *ctr)
/* set the PMM bit (see comment below) */
mtmsrd(mfmsr() | MSR_PMM);
- for (i = 0; i < num_counters; ++i) {
+ for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
if (ctr[i].enabled) {
ctr_write(i, reset_value[i]);
} else {
@@ -272,7 +269,7 @@ static void power4_handle_interrupt(struct pt_regs *regs,
/* set the PMM bit (see comment below) */
mtmsrd(mfmsr() | MSR_PMM);
- for (i = 0; i < num_counters; ++i) {
+ for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
val = ctr_read(i);
if (val < 0) {
if (oprofile_running && ctr[i].enabled) {