diff options
43 files changed, 2 insertions, 4973 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 16a5d522b2f..70f388d168d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -103,13 +103,6 @@ config ARCH_EBSA110 Ethernet interface, two PCMCIA sockets, two serial ports and a parallel port. -config ARCH_CAMELOT - bool "Epxa10db" - help - This enables support for Altera's Excalibur XA10 development board. - If you would like to build your kernel to run on one of these boards - then you must say 'Y' here. Otherwise say 'N' - config ARCH_FOOTBRIDGE bool "FootBridge" select FOOTBRIDGE @@ -221,8 +214,6 @@ endchoice source "arch/arm/mach-clps711x/Kconfig" -source "arch/arm/mach-epxa10db/Kconfig" - source "arch/arm/mach-footbridge/Kconfig" source "arch/arm/mach-integrator/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index afaf3a1e903..1c056d63115 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -84,7 +84,6 @@ endif machine-$(CONFIG_ARCH_PXA) := pxa machine-$(CONFIG_ARCH_L7200) := l7200 machine-$(CONFIG_ARCH_INTEGRATOR) := integrator - machine-$(CONFIG_ARCH_CAMELOT) := epxa10db textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 machine-$(CONFIG_ARCH_CLPS711X) := clps711x machine-$(CONFIG_ARCH_IOP3XX) := iop3xx diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 6b505ce41a7..0009a80498c 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -21,10 +21,6 @@ ifeq ($(CONFIG_ARCH_SHARK),y) OBJS += head-shark.o ofw-shark.o endif -ifeq ($(CONFIG_ARCH_CAMELOT),y) -OBJS += head-epxa10db.o -endif - ifeq ($(CONFIG_ARCH_L7200),y) OBJS += head-l7200.o endif diff --git a/arch/arm/boot/compressed/head-epxa10db.S b/arch/arm/boot/compressed/head-epxa10db.S deleted file mode 100644 index 757681f12a3..00000000000 --- a/arch/arm/boot/compressed/head-epxa10db.S +++ /dev/null @@ -1,5 +0,0 @@ -#include <asm/mach-types.h> -#include <asm/arch/excalibur.h> - - .section ".start", "ax" - mov r7, #MACH_TYPE_CAMELOT diff --git a/arch/arm/configs/epxa10db_defconfig b/arch/arm/configs/epxa10db_defconfig deleted file mode 100644 index 9fb8b58c495..00000000000 --- a/arch/arm/configs/epxa10db_defconfig +++ /dev/null @@ -1,644 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.12-rc1-bk2 -# Sun Mar 27 22:46:51 2005 -# -CONFIG_ARM=y -CONFIG_MMU=y -CONFIG_UID16=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_IOMAP=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_BROKEN_ON_SMP=y - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -CONFIG_SYSCTL=y -# CONFIG_AUDIT is not set -# CONFIG_HOTPLUG is not set -CONFIG_KOBJECT_UEVENT=y -# CONFIG_IKCONFIG is not set -# CONFIG_EMBEDDED is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SHMEM=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -# CONFIG_KMOD is not set - -# -# System Type -# -# CONFIG_ARCH_CLPS7500 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CO285 is not set -# CONFIG_ARCH_EBSA110 is not set -CONFIG_ARCH_CAMELOT=y -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_IOP3XX is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_IMX is not set -# CONFIG_ARCH_H720X is not set - -# -# Epxa10db -# - -# -# PLD hotswap support -# -CONFIG_PLD=y -# CONFIG_PLD_HOTSWAP is not set - -# -# Processor Type -# -CONFIG_CPU_32=y -CONFIG_CPU_ARM922T=y -CONFIG_CPU_32v4=y -CONFIG_CPU_ABRT_EV4T=y -CONFIG_CPU_CACHE_V4WT=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y -CONFIG_CPU_TLB_V4WBI=y - -# -# Processor Features -# -# CONFIG_ARM_THUMB is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set - -# -# Bus support -# - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -# CONFIG_PREEMPT is not set -CONFIG_ALIGNMENT_TRAP=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="mem=32M console=ttyUA0,115200 initrd=0x00200000,8M root=/dev/ram0 rw" -# CONFIG_XIP_KERNEL is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_FPE_NWFPE=y -# CONFIG_FPE_NWFPE_XP is not set -# CONFIG_FPE_FASTFPE is not set - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_AOUT is not set -# CONFIG_BINFMT_MISC is not set -# CONFIG_ARTHUR is not set - -# -# Power management options -# -# CONFIG_PM is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set - -# -# Memory Technology Devices (MTD) -# -# CONFIG_MTD is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CDROM_PKTCDVD is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_ATA_OVER_ETH is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -# CONFIG_IP_TCPDIAG is not set -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# Ethernet (10 or 100Mbit) -# -# CONFIG_NET_ETHERNET is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -CONFIG_PPP=y -CONFIG_PPP_MULTILINK=y -# CONFIG_PPP_FILTER is not set -CONFIG_PPP_ASYNC=y -CONFIG_PPP_SYNC_TTY=y -CONFIG_PPP_DEFLATE=y -# CONFIG_PPP_BSDCOMP is not set -# CONFIG_PPPOE is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Input device support -# -CONFIG_INPUT=y - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_RAW is not set -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y - -# -# Character devices -# -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_UART00=y -CONFIG_SERIAL_UART00_CONSOLE=y -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC is not set -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set - -# -# XFS support -# -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -CONFIG_AUTOFS_FS=y -CONFIG_AUTOFS4_FS=y - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_SYSFS=y -# CONFIG_DEVFS_FS is not set -# CONFIG_DEVPTS_FS_XATTR is not set -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -# CONFIG_NFS_FS is not set -# CONFIG_NFSD is not set -CONFIG_SMB_FS=y -# CONFIG_SMB_NLS_DEFAULT is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_FRAME_POINTER=y -# CONFIG_DEBUG_USER is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -# CONFIG_CRYPTO is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -CONFIG_CRC_CCITT=y -CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y diff --git a/arch/arm/mach-epxa10db/Kconfig b/arch/arm/mach-epxa10db/Kconfig deleted file mode 100644 index 55d896dd495..00000000000 --- a/arch/arm/mach-epxa10db/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -if ARCH_CAMELOT - -menu "Epxa10db" - -comment "PLD hotswap support" - -config PLD - bool - default y - -config PLD_HOTSWAP - bool "Support for PLD device hotplugging (experimental)" - depends on EXPERIMENTAL - help - This enables support for the dynamic loading and configuration of - compatible drivers when the contents of the PLD are changed. This - is still experimental and requires configuration tools which are - not yet generally available. Say N here. You must enable the kernel - module loader for this feature to work. - -endmenu - -endif diff --git a/arch/arm/mach-epxa10db/Makefile b/arch/arm/mach-epxa10db/Makefile deleted file mode 100644 index 24fbd7d3a3c..00000000000 --- a/arch/arm/mach-epxa10db/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# Object file lists. - -obj-y := arch.o irq.o mm.o time.o -obj-m := -obj-n := -obj- := - diff --git a/arch/arm/mach-epxa10db/Makefile.boot b/arch/arm/mach-epxa10db/Makefile.boot deleted file mode 100644 index 28bec7d3fc8..00000000000 --- a/arch/arm/mach-epxa10db/Makefile.boot +++ /dev/null @@ -1,2 +0,0 @@ - zreladdr-y := 0x00008000 - diff --git a/arch/arm/mach-epxa10db/arch.c b/arch/arm/mach-epxa10db/arch.c deleted file mode 100644 index 44c56571d18..00000000000 --- a/arch/arm/mach-epxa10db/arch.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * linux/arch/arm/mach-epxa10db/arch.c - * - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include <linux/types.h> -#include <linux/init.h> -#include <linux/serial_8250.h> - -#include <asm/hardware.h> -#include <asm/setup.h> -#include <asm/mach-types.h> - -#include <asm/mach/arch.h> - -static struct plat_serial8250_port serial_platform_data[] = { - { - .iobase = 0x3f8, - .irq = IRQ_UARTINT0, -#error FIXME - .uartclk = 0, - .regshift = 0, - .iotype = UPIO_PORT, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - }, - { - .iobase = 0x2f8, - .irq = IRQ_UARTINT1, -#error FIXME - .uartclk = 0, - .regshift = 0, - .iotype = UPIO_PORT, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - }, - { }, -}; - -static struct platform_device serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = serial_platform_data, - }, -}; - -extern void epxa10db_map_io(void); -extern void epxa10db_init_irq(void); -extern struct sys_timer epxa10db_timer; - -MACHINE_START(CAMELOT, "Altera Epxa10db") - /* Maintainer: Altera Corporation */ - .phys_ram = 0x00000000, - .phys_io = 0x7fffc000, - .io_pg_offst = ((0xffffc000) >> 18) & 0xfffc, - .map_io = epxa10db_map_io, - .init_irq = epxa10db_init_irq, - .timer = &epxa10db_timer, -MACHINE_END - diff --git a/arch/arm/mach-epxa10db/irq.c b/arch/arm/mach-epxa10db/irq.c deleted file mode 100644 index 9bf927e1330..00000000000 --- a/arch/arm/mach-epxa10db/irq.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * linux/arch/arm/mach-epxa10db/irq.c - * - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include <linux/init.h> -#include <linux/ioport.h> -#include <linux/stddef.h> -#include <linux/timer.h> -#include <linux/list.h> -#include <asm/io.h> -#include <asm/hardware.h> -#include <asm/irq.h> -#include <asm/mach/irq.h> -#include <asm/arch/platform.h> -#include <asm/arch/int_ctrl00.h> - - -static void epxa_mask_irq(unsigned int irq) -{ - writel(1 << irq, INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE))); -} - -static void epxa_unmask_irq(unsigned int irq) -{ - writel(1 << irq, INT_MS(IO_ADDRESS(EXC_INT_CTRL00_BASE))); -} - - -static struct irqchip epxa_irq_chip = { - .ack = epxa_mask_irq, - .mask = epxa_mask_irq, - .unmask = epxa_unmask_irq, -}; - -static struct resource irq_resource = { - .name = "irq_handler", - .start = IO_ADDRESS(EXC_INT_CTRL00_BASE), - .end = IO_ADDRESS(INT_PRIORITY_FC(EXC_INT_CTRL00_BASE))+4, -}; - -void __init epxa10db_init_irq(void) -{ - unsigned int i; - - request_resource(&iomem_resource, &irq_resource); - - /* - * This bit sets up the interrupt controller using - * the 6 PLD interrupts mode (the default) each - * irqs is assigned a priority which is the same - * as its interrupt number. This scheme is used because - * its easy, but you may want to change it depending - * on the contents of your PLD - */ - - writel(3,INT_MODE(IO_ADDRESS(EXC_INT_CTRL00_BASE))); - for (i = 0; i < NR_IRQS; i++){ - writel(i+1, INT_PRIORITY_P0(IO_ADDRESS(EXC_INT_CTRL00_BASE)) + (4*i)); - set_irq_chip(i,&epxa_irq_chip); - set_irq_handler(i,do_level_IRQ); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - } - - /* Disable all interrupts */ - writel(-1,INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE))); - -} diff --git a/arch/arm/mach-epxa10db/mm.c b/arch/arm/mach-epxa10db/mm.c deleted file mode 100644 index cfd0d2182d4..00000000000 --- a/arch/arm/mach-epxa10db/mm.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * linux/arch/arm/mach-epxa10db/mm.c - * - * MM routines for Altera'a Epxa10db board - * - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/hardware.h> -#include <asm/io.h> -#include <asm/sizes.h> -#include <asm/page.h> - -#include <asm/mach/map.h> - -/* Page table mapping for I/O region */ - -static struct map_desc epxa10db_io_desc[] __initdata = { - { - .virtual = IO_ADDRESS(EXC_REGISTERS_BASE), - .pfn = __phys_to_pfn(EXC_REGISTERS_BASE), - .length = SZ_16K, - .type = MT_DEVICE - }, { - .virtual = IO_ADDRESS(EXC_PLD_BLOCK0_BASE), - .pfn = __phys_to_pfn(EXC_PLD_BLOCK0_BASE), - .length = SZ_16K, - .type = MT_DEVICE - }, { - .virtual = IO_ADDRESS(EXC_PLD_BLOCK1_BASE), - .pfn =__phys_to_pfn(EXC_PLD_BLOCK1_BASE), - .length = SZ_16K, - .type = MT_DEVICE - }, { - .virtual = IO_ADDRESS(EXC_PLD_BLOCK2_BASE), - .physical = __phys_to_pfn(EXC_PLD_BLOCK2_BASE), - .length = SZ_16K, - .type = MT_DEVICE - }, { - .virtual = IO_ADDRESS(EXC_PLD_BLOCK3_BASE), - .pfn = __phys_to_pfn(EXC_PLD_BLOCK3_BASE), - .length = SZ_16K, - .type = MT_DEVICE - }, { - .virtual = FLASH_VADDR(EXC_EBI_BLOCK0_BASE), - .pfn = __phys_to_pfn(EXC_EBI_BLOCK0_BASE), - .length = SZ_16M, - .type = MT_DEVICE - } -}; - -void __init epxa10db_map_io(void) -{ - iotable_init(epxa10db_io_desc, ARRAY_SIZE(epxa10db_io_desc)); -} diff --git a/arch/arm/mach-epxa10db/time.c b/arch/arm/mach-epxa10db/time.c deleted file mode 100644 index 4b1084dde8d..00000000000 --- a/arch/arm/mach-epxa10db/time.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * linux/arch/arm/mach-epxa10db/time.c - * - * Copyright (C) 2000 Deep Blue Solutions - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/sched.h> - -#include <asm/hardware.h> -#include <asm/system.h> -#include <asm/leds.h> - -#include <asm/mach/time.h> - -#define TIMER00_TYPE (volatile unsigned int*) -#include <asm/arch/timer00.h> - -static int epxa10db_set_rtc(void) -{ - return 1; -} - -static int epxa10db_rtc_init(void) -{ - set_rtc = epxa10db_set_rtc; - - return 0; -} - -__initcall(epxa10db_rtc_init); - - -/* - * IRQ handler for the timer - */ -static irqreturn_t -epxa10db_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) -{ - write_seqlock(&xtime_lock); - - // ...clear the interrupt - *TIMER0_CR(IO_ADDRESS(EXC_TIMER00_BASE))|=TIMER0_CR_CI_MSK; - - timer_tick(regs); - write_sequnlock(&xtime_lock); - - return IRQ_HANDLED; -} - -static struct irqaction epxa10db_timer_irq = { - .name = "Excalibur Timer Tick", - .flags = SA_INTERRUPT | SA_TIMER, - .handler = epxa10db_timer_interrupt, -}; - -/* - * Set up timer interrupt, and return the current time in seconds. - */ -static void __init epxa10db_timer_init(void) -{ - /* Start the timer */ - *TIMER0_LIMIT(IO_ADDRESS(EXC_TIMER00_BASE))=(unsigned int)(EXC_AHB2_CLK_FREQUENCY/200); - *TIMER0_PRESCALE(IO_ADDRESS(EXC_TIMER00_BASE))=1; - *TIMER0_CR(IO_ADDRESS(EXC_TIMER00_BASE))=TIMER0_CR_IE_MSK | TIMER0_CR_S_MSK; - - setup_irq(IRQ_TIMER0, &epxa10db_timer_irq); -} - -struct sys_timer epxa10db_timer = { - .init = epxa10db_timer_init, -}; diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index e84fdde6edf..04cf0557e54 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -83,8 +83,8 @@ config CPU_ARM920T # ARM922T config CPU_ARM922T bool "Support ARM922T processor" if ARCH_INTEGRATOR - depends on ARCH_CAMELOT || ARCH_LH7A40X || ARCH_INTEGRATOR - default y if ARCH_CAMELOT || ARCH_LH7A40X + depends on ARCH_LH7A40X || ARCH_INTEGRATOR + default y if ARCH_LH7A40X select CPU_32v4 select CPU_ABRT_EV4T select CPU_CACHE_V4WT diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig index b9b77cf39a1..7abd7fee0dd 100644 --- a/drivers/mtd/maps/Kconfig +++ b/drivers/mtd/maps/Kconfig @@ -473,14 +473,6 @@ config MTD_IXP2000 IXDP425 and Coyote. If you have an IXP2000 based board and would like to use the flash chips on it, say 'Y'. -config MTD_EPXA10DB - tristate "CFI Flash device mapped on Epxa10db" - depends on MTD_CFI && MTD_PARTITIONS && ARCH_CAMELOT - help - This enables support for the flash devices on the Altera - Excalibur XA10 Development Board. If you are building a kernel - for on of these boards then you should say 'Y' otherwise say 'N'. - config MTD_FORTUNET tristate "CFI Flash device mapped on the FortuNet board" depends on MTD_CFI && MTD_PARTITIONS && SA1100_FORTUNET diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile index 2f7e254912f..ab71f172eb7 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile @@ -15,7 +15,6 @@ obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o obj-$(CONFIG_MTD_CSTM_MIPS_IXX) += cstm_mips_ixx.o obj-$(CONFIG_MTD_DC21285) += dc21285.o obj-$(CONFIG_MTD_DILNETPC) += dilnetpc.o -obj-$(CONFIG_MTD_EPXA10DB) += epxa10db-flash.o obj-$(CONFIG_MTD_IQ80310) += iq80310.o obj-$(CONFIG_MTD_L440GX) += l440gx.o obj-$(CONFIG_MTD_AMD76XROM) += amd76xrom.o diff --git a/drivers/mtd/maps/epxa10db-flash.c b/drivers/mtd/maps/epxa10db-flash.c deleted file mode 100644 index 265b079fe93..00000000000 --- a/drivers/mtd/maps/epxa10db-flash.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Flash memory access on EPXA based devices - * - * (C) 2000 Nicolas Pitre <nico@cam.org> - * Copyright (C) 2001 Altera Corporation - * Copyright (C) 2001 Red Hat, Inc. - * - * $Id: epxa10db-flash.c,v 1.15 2005/11/07 11:14:27 gleixner Exp $ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <linux/config.h> -#include <linux/module.h> -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/slab.h> - -#include <linux/mtd/mtd.h> -#include <linux/mtd/map.h> -#include <linux/mtd/partitions.h> - -#include <asm/io.h> -#include <asm/hardware.h> - -#ifdef CONFIG_EPXA10DB -#define BOARD_NAME "EPXA10DB" -#else -#define BOARD_NAME "EPXA1DB" -#endif - -static int nr_parts = 0; -static struct mtd_partition *parts; - -static struct mtd_info *mymtd; - -static int epxa_default_partitions(struct mtd_info *master, struct mtd_partition **pparts); - - -static struct map_info epxa_map = { - .name = "EPXA flash", - .size = FLASH_SIZE, - .bankwidth = 2, - .phys = FLASH_START, -}; - -static const char *probes[] = { "RedBoot", "afs", NULL }; - -static int __init epxa_mtd_init(void) -{ - int i; - - printk(KERN_NOTICE "%s flash device: 0x%x at 0x%x\n", BOARD_NAME, FLASH_SIZE, FLASH_START); - - epxa_map.virt = ioremap(FLASH_START, FLASH_SIZE); - if (!epxa_map.virt) { - printk("Failed to ioremap %s flash\n",BOARD_NAME); - return -EIO; - } - simple_map_init(&epxa_map); - - mymtd = do_map_probe("cfi_probe", &epxa_map); - if (!mymtd) { - iounmap((void *)epxa_map.virt); - return -ENXIO; - } - - mymtd->owner = THIS_MODULE; - - /* Unlock the flash device. */ - if(mymtd->unlock){ - for (i=0; i<mymtd->numeraseregions;i++){ - int j; - for(j=0;j<mymtd->eraseregions[i].numblocks;j++){ - mymtd->unlock(mymtd,mymtd->eraseregions[i].offset + j * mymtd->eraseregions[i].erasesize,mymtd->eraseregions[i].erasesize); - } - } - } - -#ifdef CONFIG_MTD_PARTITIONS - nr_parts = parse_mtd_partitions(mymtd, probes, &parts, 0); - - if (nr_parts > 0) { - add_mtd_partitions(mymtd, parts, nr_parts); - return 0; - } -#endif - /* No recognised partitioning schemes found - use defaults */ - nr_parts = epxa_default_partitions(mymtd, &parts); - if (nr_parts > 0) { - add_mtd_partitions(mymtd, parts, nr_parts); - return 0; - } - - /* If all else fails... */ - add_mtd_device(mymtd); - return 0; -} - -static void __exit epxa_mtd_cleanup(void) -{ - if (mymtd) { - if (nr_parts) - del_mtd_partitions(mymtd); - else - del_mtd_device(mymtd); - map_destroy(mymtd); - } - if (epxa_map.virt) { - iounmap((void *)epxa_map.virt); - epxa_map.virt = 0; - } -} - - -/* - * This will do for now, once we decide which bootldr we're finally - * going to use then we'll remove this function and do it properly - * - * Partions are currently (as offsets from base of flash): - * 0x00000000 - 0x003FFFFF - bootloader (!) - * 0x00400000 - 0x00FFFFFF - Flashdisk - */ - -static int __init epxa_default_partitions(struct mtd_info *master, struct mtd_partition **pparts) -{ - struct mtd_partition *parts; - int ret, i; - int npartitions = 0; - char *names; - const char *name = "jffs"; - - printk("Using default partitions for %s\n",BOARD_NAME); - npartitions=1; - parts = kmalloc(npartitions*sizeof(*parts)+strlen(name), GFP_KERNEL); - memzero(parts,npartitions*sizeof(*parts)+strlen(name)); - if (!parts) { - ret = -ENOMEM; - goto out; - } - i=0; - names = (char *)&parts[npartitions]; - parts[i].name = names; - names += strlen(name) + 1; - strcpy(parts[i].name, name); - -#ifdef CONFIG_EPXA10DB - parts[i].size = FLASH_SIZE-0x00400000; - parts[i].offset = 0x00400000; -#else - parts[i].size = FLASH_SIZE-0x00180000; - parts[i].offset = 0x00180000; -#endif - - out: - *pparts = parts; - return npartitions; -} - - -module_init(epxa_mtd_init); -module_exit(epxa_mtd_cleanup); - -MODULE_AUTHOR("Clive Davies"); -MODULE_DESCRIPTION("Altera epxa mtd flash map"); -MODULE_LICENSE("GPL"); diff --git a/drivers/net/arm/Kconfig b/drivers/net/arm/Kconfig index 470364deded..625184b65e3 100644 --- a/drivers/net/arm/Kconfig +++ b/drivers/net/arm/Kconfig @@ -31,16 +31,3 @@ config ARM_ETHERH help If you have an Acorn system with one of these network cards, you should say Y to this option if you wish to use it with Linux. - -config ARM_ETHER00 - tristate "Altera Ether00 support" - depends on NET_ETHERNET && ARM && ARCH_CAMELOT - help - This is the driver for Altera's ether00 ethernet mac IP core. Say - Y here if you want to build support for this into the kernel. It - is also available as a module (say M here) that can be inserted/ - removed from the kernel at the same time as the PLD is configured. - If this driver is running on an epxa10 development board then it - will generate a suitable hw address based on the board serial - number (MTD support is required for this). Otherwise you will - need to set a suitable hw address using ifconfig. diff --git a/drivers/net/arm/Makefile b/drivers/net/arm/Makefile index b0d706834d8..bc263edf06a 100644 --- a/drivers/net/arm/Makefile +++ b/drivers/net/arm/Makefile @@ -4,7 +4,6 @@ # obj-$(CONFIG_ARM_AM79C961A) += am79c961a.o -obj-$(CONFIG_ARM_ETHER00) += ether00.o obj-$(CONFIG_ARM_ETHERH) += etherh.o obj-$(CONFIG_ARM_ETHER3) += ether3.o obj-$(CONFIG_ARM_ETHER1) += ether1.o diff --git a/drivers/net/arm/ether00.c b/drivers/net/arm/ether00.c deleted file mode 100644 index 4f1f4e31bda..00000000000 --- a/drivers/net/arm/ether00.c +++ /dev/null @@ -1,1017 +0,0 @@ -/* - * drivers/net/ether00.c - * - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -/* includes */ -#include <linux/config.h> -#include <linux/pci.h> -#include <linux/sched.h> -#include <linux/netdevice.h> -#include <linux/skbuff.h> -#include <linux/etherdevice.h> -#include <linux/module.h> -#include <linux/tqueue.h> -#include <linux/mtd/mtd.h> -#include <linux/pld/pld_hotswap.h> -#include <asm/arch/excalibur.h> -#include <asm/arch/hardware.h> -#include <asm/irq.h> -#include <asm/io.h> -#include <asm/sizes.h> - -#include <asm/arch/ether00.h> -#include <asm/arch/tdkphy.h> - - -MODULE_AUTHOR("Clive Davies"); -MODULE_DESCRIPTION("Altera Ether00 IP core driver"); -MODULE_LICENSE("GPL"); - -#define PKT_BUF_SZ 1540 /* Size of each rx buffer */ -#define ETH_NR 4 /* Number of MACs this driver supports */ - -#define DEBUG(x) - -#define __dma_va(x) (unsigned int)((unsigned int)priv->dma_data+(((unsigned int)(x))&(EXC_SPSRAM_BLOCK0_SIZE-1))) -#define __dma_pa(x) (unsigned int)(EXC_SPSRAM_BLOCK0_BASE+(((unsigned int)(x))-(unsigned int)priv->dma_data)) - -#define ETHER00_BASE 0 -#define ETHER00_TYPE -#define ETHER00_NAME "ether00" -#define MAC_REG_SIZE 0x400 /* size of MAC register area */ - - - -/* typedefs */ - -/* The definition of the driver control structure */ - -#define RX_NUM_BUFF 10 -#define RX_NUM_FDESC 10 -#define TX_NUM_FDESC 10 - -struct tx_fda_ent{ - FDA_DESC fd; - BUF_DESC bd; - BUF_DESC pad; -}; -struct rx_fda_ent{ - FDA_DESC fd; - BUF_DESC bd; - BUF_DESC pad; -}; -struct rx_blist_ent{ - FDA_DESC fd; - BUF_DESC bd; - BUF_DESC pad; -}; -struct net_priv -{ - struct net_device_stats stats; - struct sk_buff* skb; - void* dma_data; - struct rx_blist_ent* rx_blist_vp; - struct rx_fda_ent* rx_fda_ptr; - struct tx_fda_ent* tx_fdalist_vp; - struct tq_struct tq_memupdate; - unsigned char memupdate_scheduled; - unsigned char rx_disabled; - unsigned char queue_stopped; - spinlock_t rx_lock; -}; - -static const char vendor_id[2]={0x07,0xed}; - -#ifdef ETHER00_DEBUG - -/* Dump (most) registers for debugging puposes */ - -static void dump_regs(struct net_device *dev){ - struct net_priv* priv=dev->priv; - unsigned int* i; - - printk("\n RX free descriptor area:\n"); - - for(i=(unsigned int*)priv->rx_fda_ptr; - i<((unsigned int*)(priv->rx_fda_ptr+RX_NUM_FDESC));){ - printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3)); - i+=4; - } - - printk("\n RX buffer list:\n"); - - for(i=(unsigned int*)priv->rx_blist_vp; - i<((unsigned int*)(priv->rx_blist_vp+RX_NUM_BUFF));){ - printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3)); - i+=4; - } - - printk("\n TX frame descriptor list:\n"); - - for(i=(unsigned int*)priv->tx_fdalist_vp; - i<((unsigned int*)(priv->tx_fdalist_vp+TX_NUM_FDESC));){ - printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3)); - i+=4; - } - - printk("\ndma ctl=%#x\n",readw(ETHER_DMA_CTL(dev->base_addr))); - printk("txfrmptr=%#x\n",readw(ETHER_TXFRMPTR(dev->base_addr))); - printk("txthrsh=%#x\n",readw(ETHER_TXTHRSH(dev->base_addr))); - printk("txpollctr=%#x\n",readw(ETHER_TXPOLLCTR(dev->base_addr))); - printk("blfrmptr=%#x\n",readw(ETHER_BLFRMPTR(dev->base_addr))); - printk("rxfragsize=%#x\n",readw(ETHER_RXFRAGSIZE(dev->base_addr))); - printk("tx_int_en=%#x\n",readw(ETHER_INT_EN(dev->base_addr))); - printk("fda_bas=%#x\n",readw(ETHER_FDA_BAS(dev->base_addr))); - printk("fda_lim=%#x\n",readw(ETHER_FDA_LIM(dev->base_addr))); - printk("int_src=%#x\n",readw(ETHER_INT_SRC(dev->base_addr))); - printk("pausecnt=%#x\n",readw(ETHER_PAUSECNT(dev->base_addr))); - printk("rempaucnt=%#x\n",readw(ETHER_REMPAUCNT(dev->base_addr))); - printk("txconfrmstat=%#x\n",readw(ETHER_TXCONFRMSTAT(dev->base_addr))); - printk("mac_ctl=%#x\n",readw(ETHER_MAC_CTL(dev->base_addr))); - printk("arc_ctl=%#x\n",readw(ETHER_ARC_CTL(dev->base_addr))); - printk("tx_ctl=%#x\n",readw(ETHER_TX_CTL(dev->base_addr))); -} -#endif /* ETHER00_DEBUG */ - - -static int ether00_write_phy(struct net_device *dev, short address, short value) -{ - volatile int count = 1024; - writew(value,ETHER_MD_DATA(dev->base_addr)); - writew( ETHER_MD_CA_BUSY_MSK | - ETHER_MD_CA_WR_MSK | - (address & ETHER_MD_CA_ADDR_MSK), - ETHER_MD_CA(dev->base_addr)); - - /* Wait for the command to complete */ - while((readw(ETHER_MD_CA(dev->base_addr)) & ETHER_MD_CA_BUSY_MSK)&&count){ - count--; - } - if (!count){ - printk("Write to phy failed, addr=%#x, data=%#x\n",address, value); - return -EIO; - } - return 0; -} - -static int ether00_read_phy(struct net_device *dev, short address) -{ - volatile int count = 1024; - writew( ETHER_MD_CA_BUSY_MSK | - (address & ETHER_MD_CA_ADDR_MSK), - ETHER_MD_CA(dev->base_addr)); - - /* Wait for the command to complete */ - while((readw(ETHER_MD_CA(dev->base_addr)) & ETHER_MD_CA_BUSY_MSK)&&count){ - count--; - } - if (!count){ - printk(KERN_WARNING "Read from phy timed out\n"); - return -EIO; - } - return readw(ETHER_MD_DATA(dev->base_addr)); -} - -static void ether00_phy_int(int irq_num, void* dev_id, struct pt_regs* regs) -{ - struct net_device* dev=dev_id; - int irq_status; - - irq_status=ether00_read_phy(dev, PHY_IRQ_CONTROL); - - if(irq_status & PHY_IRQ_CONTROL_ANEG_COMP_INT_MSK){ - /* - * Autonegotiation complete on epxa10db. The mac doesn't - * twig if we're in full duplex so we need to check the - * phy status register and configure the mac accordingly - */ - if(ether00_read_phy(dev, PHY_STATUS)&(PHY_STATUS_10T_F_MSK|PHY_STATUS_100_X_F_MSK)){ - int tmp; - tmp=readl(ETHER_MAC_CTL(dev->base_addr)); - writel(tmp|ETHER_MAC_CTL_FULLDUP_MSK,ETHER_MAC_CTL(dev->base_addr)); - } - } - - if(irq_status&PHY_IRQ_CONTROL_LS_CHG_INT_MSK){ - - if(ether00_read_phy(dev, PHY_STATUS)& PHY_STATUS_LINK_MSK){ - /* Link is up */ - netif_carrier_on(dev); - //printk("Carrier on\n"); - }else{ - netif_carrier_off(dev); - //printk("Carrier off\n"); - - } - } - -} - -static void setup_blist_entry(struct sk_buff* skb,struct rx_blist_ent* blist_ent_ptr){ - /* Make the buffer consistent with the cache as the mac is going to write - * directly into it*/ - blist_ent_ptr->fd.FDSystem=(unsigned int)skb; - blist_ent_ptr->bd.BuffData=(char*)__pa(skb->data); - consistent_sync(skb->data,PKT_BUF_SZ,PCI_DMA_FROMDEVICE); - /* align IP on 16 Byte (DMA_CTL set to skip 2 bytes) */ - skb_reserve(skb,2); - blist_ent_ptr->bd.BuffLength=PKT_BUF_SZ-2; - blist_ent_ptr->fd.FDLength=1; - blist_ent_ptr->fd.FDCtl=FDCTL_COWNSFD_MSK; - blist_ent_ptr->bd.BDCtl=BDCTL_COWNSBD_MSK; -} - - -static int ether00_mem_init(struct net_device* dev) -{ - struct net_priv* priv=dev->priv; - struct tx_fda_ent *tx_fd_ptr,*tx_end_ptr; - struct rx_blist_ent* blist_ent_ptr; - int i; - - /* - * Grab a block of on chip SRAM to contain the control stuctures for - * the ethernet MAC. This uncached becuase it needs to be accesses by both - * bus masters (cpu + mac). However, it shouldn't matter too much in terms - * of speed as its on chip memory - */ - priv->dma_data=ioremap_nocache(EXC_SPSRAM_BLOCK0_BASE,EXC_SPSRAM_BLOCK0_SIZE ); - if (!priv->dma_data) - return -ENOMEM; - - priv->rx_fda_ptr=(struct rx_fda_ent*)priv->dma_data; - /* - * Now share it out amongst the Frame descriptors and the buffer list - */ - priv->rx_blist_vp=(struct rx_blist_ent*)((unsigned int)priv->dma_data+RX_NUM_FDESC*sizeof(struct rx_fda_ent)); - - /* - *Initalise the FDA list - */ - /* set ownership to the controller */ - memset(priv->rx_fda_ptr,0x80,RX_NUM_FDESC*sizeof(struct rx_fda_ent)); - - /* - *Initialise the buffer list - */ - blist_ent_ptr=priv->rx_blist_vp; - i=0; - while(blist_ent_ptr<(priv->rx_blist_vp+RX_NUM_BUFF)){ - struct sk_buff *skb; - blist_ent_ptr->fd.FDLength=1; - skb=dev_alloc_skb(PKT_BUF_SZ); - if(skb){ - setup_blist_entry(skb,blist_ent_ptr); - blist_ent_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(blist_ent_ptr+1); - blist_ent_ptr->bd.BDStat=i++; - blist_ent_ptr++; - } - else - { - printk("Failed to initalise buffer list\n"); - } - - } - blist_ent_ptr--; - blist_ent_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(priv->rx_blist_vp); - - priv->tx_fdalist_vp=(struct tx_fda_ent*)(priv->rx_blist_vp+RX_NUM_BUFF); - - /* Initialise the buffers to be a circular list. The mac will then go poll - * the list until it finds a frame ready to transmit */ - tx_end_ptr=priv->tx_fdalist_vp+TX_NUM_FDESC; - for(tx_fd_ptr=priv->tx_fdalist_vp;tx_fd_ptr<tx_end_ptr;tx_fd_ptr++){ - tx_fd_ptr->fd.FDNext=(FDA_DESC*)__dma_pa((tx_fd_ptr+1)); - tx_fd_ptr->fd.FDCtl=1; - tx_fd_ptr->fd.FDStat=0; - tx_fd_ptr->fd.FDLength=1; - - } - /* Change the last FDNext pointer to make a circular list */ - tx_fd_ptr--; - tx_fd_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(priv->tx_fdalist_vp); - - /* Point the device at the chain of Rx and Tx Buffers */ - writel((unsigned int)__dma_pa(priv->rx_fda_ptr),ETHER_FDA_BAS(dev->base_addr)); - writel((RX_NUM_FDESC-1)*sizeof(struct rx_fda_ent),ETHER_FDA_LIM(dev->base_addr)); - writel((unsigned int)__dma_pa(priv->rx_blist_vp),ETHER_BLFRMPTR(dev->base_addr)); - - writel((unsigned int)__dma_pa(priv->tx_fdalist_vp),ETHER_TXFRMPTR(dev->base_addr)); - - return 0; -} - - -void ether00_mem_update(void* dev_id) -{ - struct net_device* dev=dev_id; - struct net_priv* priv=dev->priv; - struct sk_buff* skb; - struct tx_fda_ent *fda_ptr=priv->tx_fdalist_vp; - struct rx_blist_ent* blist_ent_ptr; - unsigned long flags; - - priv->tq_memupdate.sync=0; - //priv->tq_memupdate.list= - priv->memupdate_scheduled=0; - - /* Transmit interrupt */ - while(fda_ptr<(priv->tx_fdalist_vp+TX_NUM_FDESC)){ - if(!(FDCTL_COWNSFD_MSK&fda_ptr->fd.FDCtl) && (ETHER_TX_STAT_COMP_MSK&fda_ptr->fd.FDStat)){ - priv->stats.tx_packets++; - priv->stats.tx_bytes+=fda_ptr->bd.BuffLength; - skb=(struct sk_buff*)fda_ptr->fd.FDSystem; - //printk("%d:txcln:fda=%#x skb=%#x\n",jiffies,fda_ptr,skb); - dev_kfree_skb(skb); - fda_ptr->fd.FDSystem=0; - fda_ptr->fd.FDStat=0; - fda_ptr->fd.FDCtl=0; - } - fda_ptr++; - } - /* Fill in any missing buffers from the received queue */ - spin_lock_irqsave(&priv->rx_lock,flags); - blist_ent_ptr=priv->rx_blist_vp; - while(blist_ent_ptr<(priv->rx_blist_vp+RX_NUM_BUFF)){ - /* fd.FDSystem of 0 indicates we failed to allocate the buffer in the ISR */ - if(!blist_ent_ptr->fd.FDSystem){ - struct sk_buff *skb; - skb=dev_alloc_skb(PKT_BUF_SZ); - blist_ent_ptr->fd.FDSystem=(unsigned int)skb; - if(skb){ - setup_blist_entry(skb,blist_ent_ptr); - } - else - { - break; - } - } - blist_ent_ptr++; - } - spin_unlock_irqrestore(&priv->rx_lock,flags); - if(priv->queue_stopped){ - //printk("%d:cln:start q\n",jiffies); - netif_start_queue(dev); - } - if(priv->rx_disabled){ - //printk("%d:enable_irq\n",jiffies); - priv->rx_disabled=0; - writel(ETHER_RX_CTL_RXEN_MSK,ETHER_RX_CTL(dev->base_addr)); - - } -} - - -static void ether00_int( int irq_num, void* dev_id, struct pt_regs* regs) -{ - struct net_device* dev=dev_id; - struct net_priv* priv=dev->priv; - - unsigned int interruptValue; - - interruptValue=readl(ETHER_INT_SRC(dev->base_addr)); - - //printk("INT_SRC=%x\n",interruptValue); - - if(!(readl(ETHER_INT_SRC(dev->base_addr)) & ETHER_INT_SRC_IRQ_MSK)) - { - return; /* Interrupt wasn't caused by us!! */ - } - - if(readl(ETHER_INT_SRC(dev->base_addr))& - (ETHER_INT_SRC_INTMACRX_MSK | - ETHER_INT_SRC_FDAEX_MSK | - ETHER_INT_SRC_BLEX_MSK)) { - struct rx_blist_ent* blist_ent_ptr; - struct rx_fda_ent* fda_ent_ptr; - struct sk_buff* skb; - - fda_ent_ptr=priv->rx_fda_ptr; - spin_lock(&priv->rx_lock); - while(fda_ent_ptr<(priv->rx_fda_ptr+RX_NUM_FDESC)){ - int result; - - if(!(fda_ent_ptr->fd.FDCtl&FDCTL_COWNSFD_MSK)) - { - /* This frame is ready for processing */ - /*find the corresponding buffer in the bufferlist */ - blist_ent_ptr=priv->rx_blist_vp+fda_ent_ptr->bd.BDStat; - skb=(struct sk_buff*)blist_ent_ptr->fd.FDSystem; - - /* Pass this skb up the stack */ - skb->dev=dev; - skb_put(skb,fda_ent_ptr->fd.FDLength); - skb->protocol=eth_type_trans(skb,dev); - skb->ip_summed=CHECKSUM_UNNECESSARY; - result=netif_rx(skb); - /* Update statistics */ - priv->stats.rx_packets++; - priv->stats.rx_bytes+=fda_ent_ptr->fd.FDLength; - - /* Free the FDA entry */ - fda_ent_ptr->bd.BDStat=0xff; - fda_ent_ptr->fd.FDCtl=FDCTL_COWNSFD_MSK; - - /* Allocate a new skb and point the bd entry to it */ - blist_ent_ptr->fd.FDSystem=0; - skb=dev_alloc_skb(PKT_BUF_SZ); - //printk("allocskb=%#x\n",skb); - if(skb){ - setup_blist_entry(skb,blist_ent_ptr); - - } - else if(!priv->memupdate_scheduled){ - int tmp; - /* There are no buffers at the moment, so schedule */ - /* the background task to sort this out */ - schedule_task(&priv->tq_memupdate); - priv->memupdate_scheduled=1; - printk(KERN_DEBUG "%s:No buffers",dev->name); - /* If this interrupt was due to a lack of buffers then - * we'd better stop the receiver too */ - if(interruptValueÐER_INT_SRC_BLEX_MSK){ - priv->rx_disabled=1; - tmp=readl(ETHER_INT_SRC(dev->base_addr)); - writel(tmp&~ETHER_RX_CTL_RXEN_MSK,ETHER_RX_CTL(dev->base_addr)); - printk(KERN_DEBUG "%s:Halting rx",dev->name); - } - - } - - } - fda_ent_ptr++; - } - spin_unlock(&priv->rx_lock); - - /* Clear the interrupts */ - writel(ETHER_INT_SRC_INTMACRX_MSK | ETHER_INT_SRC_FDAEX_MSK - | ETHER_INT_SRC_BLEX_MSK,ETHER_INT_SRC(dev->base_addr)); - - } - - if(readl(ETHER_INT_SRC(dev->base_addr))ÐER_INT_SRC_INTMACTX_MSK){ - - if(!priv->memupdate_scheduled){ - schedule_task(&priv->tq_memupdate); - priv->memupdate_scheduled=1; - } - /* Clear the interrupt */ - writel(ETHER_INT_SRC_INTMACTX_MSK,ETHER_INT_SRC(dev->base_addr)); - } - - if (readl(ETHER_INT_SRC(dev->base_addr)) & (ETHER_INT_SRC_SWINT_MSK| - ETHER_INT_SRC_INTEARNOT_MSK| - ETHER_INT_SRC_INTLINK_MSK| - ETHER_INT_SRC_INTEXBD_MSK| - ETHER_INT_SRC_INTTXCTLCMP_MSK)) - { - /* - * Not using any of these so they shouldn't happen - * - * In the cased of INTEXBD - if you allocate more - * than 28 decsriptors you may need to think about this - */ - printk("Not using this interrupt\n"); - } - - if (readl(ETHER_INT_SRC(dev->base_addr)) & - (ETHER_INT_SRC_INTSBUS_MSK | - ETHER_INT_SRC_INTNRABT_MSK - |ETHER_INT_SRC_DMPARERR_MSK)) - { - /* - * Hardware errors, we can either ignore them and hope they go away - *or reset the device, I'll try the first for now to see if they happen - */ - printk("Hardware error\n"); - } -} - -static void ether00_setup_ethernet_address(struct net_device* dev) -{ - int tmp; - - dev->addr_len=6; - writew(0,ETHER_ARC_ADR(dev->base_addr)); - writel((dev->dev_addr[0]<<24) | - (dev->dev_addr[1]<<16) | - (dev->dev_addr[2]<<8) | - dev->dev_addr[3], - ETHER_ARC_DATA(dev->base_addr)); - - writew(4,ETHER_ARC_ADR(dev->base_addr)); - tmp=readl(ETHER_ARC_DATA(dev->base_addr)); - tmp&=0xffff; - tmp|=(dev->dev_addr[4]<<24) | (dev->dev_addr[5]<<16); - writel(tmp, ETHER_ARC_DATA(dev->base_addr)); - /* Enable this entry in the ARC */ - - writel(1,ETHER_ARC_ENA(dev->base_addr)); - - return; -} - - -static void ether00_reset(struct net_device *dev) -{ - /* reset the controller */ - writew(ETHER_MAC_CTL_RESET_MSK,ETHER_MAC_CTL(dev->base_addr)); - - /* - * Make sure we're not going to send anything - */ - - writew(ETHER_TX_CTL_TXHALT_MSK,ETHER_TX_CTL(dev->base_addr)); - - /* - * Make sure we're not going to receive anything - */ - writew(ETHER_RX_CTL_RXHALT_MSK,ETHER_RX_CTL(dev->base_addr)); - - /* - * Disable Interrupts for now, and set the burst size to 8 bytes - */ - - writel(ETHER_DMA_CTL_INTMASK_MSK | - ((8 << ETHER_DMA_CTL_DMBURST_OFST) & ETHER_DMA_CTL_DMBURST_MSK) - |(2<<ETHER_DMA_CTL_RXALIGN_OFST), - ETHER_DMA_CTL(dev->base_addr)); - - - /* - * Set TxThrsh - start transmitting a packet after 1514 - * bytes or when a packet is complete, whichever comes first - */ - writew(1514,ETHER_TXTHRSH(dev->base_addr)); - - /* - * Set TxPollCtr. Each cycle is - * 61.44 microseconds with a 33 MHz bus - */ - writew(1,ETHER_TXPOLLCTR(dev->base_addr)); - - /* - * Set Rx_Ctl - Turn off reception and let RxData turn it - * on later - */ - writew(ETHER_RX_CTL_RXHALT_MSK,ETHER_RX_CTL(dev->base_addr)); - -} - - -static void ether00_set_multicast(struct net_device* dev) -{ - int count=dev->mc_count; - - /* Set promiscuous mode if it's asked for. */ - - if (dev->flags&IFF_PROMISC){ - - writew( ETHER_ARC_CTL_COMPEN_MSK | - ETHER_ARC_CTL_BROADACC_MSK | - ETHER_ARC_CTL_GROUPACC_MSK | - ETHER_ARC_CTL_STATIONACC_MSK, - ETHER_ARC_CTL(dev->base_addr)); - return; - } - - /* - * Get all multicast packets if required, or if there are too - * many addresses to fit in hardware - */ - if (dev->flags & IFF_ALLMULTI){ - writew( ETHER_ARC_CTL_COMPEN_MSK | - ETHER_ARC_CTL_GROUPACC_MSK | - ETHER_ARC_CTL_BROADACC_MSK, - ETHER_ARC_CTL(dev->base_addr)); - return; - } - if (dev->mc_count > (ETHER_ARC_SIZE - 1)){ - - printk(KERN_WARNING "Too many multicast addresses for hardware to filter - receiving all multicast packets\n"); - writew( ETHER_ARC_CTL_COMPEN_MSK | - ETHER_ARC_CTL_GROUPACC_MSK | - ETHER_ARC_CTL_BROADACC_MSK, - ETHER_ARC_CTL(dev->base_addr)); - return; - } - - if(dev->mc_count){ - struct dev_mc_list *mc_list_ent=dev->mc_list; - unsigned int temp,i; - DEBUG(printk("mc_count=%d mc_list=%#x\n",dev-> mc_count, dev->mc_list)); - DEBUG(printk("mc addr=%02#x%02x%02x%02x%02x%02x\n", - mc_list_ent->dmi_addr[5], - mc_list_ent->dmi_addr[4], - mc_list_ent->dmi_addr[3], - mc_list_ent->dmi_addr[2], - mc_list_ent->dmi_addr[1], - mc_list_ent->dmi_addr[0]);) - - /* - * The first 6 bytes are the MAC address, so - * don't change them! - */ - writew(4,ETHER_ARC_ADR(dev->base_addr)); - temp=readl(ETHER_ARC_DATA(dev->base_addr)); - temp&=0xffff0000; - - /* Disable the current multicast stuff */ - writel(1,ETHER_ARC_ENA(dev->base_addr)); - - for(;;){ - temp|=mc_list_ent->dmi_addr[1] | - mc_list_ent->dmi_addr[0]<<8; - writel(temp,ETHER_ARC_DATA(dev->base_addr)); - - i=readl(ETHER_ARC_ADR(dev->base_addr)); - writew(i+4,ETHER_ARC_ADR(dev->base_addr)); - - temp=mc_list_ent->dmi_addr[5]| - mc_list_ent->dmi_addr[4]<<8 | - mc_list_ent->dmi_addr[3]<<16 | - mc_list_ent->dmi_addr[2]<<24; - writel(temp,ETHER_ARC_DATA(dev->base_addr)); - - count--; - if(!mc_list_ent->next || !count){ - break; - } - DEBUG(printk("mc_list_next=%#x\n",mc_list_ent->next);) - mc_list_ent=mc_list_ent->next; - - - i=readl(ETHER_ARC_ADR(dev->base_addr)); - writel(i+4,ETHER_ARC_ADR(dev->base_addr)); - - temp=mc_list_ent->dmi_addr[3]| - mc_list_ent->dmi_addr[2]<<8 | - mc_list_ent->dmi_addr[1]<<16 | - mc_list_ent->dmi_addr[0]<<24; - writel(temp,ETHER_ARC_DATA(dev->base_addr)); - - i=readl(ETHER_ARC_ADR(dev->base_addr)); - writel(i+4,ETHER_ARC_ADR(dev->base_addr)); - - temp=mc_list_ent->dmi_addr[4]<<16 | - mc_list_ent->dmi_addr[5]<<24; - - writel(temp,ETHER_ARC_DATA(dev->base_addr)); - - count--; - if(!mc_list_ent->next || !count){ - break; - } - mc_list_ent=mc_list_ent->next; - } - - - if(count) - printk(KERN_WARNING "Multicast list size error\n"); - - - writew( ETHER_ARC_CTL_BROADACC_MSK| - ETHER_ARC_CTL_COMPEN_MSK, - ETHER_ARC_CTL(dev->base_addr)); - - } - - /* enable the active ARC enties */ - writew((1<<(count+2))-1,ETHER_ARC_ENA(dev->base_addr)); -} - - -static int ether00_open(struct net_device* dev) -{ - int result,tmp; - struct net_priv* priv; - - if (!is_valid_ether_addr(dev->dev_addr)) - return -EINVAL; - - /* Install interrupt handlers */ - result=request_irq(dev->irq,ether00_int,0,"ether00",dev); - if(result) - goto open_err1; - - result=request_irq(2,ether00_phy_int,0,"ether00_phy",dev); - if(result) - goto open_err2; - - ether00_reset(dev); - result=ether00_mem_init(dev); - if(result) - goto open_err3; - - - ether00_setup_ethernet_address(dev); - - ether00_set_multicast(dev); - - result=ether00_write_phy(dev,PHY_CONTROL, PHY_CONTROL_ANEGEN_MSK | PHY_CONTROL_RANEG_MSK); - if(result) - goto open_err4; - result=ether00_write_phy(dev,PHY_IRQ_CONTROL, PHY_IRQ_CONTROL_LS_CHG_IE_MSK | - PHY_IRQ_CONTROL_ANEG_COMP_IE_MSK); - if(result) - goto open_err4; - - /* Start the device enable interrupts */ - writew(ETHER_RX_CTL_RXEN_MSK -// | ETHER_RX_CTL_STRIPCRC_MSK - | ETHER_RX_CTL_ENGOOD_MSK - | ETHER_RX_CTL_ENRXPAR_MSK| ETHER_RX_CTL_ENLONGERR_MSK - | ETHER_RX_CTL_ENOVER_MSK| ETHER_RX_CTL_ENCRCERR_MSK, - ETHER_RX_CTL(dev->base_addr)); - - writew(ETHER_TX_CTL_TXEN_MSK| - ETHER_TX_CTL_ENEXDEFER_MSK| - ETHER_TX_CTL_ENLCARR_MSK| - ETHER_TX_CTL_ENEXCOLL_MSK| - ETHER_TX_CTL_ENLATECOLL_MSK| - ETHER_TX_CTL_ENTXPAR_MSK| - ETHER_TX_CTL_ENCOMP_MSK, - ETHER_TX_CTL(dev->base_addr)); - - tmp=readl(ETHER_DMA_CTL(dev->base_addr)); - writel(tmp&~ETHER_DMA_CTL_INTMASK_MSK,ETHER_DMA_CTL(dev->base_addr)); - - return 0; - - open_err4: - ether00_reset(dev); - open_err3: - free_irq(2,dev); - open_err2: - free_irq(dev->irq,dev); - open_err1: - return result; - -} - - -static int ether00_tx(struct sk_buff* skb, struct net_device* dev) -{ - struct net_priv *priv=dev->priv; - struct tx_fda_ent *fda_ptr; - int i; - - - /* - * Find an empty slot in which to stick the frame - */ - fda_ptr=(struct tx_fda_ent*)__dma_va(readl(ETHER_TXFRMPTR(dev->base_addr))); - i=0; - while(i<TX_NUM_FDESC){ - if (fda_ptr->fd.FDStat||(fda_ptr->fd.FDCtl & FDCTL_COWNSFD_MSK)){ - fda_ptr =(struct tx_fda_ent*) __dma_va((struct tx_fda_ent*)fda_ptr->fd.FDNext); - } - else { - break; - } - i++; - } - - /* Write the skb data from the cache*/ - consistent_sync(skb->data,skb->len,PCI_DMA_TODEVICE); - fda_ptr->bd.BuffData=(char*)__pa(skb->data); - fda_ptr->bd.BuffLength=(unsigned short)skb->len; - /* Save the pointer to the skb for freeing later */ - fda_ptr->fd.FDSystem=(unsigned int)skb; - fda_ptr->fd.FDStat=0; - /* Pass ownership of the buffers to the controller */ - fda_ptr->fd.FDCtl=1; - fda_ptr->fd.FDCtl|=FDCTL_COWNSFD_MSK; - - /* If the next buffer in the list is full, stop the queue */ - fda_ptr=(struct tx_fda_ent*)__dma_va(fda_ptr->fd.FDNext); - if ((fda_ptr->fd.FDStat)||(fda_ptr->fd.FDCtl & FDCTL_COWNSFD_MSK)){ - netif_stop_queue(dev); - priv->queue_stopped=1; - } - - return 0; -} - -static struct net_device_stats *ether00_stats(struct net_device* dev) -{ - struct net_priv *priv=dev->priv; - return &priv->stats; -} - - -static int ether00_stop(struct net_device* dev) -{ - struct net_priv *priv=dev->priv; - int tmp; - - /* Stop/disable the device. */ - tmp=readw(ETHER_RX_CTL(dev->base_addr)); - tmp&=~(ETHER_RX_CTL_RXEN_MSK | ETHER_RX_CTL_ENGOOD_MSK); - tmp|=ETHER_RX_CTL_RXHALT_MSK; - writew(tmp,ETHER_RX_CTL(dev->base_addr)); - - tmp=readl(ETHER_TX_CTL(dev->base_addr)); - tmp&=~ETHER_TX_CTL_TXEN_MSK; - tmp|=ETHER_TX_CTL_TXHALT_MSK; - writel(tmp,ETHER_TX_CTL(dev->base_addr)); - - /* Free up system resources */ - free_irq(dev->irq,dev); - free_irq(2,dev); - iounmap(priv->dma_data); - - return 0; -} - - -static void ether00_get_ethernet_address(struct net_device* dev) -{ - struct mtd_info *mymtd=NULL; - int i; - size_t retlen; - - /* - * For the Epxa10 dev board (camelot), the ethernet MAC - * address is of the form 00:aa:aa:00:xx:xx where - * 00:aa:aa is the Altera vendor ID and xx:xx is the - * last 2 bytes of the board serial number, as programmed - * into the OTP area of the flash device on EBI1. If this - * isn't an expa10 dev board, or there's no mtd support to - * read the serial number from flash then we'll force the - * use to set their own mac address using ifconfig. - */ - -#ifdef CONFIG_ARCH_CAMELOT -#ifdef CONFIG_MTD - /* get the mtd_info structure for the first mtd device*/ - for(i=0;i<MAX_MTD_DEVICES;i++){ - mymtd=get_mtd_device(NULL,i); - if(!mymtd||!strcmp(mymtd->name,"EPXA10DB flash")) - break; - } - - if(!mymtd || !mymtd->read_user_prot_reg){ - printk(KERN_WARNING "%s: Failed to read MAC address from flash\n",dev->name); - }else{ - mymtd->read_user_prot_reg(mymtd,2,1,&retlen,&dev->dev_addr[5]); - mymtd->read_user_prot_reg(mymtd,3,1,&retlen,&dev->dev_addr[4]); - dev->dev_addr[3]=0; - dev->dev_addr[2]=vendor_id[1]; - dev->dev_addr[1]=vendor_id[0]; - dev->dev_addr[0]=0; - } -#else - printk(KERN_WARNING "%s: MTD support required to read MAC address from EPXA10 dev board\n", dev->name); -#endif -#endif - - if (!is_valid_ether_addr(dev->dev_addr)) - printk("%s: Invalid ethernet MAC address. Please set using " - "ifconfig\n", dev->name); - -} - -/* - * Keep a mapping of dev_info addresses -> port lines to use when - * removing ports dev==NULL indicates unused entry - */ - - -static struct net_device* dev_list[ETH_NR]; - -static int ether00_add_device(struct pldhs_dev_info* dev_info,void* dev_ps_data) -{ - struct net_device *dev; - struct net_priv *priv; - void *map_addr; - int result; - int i; - - i=0; - while(dev_list[i] && i < ETH_NR) - i++; - - if(i==ETH_NR){ - printk(KERN_WARNING "ether00: Maximum number of ports reached\n"); - return 0; - } - - - if (!request_mem_region(dev_info->base_addr, MAC_REG_SIZE, "ether00")) - return -EBUSY; - - dev = alloc_etherdev(sizeof(struct net_priv)); - if(!dev) { - result = -ENOMEM; - goto out_release; - } - priv = dev->priv; - - priv->tq_memupdate.routine=ether00_mem_update; - priv->tq_memupdate.data=(void*) dev; - - spin_lock_init(&priv->rx_lock); - - map_addr=ioremap_nocache(dev_info->base_addr,SZ_4K); - if(!map_addr){ - result = -ENOMEM; - out_kfree; - } - - dev->open=ether00_open; - dev->stop=ether00_stop; - dev->set_multicast_list=ether00_set_multicast; - dev->hard_start_xmit=ether00_tx; - dev->get_stats=ether00_stats; - - ether00_get_ethernet_address(dev); - - SET_MODULE_OWNER(dev); - - dev->base_addr=(unsigned int)map_addr; - dev->irq=dev_info->irq; - dev->features=NETIF_F_DYNALLOC | NETIF_F_HW_CSUM; - - result=register_netdev(dev); - if(result){ - printk("Ether00: Error %i registering driver\n",result); - goto out_unmap; - } - printk("registered ether00 device at %#x\n",dev_info->base_addr); - - dev_list[i]=dev; - - return result; - - out_unmap: - iounmap(map_addr); - out_kfree: - free_netdev(dev); - out_release: - release_mem_region(dev_info->base_addr, MAC_REG_SIZE); - return result; -} - - -static int ether00_remove_devices(void) -{ - int i; - - for(i=0;i<ETH_NR;i++){ - if(dev_list[i]){ - netif_device_detach(dev_list[i]); - unregister_netdev(dev_list[i]); - iounmap((void*)dev_list[i]->base_addr); - release_mem_region(dev_list[i]->base_addr, MAC_REG_SIZE); - free_netdev(dev_list[i]); - dev_list[i]=0; - } - } - return 0; -} - -static struct pld_hotswap_ops ether00_pldhs_ops={ - .name = ETHER00_NAME, - .add_device = ether00_add_device, - .remove_devices = ether00_remove_devices, -}; - - -static void __exit ether00_cleanup_module(void) -{ - int result; - result=ether00_remove_devices(); - if(result) - printk(KERN_WARNING "ether00: failed to remove all devices\n"); - - pldhs_unregister_driver(ETHER00_NAME); -} -module_exit(ether00_cleanup_module); - - -static int __init ether00_mod_init(void) -{ - printk("mod init\n"); - return pldhs_register_driver(ðer00_pldhs_ops); - -} - -module_init(ether00_mod_init); - diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 812bae62c8e..47ea8338c03 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -359,29 +359,6 @@ config SERIAL_21285_CONSOLE your boot loader (lilo or loadlin) about how to pass options to the kernel at boot time.) -config SERIAL_UART00 - bool "Excalibur serial port (uart00) support" - depends on ARM && ARCH_CAMELOT - select SERIAL_CORE - help - Say Y here if you want to use the hard logic uart on Excalibur. This - driver also supports soft logic implementations of this uart core. - -config SERIAL_UART00_CONSOLE - bool "Support for console on Excalibur serial port" - depends on SERIAL_UART00 - select SERIAL_CORE_CONSOLE - help - Say Y here if you want to support a serial console on an Excalibur - hard logic uart or uart00 IP core. - - Even if you say Y here, the currently visible virtual console - (/dev/tty0) will still be used as the system console by default, but - you can alter that using a kernel command line option such as - "console=ttyS1". (Try "man bootparam" or see the documentation of - your boot loader (lilo or loadlin) about how to pass options to the - kernel at boot time.) - config SERIAL_MPSC bool "Marvell MPSC serial port support" depends on PPC32 && MV64X60 diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index d7c7c7180e3..137148bba4f 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -29,7 +29,6 @@ obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o obj-$(CONFIG_SERIAL_PXA) += pxa.o obj-$(CONFIG_SERIAL_SA1100) += sa1100.o obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o -obj-$(CONFIG_SERIAL_UART00) += uart00.o obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o diff --git a/drivers/serial/uart00.c b/drivers/serial/uart00.c deleted file mode 100644 index 47b504ff38b..00000000000 --- a/drivers/serial/uart00.c +++ /dev/null @@ -1,782 +0,0 @@ -/* - * linux/drivers/serial/uart00.c - * - * Driver for UART00 serial ports - * - * Based on drivers/char/serial_amba.c, by ARM Limited & - * Deep Blue Solutions Ltd. - * Copyright 2001 Altera Corporation - * - * Update for 2.6.4 by Dirk Behme <dirk.behme@de.bosch.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * $Id: uart00.c,v 1.35 2002/07/28 10:03:28 rmk Exp $ - * - */ -#include <linux/config.h> - -#if defined(CONFIG_SERIAL_UART00_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) -#define SUPPORT_SYSRQ -#endif - -#include <linux/module.h> -#include <linux/ioport.h> -#include <linux/init.h> -#include <linux/console.h> -#include <linux/sysrq.h> -#include <linux/tty.h> -#include <linux/tty_flip.h> -#include <linux/serial_core.h> -#include <linux/serial.h> - -#include <asm/io.h> -#include <asm/irq.h> -#include <asm/sizes.h> - -#include <asm/arch/excalibur.h> -#define UART00_TYPE (volatile unsigned int*) -#include <asm/arch/uart00.h> -#include <asm/arch/int_ctrl00.h> - -#define UART_NR 2 - -#define SERIAL_UART00_NAME "ttyUA" -#define SERIAL_UART00_MAJOR 204 -#define SERIAL_UART00_MINOR 16 /* Temporary - will change in future */ -#define SERIAL_UART00_NR UART_NR -#define UART_PORT_SIZE 0x50 - -#define UART00_ISR_PASS_LIMIT 256 - -/* - * Access macros for the UART00 UARTs - */ -#define UART_GET_INT_STATUS(p) inl(UART_ISR((p)->membase)) -#define UART_PUT_IES(p, c) outl(c,UART_IES((p)->membase)) -#define UART_GET_IES(p) inl(UART_IES((p)->membase)) -#define UART_PUT_IEC(p, c) outl(c,UART_IEC((p)->membase)) -#define UART_GET_IEC(p) inl(UART_IEC((p)->membase)) -#define UART_PUT_CHAR(p, c) outl(c,UART_TD((p)->membase)) -#define UART_GET_CHAR(p) inl(UART_RD((p)->membase)) -#define UART_GET_RSR(p) inl(UART_RSR((p)->membase)) -#define UART_GET_RDS(p) inl(UART_RDS((p)->membase)) -#define UART_GET_MSR(p) inl(UART_MSR((p)->membase)) -#define UART_GET_MCR(p) inl(UART_MCR((p)->membase)) -#define UART_PUT_MCR(p, c) outl(c,UART_MCR((p)->membase)) -#define UART_GET_MC(p) inl(UART_MC((p)->membase)) -#define UART_PUT_MC(p, c) outl(c,UART_MC((p)->membase)) -#define UART_GET_TSR(p) inl(UART_TSR((p)->membase)) -#define UART_GET_DIV_HI(p) inl(UART_DIV_HI((p)->membase)) -#define UART_PUT_DIV_HI(p,c) outl(c,UART_DIV_HI((p)->membase)) -#define UART_GET_DIV_LO(p) inl(UART_DIV_LO((p)->membase)) -#define UART_PUT_DIV_LO(p,c) outl(c,UART_DIV_LO((p)->membase)) -#define UART_RX_DATA(s) ((s) & UART_RSR_RX_LEVEL_MSK) -#define UART_TX_READY(s) (((s) & UART_TSR_TX_LEVEL_MSK) < 15) -//#define UART_TX_EMPTY(p) ((UART_GET_FR(p) & UART00_UARTFR_TMSK) == 0) - -static void uart00_stop_tx(struct uart_port *port) -{ - UART_PUT_IEC(port, UART_IEC_TIE_MSK); -} - -static void uart00_stop_rx(struct uart_port *port) -{ - UART_PUT_IEC(port, UART_IEC_RE_MSK); -} - -static void uart00_enable_ms(struct uart_port *port) -{ - UART_PUT_IES(port, UART_IES_ME_MSK); -} - -static void -uart00_rx_chars(struct uart_port *port, struct pt_regs *regs) -{ - struct tty_struct *tty = port->info->tty; - unsigned int status, ch, rds, flg, ignored = 0; - - status = UART_GET_RSR(port); - while (UART_RX_DATA(status)) { - /* - * We need to read rds before reading the - * character from the fifo - */ - rds = UART_GET_RDS(port); - ch = UART_GET_CHAR(port); - port->icount.rx++; - - if (tty->flip.count >= TTY_FLIPBUF_SIZE) - goto ignore_char; - - flg = TTY_NORMAL; - - /* - * Note that the error handling code is - * out of the main execution path - */ - if (rds & (UART_RDS_BI_MSK |UART_RDS_FE_MSK| - UART_RDS_PE_MSK |UART_RDS_PE_MSK)) - goto handle_error; - if (uart_handle_sysrq_char(port, ch, regs)) - goto ignore_char; - - error_return: - tty_insert_flip_char(tty, ch, flg); - - ignore_char: - status = UART_GET_RSR(port); - } - out: - tty_flip_buffer_push(tty); - return; - - handle_error: - if (rds & UART_RDS_BI_MSK) { - status &= ~(UART_RDS_FE_MSK | UART_RDS_PE_MSK); - port->icount.brk++; - if (uart_handle_break(port)) - goto ignore_char; - } else if (rds & UART_RDS_PE_MSK) - port->icount.parity++; - else if (rds & UART_RDS_FE_MSK) - port->icount.frame++; - if (rds & UART_RDS_OE_MSK) - port->icount.overrun++; - - if (rds & port->ignore_status_mask) { - if (++ignored > 100) - goto out; - goto ignore_char; - } - rds &= port->read_status_mask; - - if (rds & UART_RDS_BI_MSK) - flg = TTY_BREAK; - else if (rds & UART_RDS_PE_MSK) - flg = TTY_PARITY; - else if (rds & UART_RDS_FE_MSK) - flg = TTY_FRAME; - - if (rds & UART_RDS_OE_MSK) { - /* - * CHECK: does overrun affect the current character? - * ASSUMPTION: it does not. - */ - tty_insert_flip_char(tty, ch, flg); - ch = 0; - flg = TTY_OVERRUN; - } -#ifdef SUPPORT_SYSRQ - port->sysrq = 0; -#endif - goto error_return; -} - -static void uart00_tx_chars(struct uart_port *port) -{ - struct circ_buf *xmit = &port->info->xmit; - int count; - - if (port->x_char) { - while ((UART_GET_TSR(port) & UART_TSR_TX_LEVEL_MSK) == 15) - barrier(); - UART_PUT_CHAR(port, port->x_char); - port->icount.tx++; - port->x_char = 0; - return; - } - if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { - uart00_stop_tx(port); - return; - } - - count = port->fifosize >> 1; - do { - while ((UART_GET_TSR(port) & UART_TSR_TX_LEVEL_MSK) == 15) - barrier(); - UART_PUT_CHAR(port, xmit->buf[xmit->tail]); - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); - port->icount.tx++; - if (uart_circ_empty(xmit)) - break; - } while (--count > 0); - - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) - uart_write_wakeup(port); - - if (uart_circ_empty(xmit)) - uart00_stop_tx(port); -} - -static void uart00_start_tx(struct uart_port *port) -{ - UART_PUT_IES(port, UART_IES_TIE_MSK); - uart00_tx_chars(port); -} - -static void uart00_modem_status(struct uart_port *port) -{ - unsigned int status; - - status = UART_GET_MSR(port); - - if (!(status & (UART_MSR_DCTS_MSK | UART_MSR_DDSR_MSK | - UART_MSR_TERI_MSK | UART_MSR_DDCD_MSK))) - return; - - if (status & UART_MSR_DDCD_MSK) - uart_handle_dcd_change(port, status & UART_MSR_DCD_MSK); - - if (status & UART_MSR_DDSR_MSK) - port->icount.dsr++; - - if (status & UART_MSR_DCTS_MSK) - uart_handle_cts_change(port, status & UART_MSR_CTS_MSK); - - wake_up_interruptible(&port->info->delta_msr_wait); -} - -static irqreturn_t uart00_int(int irq, void *dev_id, struct pt_regs *regs) -{ - struct uart_port *port = dev_id; - unsigned int status, pass_counter = 0; - - status = UART_GET_INT_STATUS(port); - do { - if (status & UART_ISR_RI_MSK) - uart00_rx_chars(port, regs); - if (status & UART_ISR_MI_MSK) - uart00_modem_status(port); - if (status & (UART_ISR_TI_MSK | UART_ISR_TII_MSK)) - uart00_tx_chars(port); - if (pass_counter++ > UART00_ISR_PASS_LIMIT) - break; - - status = UART_GET_INT_STATUS(port); - } while (status); - - return IRQ_HANDLED; -} - -static unsigned int uart00_tx_empty(struct uart_port *port) -{ - return UART_GET_TSR(port) & UART_TSR_TX_LEVEL_MSK? 0 : TIOCSER_TEMT; -} - -static unsigned int uart00_get_mctrl(struct uart_port *port) -{ - unsigned int result = 0; - unsigned int status; - - status = UART_GET_MSR(port); - if (status & UART_MSR_DCD_MSK) - result |= TIOCM_CAR; - if (status & UART_MSR_DSR_MSK) - result |= TIOCM_DSR; - if (status & UART_MSR_CTS_MSK) - result |= TIOCM_CTS; - if (status & UART_MSR_RI_MSK) - result |= TIOCM_RI; - - return result; -} - -static void uart00_set_mctrl_null(struct uart_port *port, unsigned int mctrl) -{ -} - -static void uart00_break_ctl(struct uart_port *port, int break_state) -{ - unsigned long flags; - unsigned int mcr; - - spin_lock_irqsave(&port->lock, flags); - mcr = UART_GET_MCR(port); - if (break_state == -1) - mcr |= UART_MCR_BR_MSK; - else - mcr &= ~UART_MCR_BR_MSK; - UART_PUT_MCR(port, mcr); - spin_unlock_irqrestore(&port->lock, flags); -} - -static void -uart00_set_termios(struct uart_port *port, struct termios *termios, - struct termios *old) -{ - unsigned int uart_mc, old_ies, baud, quot; - unsigned long flags; - - /* - * We don't support CREAD (yet) - */ - termios->c_cflag |= CREAD; - - /* - * Ask the core to calculate the divisor for us. - */ - baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); - quot = uart_get_divisor(port, baud); - - /* byte size and parity */ - switch (termios->c_cflag & CSIZE) { - case CS5: - uart_mc = UART_MC_CLS_CHARLEN_5; - break; - case CS6: - uart_mc = UART_MC_CLS_CHARLEN_6; - break; - case CS7: - uart_mc = UART_MC_CLS_CHARLEN_7; - break; - default: // CS8 - uart_mc = UART_MC_CLS_CHARLEN_8; - break; - } - if (termios->c_cflag & CSTOPB) - uart_mc|= UART_MC_ST_TWO; - if (termios->c_cflag & PARENB) { - uart_mc |= UART_MC_PE_MSK; - if (!(termios->c_cflag & PARODD)) - uart_mc |= UART_MC_EP_MSK; - } - - spin_lock_irqsave(&port->lock, flags); - - /* - * Update the per-port timeout. - */ - uart_update_timeout(port, termios->c_cflag, baud); - - port->read_status_mask = UART_RDS_OE_MSK; - if (termios->c_iflag & INPCK) - port->read_status_mask |= UART_RDS_FE_MSK | UART_RDS_PE_MSK; - if (termios->c_iflag & (BRKINT | PARMRK)) - port->read_status_mask |= UART_RDS_BI_MSK; - - /* - * Characters to ignore - */ - port->ignore_status_mask = 0; - if (termios->c_iflag & IGNPAR) - port->ignore_status_mask |= UART_RDS_FE_MSK | UART_RDS_PE_MSK; - if (termios->c_iflag & IGNBRK) { - port->ignore_status_mask |= UART_RDS_BI_MSK; - /* - * If we're ignoring parity and break indicators, - * ignore overruns to (for real raw support). - */ - if (termios->c_iflag & IGNPAR) - port->ignore_status_mask |= UART_RDS_OE_MSK; - } - - /* first, disable everything */ - old_ies = UART_GET_IES(port); - - if (UART_ENABLE_MS(port, termios->c_cflag)) - old_ies |= UART_IES_ME_MSK; - - /* Set baud rate */ - UART_PUT_DIV_LO(port, (quot & 0xff)); - UART_PUT_DIV_HI(port, ((quot & 0xf00) >> 8)); - - UART_PUT_MC(port, uart_mc); - UART_PUT_IES(port, old_ies); - - spin_unlock_irqrestore(&port->lock, flags); -} - -static int uart00_startup(struct uart_port *port) -{ - int result; - - /* - * Allocate the IRQ - */ - result = request_irq(port->irq, uart00_int, 0, "uart00", port); - if (result) { - printk(KERN_ERR "Request of irq %d failed\n", port->irq); - return result; - } - - /* - * Finally, enable interrupts. Use the TII interrupt to minimise - * the number of interrupts generated. If higher performance is - * needed, consider using the TI interrupt with a suitable FIFO - * threshold - */ - UART_PUT_IES(port, UART_IES_RE_MSK | UART_IES_TIE_MSK); - - return 0; -} - -static void uart00_shutdown(struct uart_port *port) -{ - /* - * disable all interrupts, disable the port - */ - UART_PUT_IEC(port, 0xff); - - /* disable break condition and fifos */ - UART_PUT_MCR(port, UART_GET_MCR(port) &~UART_MCR_BR_MSK); - - /* - * Free the interrupt - */ - free_irq(port->irq, port); -} - -static const char *uart00_type(struct uart_port *port) -{ - return port->type == PORT_UART00 ? "Altera UART00" : NULL; -} - -/* - * Release the memory region(s) being used by 'port' - */ -static void uart00_release_port(struct uart_port *port) -{ - release_mem_region(port->mapbase, UART_PORT_SIZE); - -#ifdef CONFIG_ARCH_CAMELOT - if (port->membase != (void*)IO_ADDRESS(EXC_UART00_BASE)) { - iounmap(port->membase); - } -#endif -} - -/* - * Request the memory region(s) being used by 'port' - */ -static int uart00_request_port(struct uart_port *port) -{ - return request_mem_region(port->mapbase, UART_PORT_SIZE, "serial_uart00") - != NULL ? 0 : -EBUSY; -} - -/* - * Configure/autoconfigure the port. - */ -static void uart00_config_port(struct uart_port *port, int flags) -{ - - /* - * Map the io memory if this is a soft uart - */ - if (!port->membase) - port->membase = ioremap_nocache(port->mapbase,SZ_4K); - - if (!port->membase) - printk(KERN_ERR "serial00: cannot map io memory\n"); - else - port->type = PORT_UART00; - -} - -/* - * verify the new serial_struct (for TIOCSSERIAL). - */ -static int uart00_verify_port(struct uart_port *port, struct serial_struct *ser) -{ - int ret = 0; - if (ser->type != PORT_UNKNOWN && ser->type != PORT_UART00) - ret = -EINVAL; - if (ser->irq < 0 || ser->irq >= NR_IRQS) - ret = -EINVAL; - if (ser->baud_base < 9600) - ret = -EINVAL; - return ret; -} - -static struct uart_ops uart00_pops = { - .tx_empty = uart00_tx_empty, - .set_mctrl = uart00_set_mctrl_null, - .get_mctrl = uart00_get_mctrl, - .stop_tx = uart00_stop_tx, - .start_tx = uart00_start_tx, - .stop_rx = uart00_stop_rx, - .enable_ms = uart00_enable_ms, - .break_ctl = uart00_break_ctl, - .startup = uart00_startup, - .shutdown = uart00_shutdown, - .set_termios = uart00_set_termios, - .type = uart00_type, - .release_port = uart00_release_port, - .request_port = uart00_request_port, - .config_port = uart00_config_port, - .verify_port = uart00_verify_port, -}; - - -#ifdef CONFIG_ARCH_CAMELOT -static struct uart_port epxa10db_port = { - .membase = (void*)IO_ADDRESS(EXC_UART00_BASE), - .mapbase = EXC_UART00_BASE, - .iotype = SERIAL_IO_MEM, - .irq = IRQ_UART, - .uartclk = EXC_AHB2_CLK_FREQUENCY, - .fifosize = 16, - .ops = &uart00_pops, - .flags = ASYNC_BOOT_AUTOCONF, -}; -#endif - - -#ifdef CONFIG_SERIAL_UART00_CONSOLE -static void uart00_console_write(struct console *co, const char *s, unsigned count) -{ -#ifdef CONFIG_ARCH_CAMELOT - struct uart_port *port = &epxa10db_port; - unsigned int status, old_ies; - int i; - - /* - * First save the CR then disable the interrupts - */ - old_ies = UART_GET_IES(port); - UART_PUT_IEC(port,0xff); - - /* - * Now, do each character - */ - for (i = 0; i < count; i++) { - do { - status = UART_GET_TSR(port); - } while (!UART_TX_READY(status)); - UART_PUT_CHAR(port, s[i]); - if (s[i] == '\n') { - do { - status = UART_GET_TSR(port); - } while (!UART_TX_READY(status)); - UART_PUT_CHAR(port, '\r'); - } - } - - /* - * Finally, wait for transmitter to become empty - * and restore the IES - */ - do { - status = UART_GET_TSR(port); - } while (status & UART_TSR_TX_LEVEL_MSK); - UART_PUT_IES(port, old_ies); -#endif -} - -static void __init -uart00_console_get_options(struct uart_port *port, int *baud, - int *parity, int *bits) -{ - unsigned int uart_mc, quot; - - uart_mc = UART_GET_MC(port); - - *parity = 'n'; - if (uart_mc & UART_MC_PE_MSK) { - if (uart_mc & UART_MC_EP_MSK) - *parity = 'e'; - else - *parity = 'o'; - } - - switch (uart_mc & UART_MC_CLS_MSK) { - case UART_MC_CLS_CHARLEN_5: - *bits = 5; - break; - case UART_MC_CLS_CHARLEN_6: - *bits = 6; - break; - case UART_MC_CLS_CHARLEN_7: - *bits = 7; - break; - case UART_MC_CLS_CHARLEN_8: - *bits = 8; - break; - } - quot = UART_GET_DIV_LO(port) | (UART_GET_DIV_HI(port) << 8); - *baud = port->uartclk / (16 *quot ); -} - -static int __init uart00_console_setup(struct console *co, char *options) -{ - struct uart_port *port; - int baud = 115200; - int bits = 8; - int parity = 'n'; - int flow = 'n'; - -#ifdef CONFIG_ARCH_CAMELOT - port = &epxa10db_port; ; -#else - return -ENODEV; -#endif - if (options) - uart_parse_options(options, &baud, &parity, &bits, &flow); - else - uart00_console_get_options(port, &baud, &parity, &bits); - - return uart_set_options(port, co, baud, parity, bits, flow); -} - -extern struct uart_driver uart00_reg; -static struct console uart00_console = { - .name = SERIAL_UART00_NAME, - .write = uart00_console_write, - .device = uart_console_device, - .setup = uart00_console_setup, - .flags = CON_PRINTBUFFER, - .index = 0, - .data = &uart00_reg, -}; - -static int __init uart00_console_init(void) -{ - register_console(&uart00_console); - return 0; -} -console_initcall(uart00_console_init); - -#define UART00_CONSOLE &uart00_console -#else -#define UART00_CONSOLE NULL -#endif - -static struct uart_driver uart00_reg = { - .owner = NULL, - .driver_name = SERIAL_UART00_NAME, - .dev_name = SERIAL_UART00_NAME, - .major = SERIAL_UART00_MAJOR, - .minor = SERIAL_UART00_MINOR, - .nr = UART_NR, - .cons = UART00_CONSOLE, -}; - -struct dev_port_entry{ - unsigned int base_addr; - struct uart_port *port; -}; - -#ifdef CONFIG_PLD_HOTSWAP - -static struct dev_port_entry dev_port_map[UART_NR]; - -/* - * Keep a mapping of dev_info addresses -> port lines to use when - * removing ports dev==NULL indicates unused entry - */ - -struct uart00_ps_data{ - unsigned int clk; - unsigned int fifosize; -}; - -int uart00_add_device(struct pldhs_dev_info* dev_info, void* dev_ps_data) -{ - struct uart00_ps_data* dev_ps=dev_ps_data; - struct uart_port * port; - int i,result; - - i=0; - while(dev_port_map[i].port) - i++; - - if(i==UART_NR){ - printk(KERN_WARNING "uart00: Maximum number of ports reached\n"); - return 0; - } - - port=kmalloc(sizeof(struct uart_port),GFP_KERNEL); - if(!port) - return -ENOMEM; - - printk("clk=%d fifo=%d\n",dev_ps->clk,dev_ps->fifosize); - port->membase=0; - port->mapbase=dev_info->base_addr; - port->iotype=SERIAL_IO_MEM; - port->irq=dev_info->irq; - port->uartclk=dev_ps->clk; - port->fifosize=dev_ps->fifosize; - port->ops=&uart00_pops; - port->line=i; - port->flags=ASYNC_BOOT_AUTOCONF; - - result=uart_add_one_port(&uart00_reg, port); - if(result){ - printk("uart_add_one_port returned %d\n",result); - return result; - } - dev_port_map[i].base_addr=dev_info->base_addr; - dev_port_map[i].port=port; - printk("uart00: added device at %x as ttyUA%d\n",dev_port_map[i].base_addr,i); - return 0; - -} - -int uart00_remove_devices(void) -{ - int i,result; - - - result=0; - for(i=1;i<UART_NR;i++){ - if(dev_port_map[i].base_addr){ - result=uart_remove_one_port(&uart00_reg, dev_port_map[i].port); - if(result) - return result; - - /* port removed sucessfully, so now tidy up */ - kfree(dev_port_map[i].port); - dev_port_map[i].base_addr=0; - dev_port_map[i].port=NULL; - } - } - return 0; - -} - -struct pld_hotswap_ops uart00_pldhs_ops={ - .name = "uart00", - .add_device = uart00_add_device, - .remove_devices = uart00_remove_devices, -}; - -#endif - -static int __init uart00_init(void) -{ - int result; - - printk(KERN_INFO "Serial: UART00 driver $Revision: 1.35 $\n"); - - printk(KERN_WARNING "serial_uart00:Using temporary major/minor pairs" - " - these WILL change in the future\n"); - - result = uart_register_driver(&uart00_reg); - if (result) - return result; -#ifdef CONFIG_ARCH_CAMELOT - result = uart_add_one_port(&uart00_reg,&epxa10db_port); -#endif - if (result) - uart_unregister_driver(&uart00_reg); - -#ifdef CONFIG_PLD_HOTSWAP - pldhs_register_driver(&uart00_pldhs_ops); -#endif - return result; -} - -__initcall(uart00_init); diff --git a/include/asm-arm/arch-epxa10db/debug-macro.S b/include/asm-arm/arch-epxa10db/debug-macro.S deleted file mode 100644 index 1d11c51f498..00000000000 --- a/include/asm-arm/arch-epxa10db/debug-macro.S +++ /dev/null @@ -1,41 +0,0 @@ -/* linux/include/asm-arm/arch-epxa10db/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include <asm/arch/excalibur.h> -#define UART00_TYPE -#include <asm/arch/uart00.h> - - .macro addruart,rx - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 @ MMU enabled? - ldr \rx, =EXC_UART00_BASE @ physical base address - orrne \rx, \rx, #0xff000000 @ virtual base - orrne \rx, \rx, #0x00f00000 - .endm - - .macro senduart,rd,rx - str \rd, [\rx, #UART_TD(0)] - .endm - - .macro waituart,rd,rx -1001: ldr \rd, [\rx, #UART_TSR(0)] - and \rd, \rd, #UART_TSR_TX_LEVEL_MSK - cmp \rd, #15 - beq 1001b - .endm - - .macro busyuart,rd,rx -1001: ldr \rd, [\rx, #UART_TSR(0)] - ands \rd, \rd, #UART_TSR_TX_LEVEL_MSK - bne 1001b - .endm diff --git a/include/asm-arm/arch-epxa10db/dma.h b/include/asm-arm/arch-epxa10db/dma.h deleted file mode 100644 index de20ec8e74b..00000000000 --- a/include/asm-arm/arch-epxa10db/dma.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * linux/include/asm-arm/arch-camelot/dma.h - * - * Copyright (C) 1997,1998 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ diff --git a/include/asm-arm/arch-epxa10db/entry-macro.S b/include/asm-arm/arch-epxa10db/entry-macro.S deleted file mode 100644 index de6ae08334e..00000000000 --- a/include/asm-arm/arch-epxa10db/entry-macro.S +++ /dev/null @@ -1,25 +0,0 @@ -/* - * include/asm-arm/arch-epxa10db/entry-macro.S - * - * Low-level IRQ helper macros for epxa10db platform - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <asm/arch/platform.h> -#undef IRQ_MODE /* same name defined in asm/proc/ptrace.h */ -#include <asm/arch/int_ctrl00.h> - - .macro disable_fiq - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - ldr \irqstat, =INT_ID(IO_ADDRESS(EXC_INT_CTRL00_BASE)) - ldr \irqnr,[\irqstat] - cmp \irqnr,#0 - subne \irqnr,\irqnr,#1 - - .endm - diff --git a/include/asm-arm/arch-epxa10db/ether00.h b/include/asm-arm/arch-epxa10db/ether00.h deleted file mode 100644 index b737b8aabe2..00000000000 --- a/include/asm-arm/arch-epxa10db/ether00.h +++ /dev/null @@ -1,482 +0,0 @@ -#ifndef __ETHER00_H -#define __ETHER00_H - - - -/* - * Register definitions for the Ethernet MAC - */ - -/* - * Copyright (c) Altera Corporation 2000. - * All rights reserved. - */ - -/* -* Structures for the DMA controller -*/ -typedef struct fda_desc - { - struct fda_desc * FDNext; - long FDSystem; - long FDStat; - short FDLength; - short FDCtl; - }FDA_DESC; - -typedef struct buf_desc - { - char * BuffData; - short BuffLength; - char BDStat; - char BDCtl; - }BUF_DESC; - -/* -* Control masks for the DMA controller -*/ -#define FDCTL_BDCOUNT_MSK (0x1F) -#define FDCTL_BDCOUNT_OFST (0) -#define FDCTL_FRMOPT_MSK (0x7C00) -#define FDCTL_FRMOPT_OFST (10) -#define FDCTL_COWNSFD_MSK (0x8000) -#define FDCTL_COWNSFD_OFST (15) - -#define BDCTL_RXBDSEQN_MSK (0x7F) -#define BDCTL_RXBDSEQN_OFST (0) -#define BDCTL_COWNSBD_MSK (0x80) -#define BDCTL_COWNSBD_OFST (7) - -#define FDNEXT_EOL_MSK (0x1) -#define FDNEXT_EOL_OFST (0) -#define FDNEXT_EOL_POINTER_MSK (0xFFFFFFF0) -#define FDNEXT_EOL_POINTER_OFST (4) - -#define ETHER_ARC_SIZE (21) - -/* -* Register definitions and masks -*/ -#define ETHER_DMA_CTL(base) (ETHER00_TYPE (base + 0x100)) -#define ETHER_DMA_CTL_DMBURST_OFST (2) -#define ETHER_DMA_CTL_DMBURST_MSK (0x1FC) -#define ETHER_DMA_CTL_POWRMGMNT_OFST (11) -#define ETHER_DMA_CTL_POWRMGMNT_MSK (0x1000) -#define ETHER_DMA_CTL_TXBIGE_OFST (14) -#define ETHER_DMA_CTL_TXBIGE_MSK (0x4000) -#define ETHER_DMA_CTL_RXBIGE_OFST (15) -#define ETHER_DMA_CTL_RXBIGE_MSK (0x8000) -#define ETHER_DMA_CTL_TXWAKEUP_OFST (16) -#define ETHER_DMA_CTL_TXWAKEUP_MSK (0x10000) -#define ETHER_DMA_CTL_SWINTREQ_OFST (17) -#define ETHER_DMA_CTL_SWINTREQ_MSK (0x20000) -#define ETHER_DMA_CTL_INTMASK_OFST (18) -#define ETHER_DMA_CTL_INTMASK_MSK (0x40000) -#define ETHER_DMA_CTL_M66ENSTAT_OFST (19) -#define ETHER_DMA_CTL_M66ENSTAT_MSK (0x80000) -#define ETHER_DMA_CTL_RMTXINIT_OFST (20) -#define ETHER_DMA_CTL_RMTXINIT_MSK (0x100000) -#define ETHER_DMA_CTL_RMRXINIT_OFST (21) -#define ETHER_DMA_CTL_RMRXINIT_MSK (0x200000) -#define ETHER_DMA_CTL_RXALIGN_OFST (22) -#define ETHER_DMA_CTL_RXALIGN_MSK (0xC00000) -#define ETHER_DMA_CTL_RMSWRQ_OFST (24) -#define ETHER_DMA_CTL_RMSWRQ_MSK (0x1000000) -#define ETHER_DMA_CTL_RMEMBANK_OFST (25) -#define ETHER_DMA_CTL_RMEMBANK_MSK (0x2000000) - -#define ETHER_TXFRMPTR(base) (ETHER00_TYPE (base + 0x104)) - -#define ETHER_TXTHRSH(base) (ETHER00_TYPE (base + 0x308)) - -#define ETHER_TXPOLLCTR(base) (ETHER00_TYPE (base + 0x30c)) - -#define ETHER_BLFRMPTR(base) (ETHER00_TYPE (base + 0x110)) -#define ETHER_BLFFRMPTR_EOL_OFST (0) -#define ETHER_BLFFRMPTR_EOL_MSK (0x1) -#define ETHER_BLFFRMPTR_ADDRESS_OFST (4) -#define ETHER_BLFFRMPTR_ADDRESS_MSK (0xFFFFFFF0) - -#define ETHER_RXFRAGSIZE(base) (ETHER00_TYPE (base + 0x114)) -#define ETHER_RXFRAGSIZE_MINFRAG_OFST (2) -#define ETHER_RXFRAGSIZE_MINFRAG_MSK (0xFFC) -#define ETHER_RXFRAGSIZE_ENPACK_OFST (15) -#define ETHER_RXFRAGSIZE_ENPACK_MSK (0x8000) - -#define ETHER_INT_EN(base) (ETHER00_TYPE (base + 0x118)) -#define ETHER_INT_EN_FDAEXEN_OFST (0) -#define ETHER_INT_EN_FDAEXEN_MSK (0x1) -#define ETHER_INT_EN_BLEXEN_OFST (1) -#define ETHER_INT_EN_BLEXN_MSK (0x2) -#define ETHER_INT_EN_STARGABTEN_OFST (2) -#define ETHER_INT_EN_STARGABTEN_MSK (0x4) -#define ETHER_INT_EN_RTARGABTEN_OFST (3) -#define ETHER_INT_EN_RTARGABTEN_MSK (0x8) -#define ETHER_INT_EN_RMASABTEN_OFST (4) -#define ETHER_INT_EN_RMASABTEN_MSK (0x10) -#define ETHER_INT_EN_SSYSERREN_OFST (5) -#define ETHER_INT_EN_SSYSERREN_MSK (0x20) -#define ETHER_INT_EN_DPARERREN_OFST (6) -#define ETHER_INT_EN_DPARERREN_MSK (0x40) -#define ETHER_INT_EN_EARNOTEN_OFST (7) -#define ETHER_INT_EN_EARNOTEN_MSK (0x80) -#define ETHER_INT_EN_DPARDEN_OFST (8) -#define ETHER_INT_EN_DPARDEN_MSK (0x100) -#define ETHER_INT_EN_DMPARERREN_OFST (9) -#define ETHER_INT_EN_DMPARERREN_MSK (0x200) -#define ETHER_INT_EN_TXCTLCMPEN_OFST (10) -#define ETHER_INT_EN_TXCTLCMPEN_MSK (0x400) -#define ETHER_INT_EN_NRABTEN_OFST (11) -#define ETHER_INT_EN_NRABTEN_MSK (0x800) - -#define ETHER_FDA_BAS(base) (ETHER00_TYPE (base + 0x11C)) -#define ETHER_FDA_BAS_ADDRESS_OFST (4) -#define ETHER_FDA_BAS_ADDRESS_MSK (0xFFFFFFF0) - -#define ETHER_FDA_LIM(base) (ETHER00_TYPE (base + 0x120)) -#define ETHER_FDA_LIM_COUNT_OFST (4) -#define ETHER_FDA_LIM_COUNT_MSK (0xFFF0) - -#define ETHER_INT_SRC(base) (ETHER00_TYPE (base + 0x124)) -#define ETHER_INT_SRC_INTMACTX_OFST (0) -#define ETHER_INT_SRC_INTMACTX_MSK (0x1) -#define ETHER_INT_SRC_INTMACRX_OFST (1) -#define ETHER_INT_SRC_INTMACRX_MSK (0x2) -#define ETHER_INT_SRC_INTSBUS_OFST (2) -#define ETHER_INT_SRC_INTSBUS_MSK (0x4) -#define ETHER_INT_SRC_INTFDAEX_OFST (3) -#define ETHER_INT_SRC_INTFDAEX_MSK (0x8) -#define ETHER_INT_SRC_INTBLEX_OFST (4) -#define ETHER_INT_SRC_INTBLEX_MSK (0x10) -#define ETHER_INT_SRC_SWINT_OFST (5) -#define ETHER_INT_SRC_SWINT_MSK (0x20) -#define ETHER_INT_SRC_INTEARNOT_OFST (6) -#define ETHER_INT_SRC_INTEARNOT_MSK (0x40) -#define ETHER_INT_SRC_DMPARERR_OFST (7) -#define ETHER_INT_SRC_DMPARERR_MSK (0x80) -#define ETHER_INT_SRC_INTEXBD_OFST (8) -#define ETHER_INT_SRC_INTEXBD_MSK (0x100) -#define ETHER_INT_SRC_INTTXCTLCMP_OFST (9) -#define ETHER_INT_SRC_INTTXCTLCMP_MSK (0x200) -#define ETHER_INT_SRC_INTNRABT_OFST (10) -#define ETHER_INT_SRC_INTNRABT_MSK (0x400) -#define ETHER_INT_SRC_FDAEX_OFST (11) -#define ETHER_INT_SRC_FDAEX_MSK (0x800) -#define ETHER_INT_SRC_BLEX_OFST (12) -#define ETHER_INT_SRC_BLEX_MSK (0x1000) -#define ETHER_INT_SRC_DMPARERRSTAT_OFST (13) -#define ETHER_INT_SRC_DMPARERRSTAT_MSK (0x2000) -#define ETHER_INT_SRC_NRABT_OFST (14) -#define ETHER_INT_SRC_NRABT_MSK (0x4000) -#define ETHER_INT_SRC_INTLINK_OFST (15) -#define ETHER_INT_SRC_INTLINK_MSK (0x8000) -#define ETHER_INT_SRC_INTEXDEFER_OFST (16) -#define ETHER_INT_SRC_INTEXDEFER_MSK (0x10000) -#define ETHER_INT_SRC_INTRMON_OFST (17) -#define ETHER_INT_SRC_INTRMON_MSK (0x20000) -#define ETHER_INT_SRC_IRQ_MSK (0x83FF) - -#define ETHER_PAUSECNT(base) (ETHER00_TYPE (base + 0x40)) -#define ETHER_PAUSECNT_COUNT_OFST (0) -#define ETHER_PAUSECNT_COUNT_MSK (0xFFFF) - -#define ETHER_REMPAUCNT(base) (ETHER00_TYPE (base + 0x44)) -#define ETHER_REMPAUCNT_COUNT_OFST (0) -#define ETHER_REMPAUCNT_COUNT_MSK (0xFFFF) - -#define ETHER_TXCONFRMSTAT(base) (ETHER00_TYPE (base + 0x348)) -#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_OFST (0) -#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_MSK (0x3FFFFF) - -#define ETHER_MAC_CTL(base) (ETHER00_TYPE (base + 0)) -#define ETHER_MAC_CTL_HALTREQ_OFST (0) -#define ETHER_MAC_CTL_HALTREQ_MSK (0x1) -#define ETHER_MAC_CTL_HALTIMM_OFST (1) -#define ETHER_MAC_CTL_HALTIMM_MSK (0x2) -#define ETHER_MAC_CTL_RESET_OFST (2) -#define ETHER_MAC_CTL_RESET_MSK (0x4) -#define ETHER_MAC_CTL_FULLDUP_OFST (3) -#define ETHER_MAC_CTL_FULLDUP_MSK (0x8) -#define ETHER_MAC_CTL_MACLOOP_OFST (4) -#define ETHER_MAC_CTL_MACLOOP_MSK (0x10) -#define ETHER_MAC_CTL_CONN_OFST (5) -#define ETHER_MAC_CTL_CONN_MSK (0x60) -#define ETHER_MAC_CTL_LOOP10_OFST (7) -#define ETHER_MAC_CTL_LOOP10_MSK (0x80) -#define ETHER_MAC_CTL_LNKCHG_OFST (8) -#define ETHER_MAC_CTL_LNKCHG_MSK (0x100) -#define ETHER_MAC_CTL_MISSROLL_OFST (10) -#define ETHER_MAC_CTL_MISSROLL_MSK (0x400) -#define ETHER_MAC_CTL_ENMISSROLL_OFST (13) -#define ETHER_MAC_CTL_ENMISSROLL_MSK (0x2000) -#define ETHER_MAC_CTL_LINK10_OFST (15) -#define ETHER_MAC_CTL_LINK10_MSK (0x8000) - -#define ETHER_ARC_CTL(base) (ETHER00_TYPE (base + 0x4)) -#define ETHER_ARC_CTL_STATIONACC_OFST (0) -#define ETHER_ARC_CTL_STATIONACC_MSK (0x1) -#define ETHER_ARC_CTL_GROUPACC_OFST (1) -#define ETHER_ARC_CTL_GROUPACC_MSK (0x2) -#define ETHER_ARC_CTL_BROADACC_OFST (2) -#define ETHER_ARC_CTL_BROADACC_MSK (0x4) -#define ETHER_ARC_CTL_NEGARC_OFST (3) -#define ETHER_ARC_CTL_NEGARC_MSK (0x8) -#define ETHER_ARC_CTL_COMPEN_OFST (4) -#define ETHER_ARC_CTL_COMPEN_MSK (0x10) - -#define ETHER_TX_CTL(base) (ETHER00_TYPE (base + 0x8)) -#define ETHER_TX_CTL_TXEN_OFST (0) -#define ETHER_TX_CTL_TXEN_MSK (0x1) -#define ETHER_TX_CTL_TXHALT_OFST (1) -#define ETHER_TX_CTL_TXHALT_MSK (0x2) -#define ETHER_TX_CTL_NOPAD_OFST (2) -#define ETHER_TX_CTL_NOPAD_MSK (0x4) -#define ETHER_TX_CTL_NOCRC_OFST (3) -#define ETHER_TX_CTL_NOCRC_MSK (0x8) -#define ETHER_TX_CTL_FBACK_OFST (4) -#define ETHER_TX_CTL_FBACK_MSK (0x10) -#define ETHER_TX_CTL_NOEXDEF_OFST (5) -#define ETHER_TX_CTL_NOEXDEF_MSK (0x20) -#define ETHER_TX_CTL_SDPAUSE_OFST (6) -#define ETHER_TX_CTL_SDPAUSE_MSK (0x40) -#define ETHER_TX_CTL_MII10_OFST (7) -#define ETHER_TX_CTL_MII10_MSK (0x80) -#define ETHER_TX_CTL_ENUNDER_OFST (8) -#define ETHER_TX_CTL_ENUNDER_MSK (0x100) -#define ETHER_TX_CTL_ENEXDEFER_OFST (9) -#define ETHER_TX_CTL_ENEXDEFER_MSK (0x200) -#define ETHER_TX_CTL_ENLCARR_OFST (10) -#define ETHER_TX_CTL_ENLCARR_MSK (0x400) -#define ETHER_TX_CTL_ENEXCOLL_OFST (11) -#define ETHER_TX_CTL_ENEXCOLL_MSK (0x800) -#define ETHER_TX_CTL_ENLATECOLL_OFST (12) -#define ETHER_TX_CTL_ENLATECOLL_MSK (0x1000) -#define ETHER_TX_CTL_ENTXPAR_OFST (13) -#define ETHER_TX_CTL_ENTXPAR_MSK (0x2000) -#define ETHER_TX_CTL_ENCOMP_OFST (14) -#define ETHER_TX_CTL_ENCOMP_MSK (0x4000) - -#define ETHER_TX_STAT(base) (ETHER00_TYPE (base + 0xc)) -#define ETHER_TX_STAT_TXCOLL_OFST (0) -#define ETHER_TX_STAT_TXCOLL_MSK (0xF) -#define ETHER_TX_STAT_EXCOLL_OFST (4) -#define ETHER_TX_STAT_EXCOLL_MSK (0x10) -#define ETHER_TX_STAT_TXDEFER_OFST (5) -#define ETHER_TX_STAT_TXDEFER_MSK (0x20) -#define ETHER_TX_STAT_PAUSED_OFST (6) -#define ETHER_TX_STAT_PAUSED_MSK (0x40) -#define ETHER_TX_STAT_INTTX_OFST (7) -#define ETHER_TX_STAT_INTTX_MSK (0x80) -#define ETHER_TX_STAT_UNDER_OFST (8) -#define ETHER_TX_STAT_UNDER_MSK (0x100) -#define ETHER_TX_STAT_EXDEFER_OFST (9) -#define ETHER_TX_STAT_EXDEFER_MSK (0x200) -#define ETHER_TX_STAT_LCARR_OFST (10) -#define ETHER_TX_STAT_LCARR_MSK (0x400) -#define ETHER_TX_STAT_TX10STAT_OFST (11) -#define ETHER_TX_STAT_TX10STAT_MSK (0x800) -#define ETHER_TX_STAT_LATECOLL_OFST (12) -#define ETHER_TX_STAT_LATECOLL_MSK (0x1000) -#define ETHER_TX_STAT_TXPAR_OFST (13) -#define ETHER_TX_STAT_TXPAR_MSK (0x2000) -#define ETHER_TX_STAT_COMP_OFST (14) -#define ETHER_TX_STAT_COMP_MSK (0x4000) -#define ETHER_TX_STAT_TXHALTED_OFST (15) -#define ETHER_TX_STAT_TXHALTED_MSK (0x8000) -#define ETHER_TX_STAT_SQERR_OFST (16) -#define ETHER_TX_STAT_SQERR_MSK (0x10000) -#define ETHER_TX_STAT_TXMCAST_OFST (17) -#define ETHER_TX_STAT_TXMCAST_MSK (0x20000) -#define ETHER_TX_STAT_TXBCAST_OFST (18) -#define ETHER_TX_STAT_TXBCAST_MSK (0x40000) -#define ETHER_TX_STAT_VLAN_OFST (19) -#define ETHER_TX_STAT_VLAN_MSK (0x80000) -#define ETHER_TX_STAT_MACC_OFST (20) -#define ETHER_TX_STAT_MACC_MSK (0x100000) -#define ETHER_TX_STAT_TXPAUSE_OFST (21) -#define ETHER_TX_STAT_TXPAUSE_MSK (0x200000) - -#define ETHER_RX_CTL(base) (ETHER00_TYPE (base + 0x10)) -#define ETHER_RX_CTL_RXEN_OFST (0) -#define ETHER_RX_CTL_RXEN_MSK (0x1) -#define ETHER_RX_CTL_RXHALT_OFST (1) -#define ETHER_RX_CTL_RXHALT_MSK (0x2) -#define ETHER_RX_CTL_LONGEN_OFST (2) -#define ETHER_RX_CTL_LONGEN_MSK (0x4) -#define ETHER_RX_CTL_SHORTEN_OFST (3) -#define ETHER_RX_CTL_SHORTEN_MSK (0x8) -#define ETHER_RX_CTL_STRIPCRC_OFST (4) -#define ETHER_RX_CTL_STRIPCRC_MSK (0x10) -#define ETHER_RX_CTL_PASSCTL_OFST (5) -#define ETHER_RX_CTL_PASSCTL_MSK (0x20) -#define ETHER_RX_CTL_IGNORECRC_OFST (6) -#define ETHER_RX_CTL_IGNORECRC_MSK (0x40) -#define ETHER_RX_CTL_ENALIGN_OFST (8) -#define ETHER_RX_CTL_ENALIGN_MSK (0x100) -#define ETHER_RX_CTL_ENCRCERR_OFST (9) -#define ETHER_RX_CTL_ENCRCERR_MSK (0x200) -#define ETHER_RX_CTL_ENOVER_OFST (10) -#define ETHER_RX_CTL_ENOVER_MSK (0x400) -#define ETHER_RX_CTL_ENLONGERR_OFST (11) -#define ETHER_RX_CTL_ENLONGERR_MSK (0x800) -#define ETHER_RX_CTL_ENRXPAR_OFST (13) -#define ETHER_RX_CTL_ENRXPAR_MSK (0x2000) -#define ETHER_RX_CTL_ENGOOD_OFST (14) -#define ETHER_RX_CTL_ENGOOD_MSK (0x4000) - -#define ETHER_RX_STAT(base) (ETHER00_TYPE (base + 0x14)) -#define ETHER_RX_STAT_LENERR_OFST (4) -#define ETHER_RX_STAT_LENERR_MSK (0x10) -#define ETHER_RX_STAT_CTLRECD_OFST (5) -#define ETHER_RX_STAT_CTLRECD_MSK (0x20) -#define ETHER_RX_STAT_INTRX_OFST (6) -#define ETHER_RX_STAT_INTRX_MSK (0x40) -#define ETHER_RX_STAT_RX10STAT_OFST (7) -#define ETHER_RX_STAT_RX10STAT_MSK (0x80) -#define ETHER_RX_STAT_ALIGNERR_OFST (8) -#define ETHER_RX_STAT_ALIGNERR_MSK (0x100) -#define ETHER_RX_STAT_CRCERR_OFST (9) -#define ETHER_RX_STAT_CRCERR_MSK (0x200) -#define ETHER_RX_STAT_OVERFLOW_OFST (10) -#define ETHER_RX_STAT_OVERFLOW_MSK (0x400) -#define ETHER_RX_STAT_LONGERR_OFST (11) -#define ETHER_RX_STAT_LONGERR_MSK (0x800) -#define ETHER_RX_STAT_RXPAR_OFST (13) -#define ETHER_RX_STAT_RXPAR_MSK (0x2000) -#define ETHER_RX_STAT_GOOD_OFST (14) -#define ETHER_RX_STAT_GOOD_MSK (0x4000) -#define ETHER_RX_STAT_RXHALTED_OFST (15) -#define ETHER_RX_STAT_RXHALTED_MSK (0x8000) -#define ETHER_RX_STAT_RXMCAST_OFST (17) -#define ETHER_RX_STAT_RXMCAST_MSK (0x10000) -#define ETHER_RX_STAT_RXBCAST_OFST (18) -#define ETHER_RX_STAT_RXBCAST_MSK (0x20000) -#define ETHER_RX_STAT_RXVLAN_OFST (19) -#define ETHER_RX_STAT_RXVLAN_MSK (0x40000) -#define ETHER_RX_STAT_RXPAUSE_OFST (20) -#define ETHER_RX_STAT_RXPAUSE_MSK (0x80000) -#define ETHER_RX_STAT_ARCSTATUS_OFST (21) -#define ETHER_RX_STAT_ARCSTATUS_MSK (0xF00000) -#define ETHER_RX_STAT_ARCENT_OFST (25) -#define ETHER_RX_STAT_ARCENT_MSK (0x1F000000) - -#define ETHER_MD_DATA(base) (ETHER00_TYPE (base + 0x18)) - -#define ETHER_MD_CA(base) (ETHER00_TYPE (base + 0x1c)) -#define ETHER_MD_CA_ADDR_OFST (0) -#define ETHER_MD_CA_ADDR_MSK (0x1F) -#define ETHER_MD_CA_PHY_OFST (5) -#define ETHER_MD_CA_PHY_MSK (0x3E0) -#define ETHER_MD_CA_WR_OFST (10) -#define ETHER_MD_CA_WR_MSK (0x400) -#define ETHER_MD_CA_BUSY_OFST (11) -#define ETHER_MD_CA_BUSY_MSK (0x800) -#define ETHER_MD_CA_PRESUPP_OFST (12) -#define ETHER_MD_CA_PRESUPP_MSK (0x1000) - -#define ETHER_ARC_ADR(base) (ETHER00_TYPE (base + 0x160)) -#define ETHER_ARC_ADR_ARC_LOC_OFST (2) -#define ETHER_ARC_ADR_ARC_LOC_MSK (0xFFC) - -#define ETHER_ARC_DATA(base) (ETHER00_TYPE (base + 0x364)) - -#define ETHER_ARC_ENA(base) (ETHER00_TYPE (base + 0x28)) -#define ETHER_ARC_ENA_MSK (0x1FFFFF) - -#define ETHER_PROM_CTL(base) (ETHER00_TYPE (base + 0x2c)) -#define ETHER_PROM_CTL_PROM_ADDR_OFST (0) -#define ETHER_PROM_CTL_PROM_ADDR_MSK (0x3F) -#define ETHER_PROM_CTL_OPCODE_OFST (13) -#define ETHER_PROM_CTL_OPCODE_MSK (0x6000) -#define ETHER_PROM_CTL_OPCODE_READ_MSK (0x4000) -#define ETHER_PROM_CTL_OPCODE_WRITE_MSK (0x2000) -#define ETHER_PROM_CTL_OPCODE_ERASE_MSK (0x6000) -#define ETHER_PROM_CTL_ENABLE_MSK (0x0030) -#define ETHER_PROM_CTL_DISABLE_MSK (0x0000) -#define ETHER_PROM_CTL_BUSY_OFST (15) -#define ETHER_PROM_CTL_BUSY_MSK (0x8000) - -#define ETHER_PROM_DATA(base) (ETHER00_TYPE (base + 0x30)) - -#define ETHER_MISS_CNT(base) (ETHER00_TYPE (base + 0x3c)) -#define ETHER_MISS_CNT_COUNT_OFST (0) -#define ETHER_MISS_CNT_COUNT_MSK (0xFFFF) - -#define ETHER_CNTDATA(base) (ETHER00_TYPE (base + 0x80)) - -#define ETHER_CNTACC(base) (ETHER00_TYPE (base + 0x84)) -#define ETHER_CNTACC_ADDR_OFST (0) -#define ETHER_CNTACC_ADDR_MSK (0xFF) -#define ETHER_CNTACC_WRRDN_OFST (8) -#define ETHER_CNTACC_WRRDN_MSK (0x100) -#define ETHER_CNTACC_CLEAR_OFST (9) -#define ETHER_CNTACC_CLEAR_MSK (0x200) - -#define ETHER_TXRMINTEN(base) (ETHER00_TYPE (base + 0x88)) -#define ETHER_TXRMINTEN_MSK (0x3FFFFFFF) - -#define ETHER_RXRMINTEN(base) (ETHER00_TYPE (base + 0x8C)) -#define ETHER_RXRMINTEN_MSK (0xFFFFFF) - -/* -* RMON Registers -*/ -#define RMON_COLLISION0 0x0 -#define RMON_COLLISION1 0x1 -#define RMON_COLLISION2 0x2 -#define RMON_COLLISION3 0x3 -#define RMON_COLLISION4 0x4 -#define RMON_COLLISION5 0x5 -#define RMON_COLLISION6 0x6 -#define RMON_COLLISION7 0x7 -#define RMON_COLLISION8 0x8 -#define RMON_COLLISION9 0x9 -#define RMON_COLLISION10 0xa -#define RMON_COLLISION11 0xb -#define RMON_COLLISION12 0xc -#define RMON_COLLISION13 0xd -#define RMON_COLLISION14 0xe -#define RMON_COLLISION15 0xf -#define RMON_COLLISION16 0x10 -#define RMON_FRAMES_WITH_DEFERRED_XMISSIONS 0x11 -#define RMON_LATE_COLLISIONS 0x12 -#define RMON_FRAMES_LOST_DUE_TO_MAC_XMIT 0x13 -#define RMON_CARRIER_SENSE_ERRORS 0x14 -#define RMON_FRAMES_WITH_EXCESSIVE_DEFERAL 0x15 -#define RMON_UNICAST_FRAMES_TRANSMITTED_OK 0x16 -#define RMON_MULTICAST_FRAMES_XMITTED_OK 0x17 -#define RMON_BROADCAST_FRAMES_XMITTED_OK 0x18 -#define RMON_SQE_TEST_ERRORS 0x19 -#define RMON_PAUSE_MACCTRL_FRAMES_XMITTED 0x1A -#define RMON_MACCTRL_FRAMES_XMITTED 0x1B -#define RMON_VLAN_FRAMES_XMITTED 0x1C -#define RMON_OCTETS_XMITTED_OK 0x1D -#define RMON_OCTETS_XMITTED_OK_HI 0x1E - -#define RMON_RX_PACKET_SIZES0 0x40 -#define RMON_RX_PACKET_SIZES1 0x41 -#define RMON_RX_PACKET_SIZES2 0x42 -#define RMON_RX_PACKET_SIZES3 0x43 -#define RMON_RX_PACKET_SIZES4 0x44 -#define RMON_RX_PACKET_SIZES5 0x45 -#define RMON_RX_PACKET_SIZES6 0x46 -#define RMON_RX_PACKET_SIZES7 0x47 -#define RMON_FRAME_CHECK_SEQUENCE_ERRORS 0x48 -#define RMON_ALIGNMENT_ERRORS 0x49 -#define RMON_FRAGMENTS 0x4A -#define RMON_JABBERS 0x4B -#define RMON_FRAMES_LOST_TO_INTMACRCVERR 0x4C -#define RMON_UNICAST_FRAMES_RCVD_OK 0x4D -#define RMON_MULTICAST_FRAMES_RCVD_OK 0x4E -#define RMON_BROADCAST_FRAMES_RCVD_OK 0x4F -#define RMON_IN_RANGE_LENGTH_ERRORS 0x50 -#define RMON_OUT_OF_RANGE_LENGTH_ERRORS 0x51 -#define RMON_VLAN_FRAMES_RCVD 0x52 -#define RMON_PAUSE_MAC_CTRL_FRAMES_RCVD 0x53 -#define RMON_MAC_CTRL_FRAMES_RCVD 0x54 -#define RMON_OCTETS_RCVD_OK 0x55 -#define RMON_OCTETS_RCVD_OK_HI 0x56 -#define RMON_OCTETS_RCVD_OTHER 0x57 -#define RMON_OCTETS_RCVD_OTHER_HI 0x58 - -#endif /* __ETHER00_H */ diff --git a/include/asm-arm/arch-epxa10db/excalibur.h b/include/asm-arm/arch-epxa10db/excalibur.h deleted file mode 100644 index 5c91dd6d782..00000000000 --- a/include/asm-arm/arch-epxa10db/excalibur.h +++ /dev/null @@ -1,91 +0,0 @@ -/* megafunction wizard: %ARM-Based Excalibur% - GENERATION: STANDARD - VERSION: WM1.0 - MODULE: ARM-Based Excalibur - PROJECT: excalibur - ============================================================ - File Name: v:\embedded\linux\bootldr\excalibur.h - Megafunction Name(s): ARM-Based Excalibur - ============================================================ - - ************************************************************ - THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! - ************************************************************/ - -#ifndef EXCALIBUR_H_INCLUDED -#define EXCALIBUR_H_INCLUDED - -#define EXC_DEFINE_PROCESSOR_LITTLE_ENDIAN -#define EXC_DEFINE_BOOT_FROM_FLASH - -#define EXC_INPUT_CLK_FREQUENCY (50000000) -#define EXC_AHB1_CLK_FREQUENCY (150000000) -#define EXC_AHB2_CLK_FREQUENCY (75000000) -#define EXC_SDRAM_CLK_FREQUENCY (75000000) - -/* Registers Block */ -#define EXC_REGISTERS_BASE (0x7fffc000) -#define EXC_MODE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x000) -#define EXC_IO_CTRL00_BASE (EXC_REGISTERS_BASE + 0x040) -#define EXC_MMAP00_BASE (EXC_REGISTERS_BASE + 0x080) -#define EXC_PLD_CONFIG00_BASE (EXC_REGISTERS_BASE + 0x140) -#define EXC_TIMER00_BASE (EXC_REGISTERS_BASE + 0x200) -#define EXC_INT_CTRL00_BASE (EXC_REGISTERS_BASE + 0xc00) -#define EXC_CLOCK_CTRL00_BASE (EXC_REGISTERS_BASE + 0x300) -#define EXC_WATCHDOG00_BASE (EXC_REGISTERS_BASE + 0xa00) -#define EXC_UART00_BASE (EXC_REGISTERS_BASE + 0x280) -#define EXC_EBI00_BASE (EXC_REGISTERS_BASE + 0x380) -#define EXC_SDRAM00_BASE (EXC_REGISTERS_BASE + 0x400) -#define EXC_AHB12_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x800) -#define EXC_PLD_STRIPE_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100) -#define EXC_STRIPE_PLD_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100) - -#define EXC_REGISTERS_SIZE (0x00004000) - -/* EBI Block(s) */ -#define EXC_EBI_BLOCK0_BASE (0x40000000) -#define EXC_EBI_BLOCK0_SIZE (0x00400000) -#define EXC_EBI_BLOCK0_WIDTH (8) -#define EXC_EBI_BLOCK0_NON_CACHEABLE -#define EXC_EBI_BLOCK1_BASE (0x40400000) -#define EXC_EBI_BLOCK1_SIZE (0x00400000) -#define EXC_EBI_BLOCK1_WIDTH (16) -#define EXC_EBI_BLOCK1_NON_CACHEABLE -#define EXC_EBI_BLOCK2_BASE (0x40800000) -#define EXC_EBI_BLOCK2_SIZE (0x00400000) -#define EXC_EBI_BLOCK2_WIDTH (16) -#define EXC_EBI_BLOCK2_NON_CACHEABLE -#define EXC_EBI_BLOCK3_BASE (0x40c00000) -#define EXC_EBI_BLOCK3_SIZE (0x00400000) -#define EXC_EBI_BLOCK3_WIDTH (16) -#define EXC_EBI_BLOCK3_NON_CACHEABLE - -/* SDRAM Block(s) */ -#define EXC_SDRAM_BLOCK0_BASE (0x00000000) -#define EXC_SDRAM_BLOCK0_SIZE (0x04000000) -#define EXC_SDRAM_BLOCK0_WIDTH (32) -#define EXC_SDRAM_BLOCK1_BASE (0x04000000) -#define EXC_SDRAM_BLOCK1_SIZE (0x04000000) -#define EXC_SDRAM_BLOCK1_WIDTH (32) - -/* Single Port SRAM Block(s) */ -#define EXC_SPSRAM_BLOCK0_BASE (0x08000000) -#define EXC_SPSRAM_BLOCK0_SIZE (0x00020000) -#define EXC_SPSRAM_BLOCK1_BASE (0x08020000) -#define EXC_SPSRAM_BLOCK1_SIZE (0x00020000) - -/* PLD Block(s) */ -#define EXC_PLD_BLOCK0_BASE (0x80000000) -#define EXC_PLD_BLOCK0_SIZE (0x00004000) -#define EXC_PLD_BLOCK0_NON_CACHEABLE -#define EXC_PLD_BLOCK1_BASE (0xf000000) -#define EXC_PLD_BLOCK1_SIZE (0x00004000) -#define EXC_PLD_BLOCK1_NON_CACHEABLE -#define EXC_PLD_BLOCK2_BASE (0x80008000) -#define EXC_PLD_BLOCK2_SIZE (0x00004000) -#define EXC_PLD_BLOCK2_NON_CACHEABLE -#define EXC_PLD_BLOCK3_BASE (0x8000c000) -#define EXC_PLD_BLOCK3_SIZE (0x00004000) -#define EXC_PLD_BLOCK3_NON_CACHEABLE - -#endif diff --git a/include/asm-arm/arch-epxa10db/hardware.h b/include/asm-arm/arch-epxa10db/hardware.h deleted file mode 100644 index b992c2924a7..00000000000 --- a/include/asm-arm/arch-epxa10db/hardware.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * linux/include/asm-arm/arch-epxa10/hardware.h - * - * This file contains the hardware definitions of the Integrator. - * - * Copyright (C) 1999 ARM Limited. - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <asm/arch/platform.h> - -/* - * Where in virtual memory the IO devices (timers, system controllers - * and so on) - */ -#define IO_BASE 0xf0000000 // VA of IO -#define IO_SIZE 0x10000000 // How much? -#define IO_START EXC_REGISTERS_BASE // PA of IO -/* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) ((x) | 0xf0000000) - -#define FLASH_VBASE 0xFE000000 -#define FLASH_SIZE 0x01000000 -#define FLASH_START EXC_EBI_BLOCK0_BASE -#define FLASH_VADDR(x) ((x)|0xFE000000) -/* - * Similar to above, but for PCI addresses (memory, IO, Config and the - * V3 chip itself). WARNING: this has to mirror definitions in platform.h - */ -#if 0 -#define PCI_MEMORY_VADDR 0xe8000000 -#define PCI_CONFIG_VADDR 0xec000000 -#define PCI_V3_VADDR 0xed000000 -#define PCI_IO_VADDR 0xee000000 - -#define PCIO_BASE PCI_IO_VADDR -#define PCIMEM_BASE PCI_MEMORY_VADDR - - -#define pcibios_assign_all_busses() 1 - -#define PCIBIOS_MIN_IO 0x6000 -#define PCIBIOS_MIN_MEM 0x00100000 -#endif - - -#endif - diff --git a/include/asm-arm/arch-epxa10db/int_ctrl00.h b/include/asm-arm/arch-epxa10db/int_ctrl00.h deleted file mode 100644 index 23ec864c40b..00000000000 --- a/include/asm-arm/arch-epxa10db/int_ctrl00.h +++ /dev/null @@ -1,288 +0,0 @@ -/* - * - * This file contains the register definitions for the Excalibur - * Timer TIMER00. - * - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __INT_CTRL00_H -#define __INT_CTRL00_H - -#define INT_MS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x00 )) -#define INT_MS_FC_MSK (0x10000) -#define INT_MS_FC_OFST (16) -#define INT_MS_M1_MSK (0x8000) -#define INT_MS_M1_OFST (15) -#define INT_MS_M0_MSK (0x4000) -#define INT_MS_M0_OFST (14) -#define INT_MS_AE_MSK (0x2000) -#define INT_MS_AE_OFST (13) -#define INT_MS_PE_MSK (0x1000) -#define INT_MS_PE_OFST (12) -#define INT_MS_EE_MSK (0x0800) -#define INT_MS_EE_OFST (11) -#define INT_MS_PS_MSK (0x0400) -#define INT_MS_PS_OFST (10) -#define INT_MS_T1_MSK (0x0200) -#define INT_MS_T1_OFST (9) -#define INT_MS_T0_MSK (0x0100) -#define INT_MS_T0_OFST (8) -#define INT_MS_UA_MSK (0x0080) -#define INT_MS_UA_OFST (7) -#define INT_MS_IP_MSK (0x0040) -#define INT_MS_IP_OFST (6) -#define INT_MS_P5_MSK (0x0020) -#define INT_MS_P5_OFST (5) -#define INT_MS_P4_MSK (0x0010) -#define INT_MS_P4_OFST (4) -#define INT_MS_P3_MSK (0x0008) -#define INT_MS_P3_OFST (3) -#define INT_MS_P2_MSK (0x0004) -#define INT_MS_P2_OFST (2) -#define INT_MS_P1_MSK (0x0002) -#define INT_MS_P1_OFST (1) -#define INT_MS_P0_MSK (0x0001) -#define INT_MS_P0_OFST (0) - -#define INT_MC(base_addr) (INT_CTRL00_TYPE (base_addr + 0x04 )) -#define INT_MC_FC_MSK (0x10000) -#define INT_MC_FC_OFST (16) -#define INT_MC_M1_MSK (0x8000) -#define INT_MC_M1_OFST (15) -#define INT_MC_M0_MSK (0x4000) -#define INT_MC_M0_OFST (14) -#define INT_MC_AE_MSK (0x2000) -#define INT_MC_AE_OFST (13) -#define INT_MC_PE_MSK (0x1000) -#define INT_MC_PE_OFST (12) -#define INT_MC_EE_MSK (0x0800) -#define INT_MC_EE_OFST (11) -#define INT_MC_PS_MSK (0x0400) -#define INT_MC_PS_OFST (10) -#define INT_MC_T1_MSK (0x0200) -#define INT_MC_T1_OFST (9) -#define INT_MC_T0_MSK (0x0100) -#define INT_MC_T0_OFST (8) -#define INT_MC_UA_MSK (0x0080) -#define INT_MC_UA_OFST (7) -#define INT_MC_IP_MSK (0x0040) -#define INT_MC_IP_OFST (6) -#define INT_MC_P5_MSK (0x0020) -#define INT_MC_P5_OFST (5) -#define INT_MC_P4_MSK (0x0010) -#define INT_MC_P4_OFST (4) -#define INT_MC_P3_MSK (0x0008) -#define INT_MC_P3_OFST (3) -#define INT_MC_P2_MSK (0x0004) -#define INT_MC_P2_OFST (2) -#define INT_MC_P1_MSK (0x0002) -#define INT_MC_P1_OFST (1) -#define INT_MC_P0_MSK (0x0001) -#define INT_MC_P0_OFST (0) - -#define INT_SS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x08 )) -#define INT_SS_FC_SSK (0x8000) -#define INT_SS_FC_OFST (15) -#define INT_SS_M1_SSK (0x8000) -#define INT_SS_M1_OFST (15) -#define INT_SS_M0_SSK (0x4000) -#define INT_SS_M0_OFST (14) -#define INT_SS_AE_SSK (0x2000) -#define INT_SS_AE_OFST (13) -#define INT_SS_PE_SSK (0x1000) -#define INT_SS_PE_OFST (12) -#define INT_SS_EE_SSK (0x0800) -#define INT_SS_EE_OFST (11) -#define INT_SS_PS_SSK (0x0400) -#define INT_SS_PS_OFST (10) -#define INT_SS_T1_SSK (0x0200) -#define INT_SS_T1_OFST (9) -#define INT_SS_T0_SSK (0x0100) -#define INT_SS_T0_OFST (8) -#define INT_SS_UA_SSK (0x0080) -#define INT_SS_UA_OFST (7) -#define INT_SS_IP_SSK (0x0040) -#define INT_SS_IP_OFST (6) -#define INT_SS_P5_SSK (0x0020) -#define INT_SS_P5_OFST (5) -#define INT_SS_P4_SSK (0x0010) -#define INT_SS_P4_OFST (4) -#define INT_SS_P3_SSK (0x0008) -#define INT_SS_P3_OFST (3) -#define INT_SS_P2_SSK (0x0004) -#define INT_SS_P2_OFST (2) -#define INT_SS_P1_SSK (0x0002) -#define INT_SS_P1_OFST (1) -#define INT_SS_P0_SSK (0x0001) -#define INT_SS_P0_OFST (0) - -#define INT_RS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x0C )) -#define INT_RS_FC_RSK (0x10000) -#define INT_RS_FC_OFST (16) -#define INT_RS_M1_RSK (0x8000) -#define INT_RS_M1_OFST (15) -#define INT_RS_M0_RSK (0x4000) -#define INT_RS_M0_OFST (14) -#define INT_RS_AE_RSK (0x2000) -#define INT_RS_AE_OFST (13) -#define INT_RS_PE_RSK (0x1000) -#define INT_RS_PE_OFST (12) -#define INT_RS_EE_RSK (0x0800) -#define INT_RS_EE_OFST (11) -#define INT_RS_PS_RSK (0x0400) -#define INT_RS_PS_OFST (10) -#define INT_RS_T1_RSK (0x0200) -#define INT_RS_T1_OFST (9) -#define INT_RS_T0_RSK (0x0100) -#define INT_RS_T0_OFST (8) -#define INT_RS_UA_RSK (0x0080) -#define INT_RS_UA_OFST (7) -#define INT_RS_IP_RSK (0x0040) -#define INT_RS_IP_OFST (6) -#define INT_RS_P5_RSK (0x0020) -#define INT_RS_P5_OFST (5) -#define INT_RS_P4_RSK (0x0010) -#define INT_RS_P4_OFST (4) -#define INT_RS_P3_RSK (0x0008) -#define INT_RS_P3_OFST (3) -#define INT_RS_P2_RSK (0x0004) -#define INT_RS_P2_OFST (2) -#define INT_RS_P1_RSK (0x0002) -#define INT_RS_P1_OFST (1) -#define INT_RS_P0_RSK (0x0001) -#define INT_RS_P0_OFST (0) - -#define INT_ID(base_addr) (INT_CTRL00_TYPE (base_addr + 0x10 )) -#define INT_ID_ID_MSK (0x3F) -#define INT_ID_ID_OFST (0) - -#define INT_PLD_PRIORITY(base_addr) (INT_CTRL00_TYPE (base_addr + 0x14 )) -#define INT_PLD_PRIORITY_PRI_MSK (0x3F) -#define INT_PLD_PRIORITY_PRI_OFST (0) -#define INT_PLD_PRIORITY_GA_MSK (0x40) -#define INT_PLD_PRIORITY_GA_OFST (6) - -#define INT_MODE(base_addr) (INT_CTRL00_TYPE (base_addr + 0x18 )) -#define INT_MODE_MODE_MSK (0x3) -#define INT_MODE_MODE_OFST (0) - -#define INT_PRIORITY_P0(base_addr) (INT_CTRL00_TYPE (base_addr + 0x80 )) -#define INT_PRIORITY_P0_PRI_MSK (0x3F) -#define INT_PRIORITY_P0_PRI_OFST (0) -#define INT_PRIORITY_P0_FQ_MSK (0x40) -#define INT_PRIORITY_P0_FQ_OFST (6) - -#define INT_PRIORITY_P1(base_addr) (INT_CTRL00_TYPE (base_addr + 0x84 )) -#define INT_PRIORITY_P1_PRI_MSK (0x3F) -#define INT_PRIORITY_P1_PRI_OFST (0) -#define INT_PRIORITY_P1_FQ_MSK (0x40) -#define INT_PRIORITY_P1_FQ_OFST (6) - -#define INT_PRIORITY_P2(base_addr) (INT_CTRL00_TYPE (base_addr + 0x88 )) -#define INT_PRIORITY_P2_PRI_MSK (0x3F) -#define INT_PRIORITY_P2_PRI_OFST (0) -#define INT_PRIORITY_P2_FQ_MSK (0x40) -#define INT_PRIORITY_P2_FQ_OFST (6) - -#define INT_PRIORITY_P3(base_addr) (INT_CTRL00_TYPE (base_addr + 0x8C )) -#define INT_PRIORITY_P3_PRI_MSK (0x3F) -#define INT_PRIORITY_P3_PRI_OFST (0) -#define INT_PRIORITY_P3_FQ_MSK (0x40) -#define INT_PRIORITY_P3_FQ_OFST (6) - -#define INT_PRIORITY_P4(base_addr) (INT_CTRL00_TYPE (base_addr + 0x90 )) -#define INT_PRIORITY_P4_PRI_MSK (0x3F) -#define INT_PRIORITY_P4_PRI_OFST (0) -#define INT_PRIORITY_P4_FQ_MSK (0x40) -#define INT_PRIORITY_P4_FQ_OFST (6) - -#define INT_PRIORITY_P5(base_addr) (INT_CTRL00_TYPE (base_addr + 0x94 )) -#define INT_PRIORITY_P5_PRI_MSK (0x3F) -#define INT_PRIORITY_P5_PRI_OFST (0) -#define INT_PRIORITY_P5_FQ_MSK (0x40) -#define INT_PRIORITY_P5_FQ_OFST (6) - -#define INT_PRIORITY_IP(base_addr) (INT_CTRL00_TYPE (base_addr + 0x94 )) -#define INT_PRIORITY_IP_PRI_MSK (0x3F) -#define INT_PRIORITY_IP_PRI_OFST (0) -#define INT_PRIORITY_IP_FQ_MSK (0x40) -#define INT_PRIORITY_IP_FQ_OFST (6) - -#define INT_PRIORITY_UA(base_addr) (INT_CTRL00_TYPE (base_addr + 0x9C )) -#define INT_PRIORITY_UA_PRI_MSK (0x3F) -#define INT_PRIORITY_UA_PRI_OFST (0) -#define INT_PRIORITY_UA_FQ_MSK (0x40) -#define INT_PRIORITY_UA_FQ_OFST (6) - -#define INT_PRIORITY_T0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA0 )) -#define INT_PRIORITY_T0_PRI_MSK (0x3F) -#define INT_PRIORITY_T0_PRI_OFST (0) -#define INT_PRIORITY_T0_FQ_MSK (0x40) -#define INT_PRIORITY_T0_FQ_OFST (6) - -#define INT_PRIORITY_T1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA4 )) -#define INT_PRIORITY_T1_PRI_MSK (0x3F) -#define INT_PRIORITY_T1_PRI_OFST (0) -#define INT_PRIORITY_T1_FQ_MSK (0x40) -#define INT_PRIORITY_T1_FQ_OFST (6) - -#define INT_PRIORITY_PS(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA8 )) -#define INT_PRIORITY_PS_PRI_MSK (0x3F) -#define INT_PRIORITY_PS_PRI_OFST (0) -#define INT_PRIORITY_PS_FQ_MSK (0x40) -#define INT_PRIORITY_PS_FQ_OFST (6) - -#define INT_PRIORITY_EE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xAC )) -#define INT_PRIORITY_EE_PRI_MSK (0x3F) -#define INT_PRIORITY_EE_PRI_OFST (0) -#define INT_PRIORITY_EE_FQ_MSK (0x40) -#define INT_PRIORITY_EE_FQ_OFST (6) - -#define INT_PRIORITY_PE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB0 )) -#define INT_PRIORITY_PE_PRI_MSK (0x3F) -#define INT_PRIORITY_PE_PRI_OFST (0) -#define INT_PRIORITY_PE_FQ_MSK (0x40) -#define INT_PRIORITY_PE_FQ_OFST (6) - -#define INT_PRIORITY_AE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB4 )) -#define INT_PRIORITY_AE_PRI_MSK (0x3F) -#define INT_PRIORITY_AE_PRI_OFST (0) -#define INT_PRIORITY_AE_FQ_MSK (0x40) -#define INT_PRIORITY_AE_FQ_OFST (6) - -#define INT_PRIORITY_M0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB8 )) -#define INT_PRIORITY_M0_PRI_MSK (0x3F) -#define INT_PRIORITY_M0_PRI_OFST (0) -#define INT_PRIORITY_M0_FQ_MSK (0x40) -#define INT_PRIORITY_M0_FQ_OFST (6) - -#define INT_PRIORITY_M1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xBC )) -#define INT_PRIORITY_M1_PRI_MSK (0x3F) -#define INT_PRIORITY_M1_PRI_OFST (0) -#define INT_PRIORITY_M1_FQ_MSK (0x40) -#define INT_PRIORITY_M1_FQ_OFST (6) - -#define INT_PRIORITY_FC(base_addr) (INT_CTRL00_TYPE (base_addr + 0xC0 )) -#define INT_PRIORITY_FC_PRI_MSK (0x3F) -#define INT_PRIORITY_FC_PRI_OFST (0) -#define INT_PRIORITY_FC_FQ_MSK (0x40) -#define INT_PRIORITY_FC_FQ_OFST (6) - -#endif /* __INT_CTRL00_H */ - - diff --git a/include/asm-arm/arch-epxa10db/io.h b/include/asm-arm/arch-epxa10db/io.h deleted file mode 100644 index 9fe100c9d6b..00000000000 --- a/include/asm-arm/arch-epxa10db/io.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * linux/include/asm-arm/arch-epxa10db/io.h - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#include <asm/hardware.h> - -#define IO_SPACE_LIMIT 0xffff - - -/* - * Generic virtual read/write - */ -/*#define outsw __arch_writesw -#define outsl __arch_writesl -#define outsb __arch_writesb -#define insb __arch_readsb -#define insw __arch_readsw -#define insl __arch_readsl*/ - -#define __io(a) ((void __iomem *)(a)) -#define __mem_pci(a) (a) - -#endif diff --git a/include/asm-arm/arch-epxa10db/irqs.h b/include/asm-arm/arch-epxa10db/irqs.h deleted file mode 100644 index c3758a3b5d9..00000000000 --- a/include/asm-arm/arch-epxa10db/irqs.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * linux/include/asm-arm/arch-camelot/irqs.h - * - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -/* Use the Excalibur chip definitions */ -#define INT_CTRL00_TYPE -#include "asm/arch/int_ctrl00.h" - - -#define IRQ_PLD0 INT_MS_P0_OFST -#define IRQ_PLD1 INT_MS_P1_OFST -#define IRQ_PLD2 INT_MS_P2_OFST -#define IRQ_PLD3 INT_MS_P3_OFST -#define IRQ_PLD4 INT_MS_P4_OFST -#define IRQ_PLD5 INT_MS_P5_OFST -#define IRQ_EXT INT_MS_IP_OFST -#define IRQ_UART INT_MS_UA_OFST -#define IRQ_TIMER0 INT_MS_T0_OFST -#define IRQ_TIMER1 INT_MS_T1_OFST -#define IRQ_PLL INT_MS_PLL_OFST -#define IRQ_EBI INT_MS_EBI_OFST -#define IRQ_STRIPE_BRIDGE INT_MS_PLL_OFST -#define IRQ_AHB_BRIDGE INT_MS_PLL_OFST -#define IRQ_COMMRX INT_MS_CR_OFST -#define IRQ_COMMTX INT_MS_CT_OFST -#define IRQ_FAST_COMM INT_MS_FC_OFST - -#define NR_IRQS (INT_MS_FC_OFST + 1) - diff --git a/include/asm-arm/arch-epxa10db/memory.h b/include/asm-arm/arch-epxa10db/memory.h deleted file mode 100644 index 999541b6a9f..00000000000 --- a/include/asm-arm/arch-epxa10db/memory.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * linux/include/asm-arm/arch-epxa10/memory.h - * - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* - * Physical DRAM offset. - */ -#define PHYS_OFFSET UL(0x00000000) - -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - */ -#define __virt_to_bus(x) (x - PAGE_OFFSET + /*SDRAM_BASE*/0) -#define __bus_to_virt(x) (x - /*SDRAM_BASE*/0 + PAGE_OFFSET) - -#endif diff --git a/include/asm-arm/arch-epxa10db/mode_ctrl00.h b/include/asm-arm/arch-epxa10db/mode_ctrl00.h deleted file mode 100644 index d8a7efa12e1..00000000000 --- a/include/asm-arm/arch-epxa10db/mode_ctrl00.h +++ /dev/null @@ -1,80 +0,0 @@ -#ifndef __MODE_CTRL00_H -#define __MODE_CTRL00_H - -/* - * Register definitions for the reset and mode control - */ - -/* - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - - - -#define BOOT_CR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR )) -#define BOOT_CR_BF_MSK (0x1) -#define BOOT_CR_BF_OFST (0) -#define BOOT_CR_HM_MSK (0x2) -#define BOOT_CR_HM_OFST (1) -#define BOOT_CR_RE_MSK (0x4) -#define BOOT_CR_RE_OFST (2) - -#define RESET_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x4 )) -#define RESET_SR_WR_MSK (0x1) -#define RESET_SR_WR_OFST (0) -#define RESET_SR_CR_MSK (0x2) -#define RESET_SR_CR_OFST (1) -#define RESET_SR_JT_MSK (0x4) -#define RESET_SR_JT_OFST (2) -#define RESET_SR_ER_MSK (0x8) -#define RESET_SR_ER_OFST (3) - -#define ID_CODE(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x08 )) - -#define SRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x20 )) -#define SRAM0_SR_SIZE_MSK (0xFFFFF000) -#define SRAM0_SR_SIZE_OFST (12) - -#define SRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x24 )) -#define SRAM1_SR_SIZE_MSK (0xFFFFF000) -#define SRAM1_SR_SIZE_OFST (12) - -#define DPSRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x30 )) - -#define DPSRAM0_SR_MODE_MSK (0xF) -#define DPSRAM0_SR_MODE_OFST (0) -#define DPSRAM0_SR_GLBL_MSK (0x30) -#define DPSRAM0_SR_SIZE_MSK (0xFFFFF000) -#define DPSRAM0_SR_SIZE_OFST (12) - -#define DPSRAM0_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x34 )) -#define DPSRAM0_LCR_LCKADDR_MSK (0x1FFE0) -#define DPSRAM0_LCR_LCKADDR_OFST (4) - -#define DPSRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x38 )) -#define DPSRAM1_SR_MODE_MSK (0xF) -#define DPSRAM1_SR_MODE_OFST (0) -#define DPSRAM1_SR_GLBL_MSK (0x30) -#define DPSRAM1_SR_GLBL_OFST (4) -#define DPSRAM1_SR_SIZE_MSK (0xFFFFF000) -#define DPSRAM1_SR_SIZE_OFST (12) - -#define DPSRAM1_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x3C )) -#define DPSRAM1_LCR_LCKADDR_MSK (0x1FFE0) -#define DPSRAM1_LCR_LCKADDR_OFST (4) - -#endif /* __MODE_CTRL00_H */ diff --git a/include/asm-arm/arch-epxa10db/param.h b/include/asm-arm/arch-epxa10db/param.h deleted file mode 100644 index 783dedd71c8..00000000000 --- a/include/asm-arm/arch-epxa10db/param.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * linux/include/asm-arm/arch-epxa10db/param.h - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ diff --git a/include/asm-arm/arch-epxa10db/platform.h b/include/asm-arm/arch-epxa10db/platform.h deleted file mode 100644 index 129bb0f212a..00000000000 --- a/include/asm-arm/arch-epxa10db/platform.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef PLATFORM_H -#define PLATFORM_H -#include "excalibur.h" - -#define MAXIRQNUM 15 -#endif - diff --git a/include/asm-arm/arch-epxa10db/pld_conf00.h b/include/asm-arm/arch-epxa10db/pld_conf00.h deleted file mode 100644 index 7af2c38dacc..00000000000 --- a/include/asm-arm/arch-epxa10db/pld_conf00.h +++ /dev/null @@ -1,73 +0,0 @@ -#ifndef __PLD_CONF00_H -#define __PLD_CONF00_H - -/* - * Register definitions for the PLD Configuration Logic - */ - -/* - * - * This file contains the register definitions for the Excalibur - * Interrupt controller INT_CTRL00. - * - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#define CONFIG_CONTROL(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR)) -#define CONFIG_CONTROL_LK_MSK (0x1) -#define CONFIG_CONTROL_LK_OFST (0) -#define CONFIG_CONTROL_CO_MSK (0x2) -#define CONFIG_CONTROL_CO_OFST (1) -#define CONFIG_CONTROL_B_MSK (0x4) -#define CONFIG_CONTROL_B_OFST (2) -#define CONFIG_CONTROL_PC_MSK (0x8) -#define CONFIG_CONTROL_PC_OFST (3) -#define CONFIG_CONTROL_E_MSK (0x10) -#define CONFIG_CONTROL_E_OFST (4) -#define CONFIG_CONTROL_ES_MSK (0xE0) -#define CONFIG_CONTROL_ES_OFST (5) -#define CONFIG_CONTROL_ES_0_MSK (0x20) -#define CONFIG_CONTROL_ES_1_MSK (0x40) -#define CONFIG_CONTROL_ES_2_MSK (0x80) - -#define CONFIG_CONTROL_CLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0x4 )) -#define CONFIG_CONTROL_CLOCK_RATIO_MSK (0xFFFF) -#define CONFIG_CONTROL_CLOCK_RATIO_OFST (0) - -#define CONFIG_CONTROL_DATA(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0x8 )) -#define CONFIG_CONTROL_DATA_MSK (0xFFFFFFFF) -#define CONFIG_CONTROL_DATA_OFST (0) - -#define CONFIG_UNLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0xC )) -#define CONFIG_UNLOCK_MSK (0xFFFFFFFF) -#define CONFIG_UNLOCK_OFST (0) - -#define CONFIG_UNLOCK_MAGIC (0x554E4C4B) - -#endif /* __PLD_CONF00_H */ - - - - - - - - - - - - diff --git a/include/asm-arm/arch-epxa10db/system.h b/include/asm-arm/arch-epxa10db/system.h deleted file mode 100644 index 345b092a1ed..00000000000 --- a/include/asm-arm/arch-epxa10db/system.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * linux/include/asm-arm/arch-epxa10db/system.h - * - * Copyright (C) 1999 ARM Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -#include <asm/arch/platform.h> - -static inline void arch_idle(void) -{ - /* - * This should do all the clock switching - * and wait for interrupt tricks - */ - cpu_do_idle(); -} - -extern __inline__ void arch_reset(char mode) -{ - /* Hmm... We can probably do something with the watchdog... */ -} - -#endif diff --git a/include/asm-arm/arch-epxa10db/tdkphy.h b/include/asm-arm/arch-epxa10db/tdkphy.h deleted file mode 100644 index 5e107bd4e10..00000000000 --- a/include/asm-arm/arch-epxa10db/tdkphy.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * linux/drivers/tdkphy.h - * - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __TDKPHY_H -#define __TDKPHY_H - -/* - * Register definitions for the TDK 78Q2120 PHY - * which is on the Camelot board - */ - -/* - * Copyright (c) Altera Corporation 2000. - * All rights reserved. - */ -#define PHY_CONTROL (0) -#define PHY_CONTROL_COLT_MSK (0x80) -#define PHY_CONTROL_COLT_OFST (7) -#define PHY_CONTROL_DUPLEX_MSK (0x100) -#define PHY_CONTROL_DUPLEX_OFST (8) -#define PHY_CONTROL_RANEG_MSK (0x200) -#define PHY_CONTROL_RANEG_OFST (9) -#define PHY_CONTROL_ISO_MSK (0x400) -#define PHY_CONTROL_ISO_OFST (10) -#define PHY_CONTROL_PWRDN_MSK (0x800) -#define PHY_CONTROL_PWRDN_OFST (11) -#define PHY_CONTROL_ANEGEN_MSK (0x1000) -#define PHY_CONTROL_ANEGEN_OFST (12) -#define PHY_CONTROL_SPEEDSL_MSK (0x2000) -#define PHY_CONTROL_SPEEDSL_OFST (13) -#define PHY_CONTROL_LOOPBK_MSK (0x4000) -#define PHY_CONTROL_LOOPBK_OFST (14) -#define PHY_CONTROL_RESET_MSK (0x8000) -#define PHY_CONTROL_RESET_OFST (15) - -#define PHY_STATUS (1) -#define PHY_STATUS_ETXD_MSK (0x1) -#define PHY_STATUS_EXTD_OFST (0) -#define PHY_STATUS_JAB_MSK (0x2) -#define PHY_STATUS_JAB_OFST (1) -#define PHY_STATUS_LINK_MSK (0x4) -#define PHY_STATUS_LINK_OFST (2) -#define PHY_STATUS_ANEGA_MSK (0x8) -#define PHY_STATUS_ANEGA_OFST (3) -#define PHY_STATUS_RFAULT_MSK (0x10) -#define PHY_STATUS_RFAULT_OFST (4) -#define PHY_STATUS_ANEGC_MSK (0x20) -#define PHY_STATUS_ANEGC_OFST (5) -#define PHY_STATUS_10T_H_MSK (0x800) -#define PHY_STATUS_10T_H_OFST (11) -#define PHY_STATUS_10T_F_MSK (0x1000) -#define PHY_STATUS_10T_F_OFST (12) -#define PHY_STATUS_100_X_H_MSK (0x2000) -#define PHY_STATUS_100_X_H_OFST (13) -#define PHY_STATUS_100_X_F_MSK (0x4000) -#define PHY_STATUS_100_X_F_OFST (14) -#define PHY_STATUS_100T4_MSK (0x8000) -#define PHY_STATUS_100T4_OFST (15) - -#define PHY_ID1 (2) -#define PHY_ID1_OUI_MSK (0xFFFF) -#define PHY_ID1_OUI_OFST (0) - -#define PHY_ID2 (3) -#define PHY_ID2_RN_MSK (0xF) -#define PHY_ID2_RN_OFST (0) -#define PHY_ID2_MN_MSK (0x3F0) -#define PHY_ID2_MN_OFST (4) -#define PHY_ID2_OUI_MSK (0xFC00) -#define PHY_ID2_OUI_OFST (10) - -#define PHY_AUTO_NEG_ADVERTISEMENT (4) -#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_MSK (0x1F) -#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_OFST (0) -#define PHY_AUTO_NEG_ADVERTISEMENT_A0_MSK (0x20) -#define PHY_AUTO_NEG_ADVERTISEMENT_A0_OFST (5) -#define PHY_AUTO_NEG_ADVERTISEMENT_A1_MSK (0x40) -#define PHY_AUTO_NEG_ADVERTISEMENT_A1_OFST (6) -#define PHY_AUTO_NEG_ADVERTISEMENT_A2_MSK (0x80) -#define PHY_AUTO_NEG_ADVERTISEMENT_A2_OFST (7) -#define PHY_AUTO_NEG_ADVERTISEMENT_A3_MSK (0x100) -#define PHY_AUTO_NEG_ADVERTISEMENT_A3_OFST (8) -#define PHY_AUTO_NEG_ADVERTISEMENT_A4_MSK (0x200) -#define PHY_AUTO_NEG_ADVERTISEMENT_A4_OFST (9) -#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_MSK (0x1FE0) -#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_OFST (5) -#define PHY_AUTO_NEG_ADVERTISEMENT_RF_MSK (0x2000) -#define PHY_AUTO_NEG_ADVERTISEMENT_RF_OFST (13) -#define PHY_AUTO_NEG_ADVERTISEMENT_RSVD_MSK (0x4000) -#define PHY_AUTO_NEG_ADVERTISEMENT_RVSD_OFST (14) -#define PHY_AUTO_NEG_ADVERTISEMENT_NP_MSK (0x8000) -#define PHY_AUTO_NEG_ADVERTISEMENT_NP_OFST (15) - -#define PHY_AUTO_NEG_LINK_PARTNER (5) -#define PHY_AUTO_NEG_LINK_PARTNER_S4_MSK (0x1F) -#define PHY_AUTO_NEG_LINK_PARTNER_S4_OFST (0) -#define PHY_AUTO_NEG_LINK_PARTNER_A7_MSK (0x1FE0) -#define PHY_AUTO_NEG_LINK_PARTNER_A7_OFST (5) -#define PHY_AUTO_NEG_LINK_PARTNER_RF_MSK (0x2000) -#define PHY_AUTO_NEG_LINK_PARTNER_RF_OFST (13) -#define PHY_AUTO_NEG_LINK_PARTNER_ACK_MSK (0x4000) -#define PHY_AUTO_NEG_LINK_PARTNER_ACK_OFST (14) -#define PHY_AUTO_NEG_LINK_PARTNER_NP_MSK (0x8000) -#define PHY_AUTO_NEG_LINK_PARTNER_NP_OFST (15) - -#define PHY_AUTO_NEG_EXPANSION (6) -#define PHY_AUTO_NEG_EXPANSION_LPANEGA_MSK (0x1) -#define PHY_AUTO_NEG_EXPANSION_LPANEGA_OFST (0) -#define PHY_AUTO_NEG_EXPANSION_PRX_MSK (0x2) -#define PHY_AUTO_NEG_EXPANSION_PRX_OFST (1) -#define PHY_AUTO_NEG_EXPANSION_NPA_MSK (0x4) -#define PHY_AUTO_NEG_EXPANSION_NPA_OFST (2) -#define PHY_AUTO_NEG_EXPANSION_LPNPA_MSK (0x8) -#define PHY_AUTO_NEG_EXPANSION_LPNPA_OFST (3) -#define PHY_AUTO_NEG_EXPANSION_PDF_MSK (0x10) -#define PHY_AUTO_NEG_EXPANSION_PDF_OFST (4) - -#define PHY_VENDOR_SPECIFIC (16) -#define PHY_VENDOR_SPECIFIC_RXCC_MSK (0x1) -#define PHY_VENDOR_SPECIFIC_RXCC_OFST (0) -#define PHY_VENDOR_SPECIFIC_PCSBP_MSK (0x2) -#define PHY_VENDOR_SPECIFIC_PCSBP_OFST (1) -#define PHY_VENDOR_SPECIFIC_RVSPOL_MSK (0x10) -#define PHY_VENDOR_SPECIFIC_RVSPOL_OFST (4) -#define PHY_VENDOR_SPECIFIC_APOL_MSK (0x20) -#define PHY_VENDOR_SPECIFIC_APOL_OFST (5) -#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_MSK (0x40) -#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_OFST (6) -#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_MSK (0x80) -#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_OFST (7) -#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_MSK (0x100) -#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_OFST (8) -#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_MSK (0x200) -#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_OFST (9) -#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_MSK (0x400) -#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_OFST (10) -#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_MSK (0x800) -#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_OFST (11) -#define PHY_VENDOR_SPECIFIC_TXHIM_MSK (0x1000) -#define PHY_VENDOR_SPECIFIC_TXHIM_OFST (12) -#define PHY_VENDOR_SPECIFIC_INT_LEVEL_MSK (0x4000) -#define PHY_VENDOR_SPECIFIC_INT_LEVEL_OFST (14) -#define PHY_VENDOR_SPECIFIC_RPTR_MSK (0x8000) -#define PHY_VENDOR_SPECIFIC_RPTR_OFST (15) - -#define PHY_IRQ_CONTROL (17) -#define PHY_IRQ_CONTROL_ANEG_COMP_INT_MSK (0x1) -#define PHY_IRQ_CONTROL_ANEG_COMP_INT_OFST (0) -#define PHY_IRQ_CONTROL_RFAULT_INT_MSK (0x2) -#define PHY_IRQ_CONTROL_RFAULT_INT_OFST (1) -#define PHY_IRQ_CONTROL_LS_CHG_INT_MSK (0x4) -#define PHY_IRQ_CONTROL_LS_CHG_INT_OFST (2) -#define PHY_IRQ_CONTROL_LP_ACK_INT_MSK (0x8) -#define PHY_IRQ_CONTROL_LP_ACK_INT_OFST (3) -#define PHY_IRQ_CONTROL_PDF_INT_MSK (0x10) -#define PHY_IRQ_CONTROL_PDF_INT_OFST (4) -#define PHY_IRQ_CONTROL_PRX_INT_MSK (0x20) -#define PHY_IRQ_CONTROL_PRX_INT_OFST (5) -#define PHY_IRQ_CONTROL_RXER_INT_MSK (0x40) -#define PHY_IRQ_CONTROL_RXER_INT_OFST (6) -#define PHY_IRQ_CONTROL_JABBER_INT_MSK (0x80) -#define PHY_IRQ_CONTROL_JABBER_INT_OFST (7) -#define PHY_IRQ_CONTROL_ANEG_COMP_IE_MSK (0x100) -#define PHY_IRQ_CONTROL_ANEG_COMP_IE_OFST (8) -#define PHY_IRQ_CONTROL_RFAULT_IE_MSK (0x200) -#define PHY_IRQ_CONTROL_RFAULT_IE_OFST (9) -#define PHY_IRQ_CONTROL_LS_CHG_IE_MSK (0x400) -#define PHY_IRQ_CONTROL_LS_CHG_IE_OFST (10) -#define PHY_IRQ_CONTROL_LP_ACK_IE_MSK (0x800) -#define PHY_IRQ_CONTROL_LP_ACK_IE_OFST (11) -#define PHY_IRQ_CONTROL_PDF_IE_MSK (0x1000) -#define PHY_IRQ_CONTROL_PDF_IE_OFST (12) -#define PHY_IRQ_CONTROL_PRX_IE_MSK (0x2000) -#define PHY_IRQ_CONTROL_PRX_IE_OFST (13) -#define PHY_IRQ_CONTROL_RXER_IE_MSK (0x4000) -#define PHY_IRQ_CONTROL_RXER_IE_OFST (14) -#define PHY_IRQ_CONTROL_JABBER_IE_MSK (0x8000) -#define PHY_IRQ_CONTROL_JABBER_IE_OFST (15) - -#define PHY_DIAGNOSTIC (18) -#define PHY_DIAGNOSTIC_RX_LOCK_MSK (0x100) -#define PHY_DIAGNOSTIC_RX_LOCK_OFST (8) -#define PHY_DIAGNOSTIC_RX_PASS_MSK (0x200) -#define PHY_DIAGNOSTIC_RX_PASS_OFST (9) -#define PHY_DIAGNOSTIC_RATE_MSK (0x400) -#define PHY_DIAGNOSTIC_RATE_OFST (10) -#define PHY_DIAGNOSTIC_DPLX_MSK (0x800) -#define PHY_DIAGNOSTIC_DPLX_OFST (11) -#define PHY_DIAGNOSTIC_ANEGF_MSK (0x1000) -#define PHY_DIAGNOSTIC_ANEGF_OFST (12) - -#endif /* __TDKPHY_H */ diff --git a/include/asm-arm/arch-epxa10db/timer00.h b/include/asm-arm/arch-epxa10db/timer00.h deleted file mode 100644 index 52a3fb58b59..00000000000 --- a/include/asm-arm/arch-epxa10db/timer00.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * - * This file contains the register definitions for the Excalibur - * Timer TIMER00. - * - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __TIMER00_H -#define __TIMER00_H - -/* - * Register definitions for the timers - */ - - -#define TIMER0_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x00 )) -#define TIMER0_CR_B_MSK (0x20) -#define TIMER0_CR_B_OFST (0x5) -#define TIMER0_CR_S_MSK (0x10) -#define TIMER0_CR_S_OFST (0x4) -#define TIMER0_CR_CI_MSK (0x08) -#define TIMER0_CR_CI_OFST (0x3) -#define TIMER0_CR_IE_MSK (0x04) -#define TIMER0_CR_IE_OFST (0x2) -#define TIMER0_CR_MODE_MSK (0x3) -#define TIMER0_CR_MODE_OFST (0) -#define TIMER0_CR_MODE_FREE (0) -#define TIMER0_CR_MODE_ONE (1) -#define TIMER0_CR_MODE_INTVL (2) - -#define TIMER0_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x00 )) -#define TIMER0_SR_B_MSK (0x20) -#define TIMER0_SR_B_OFST (0x5) -#define TIMER0_SR_S_MSK (0x10) -#define TIMER0_SR_S_OFST (0x4) -#define TIMER0_SR_CI_MSK (0x08) -#define TIMER0_SR_CI_OFST (0x3) -#define TIMER0_SR_IE_MSK (0x04) -#define TIMER0_SR_IE_OFST (0x2) -#define TIMER0_SR_MODE_MSK (0x3) -#define TIMER0_SR_MODE_OFST (0) -#define TIMER0_SR_MODE_FREE (0) -#define TIMER0_SR_MODE_ONE (1) -#define TIMER0_SR_MODE_INTVL (2) - -#define TIMER0_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x010 )) -#define TIMER0_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x020 )) -#define TIMER0_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x030 )) - -#define TIMER1_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x40 )) -#define TIMER1_CR_B_MSK (0x20) -#define TIMER1_CR_B_OFST (0x5) -#define TIMER1_CR_S_MSK (0x10) -#define TIMER1_CR_S_OFST (0x4) -#define TIMER1_CR_CI_MSK (0x08) -#define TIMER1_CR_CI_OFST (0x3) -#define TIMER1_CR_IE_MSK (0x04) -#define TIMER1_CR_IE_OFST (0x2) -#define TIMER1_CR_MODE_MSK (0x3) -#define TIMER1_CR_MODE_OFST (0) -#define TIMER1_CR_MODE_FREE (0) -#define TIMER1_CR_MODE_ONE (1) -#define TIMER1_CR_MODE_INTVL (2) - -#define TIMER1_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x40 )) -#define TIMER1_SR_B_MSK (0x20) -#define TIMER1_SR_B_OFST (0x5) -#define TIMER1_SR_S_MSK (0x10) -#define TIMER1_SR_S_OFST (0x4) -#define TIMER1_SR_CI_MSK (0x08) -#define TIMER1_SR_CI_OFST (0x3) -#define TIMER1_SR_IE_MSK (0x04) -#define TIMER1_SR_IE_OFST (0x2) -#define TIMER1_SR_MODE_MSK (0x3) -#define TIMER1_SR_MODE_OFST (0) -#define TIMER1_SR_MODE_FREE (0) -#define TIMER1_SR_MODE_ONE (1) -#define TIMER1_SR_MODE_INTVL (2) - -#define TIMER1_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x050 )) -#define TIMER1_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x060 )) -#define TIMER1_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x070 )) - -#endif /* __TIMER00_H */ diff --git a/include/asm-arm/arch-epxa10db/timex.h b/include/asm-arm/arch-epxa10db/timex.h deleted file mode 100644 index b87a75fc958..00000000000 --- a/include/asm-arm/arch-epxa10db/timex.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * linux/include/asm-arm/arch-epxa10db/timex.h - * - * Excalibur timex specifications - * - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -/* - * ?? - */ -#define CLOCK_TICK_RATE (50000000 / 16) diff --git a/include/asm-arm/arch-epxa10db/uart00.h b/include/asm-arm/arch-epxa10db/uart00.h deleted file mode 100644 index 5abd8914d68..00000000000 --- a/include/asm-arm/arch-epxa10db/uart00.h +++ /dev/null @@ -1,181 +0,0 @@ -/* * - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __UART00_H -#define __UART00_H - -/* - * Register definitions for the UART - */ - -#define UART_TX_FIFO_SIZE (15) - -#define UART_RSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x00 )) -#define UART_RSR_RX_LEVEL_MSK (0x1f) -#define UART_RSR_RX_LEVEL_OFST (0) -#define UART_RSR_RE_MSK (0x80) -#define UART_RSR_RE_OFST (7) - -#define UART_RDS(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x04 )) -#define UART_RDS_BI_MSK (0x8) -#define UART_RDS_BI_OFST (4) -#define UART_RDS_FE_MSK (0x4) -#define UART_RDS_FE_OFST (2) -#define UART_RDS_PE_MSK (0x2) -#define UART_RDS_PE_OFST (1) -#define UART_RDS_OE_MSK (0x1) -#define UART_RDS_OE_OFST (0) - -#define UART_RD(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x08 )) -#define UART_RD_RX_DATA_MSK (0xff) -#define UART_RD_RX_DATA_OFST (0) - -#define UART_TSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x0c )) -#define UART_TSR_TX_LEVEL_MSK (0x1f) -#define UART_TSR_TX_LEVEL_OFST (0) -#define UART_TSR_TXI_MSK (0x80) -#define UART_TSR_TXI_OFST (7) - -#define UART_TD(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x10 )) -#define UART_TD_TX_DATA_MSK (0xff) -#define UART_TD_TX_DATA_OFST (0) - -#define UART_FCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x14 )) -#define UART_FCR_RX_THR_MSK (0xd0) -#define UART_FCR_RX_THR_OFST (5) -#define UART_FCR_RX_THR_1 (0x00) -#define UART_FCR_RX_THR_2 (0x20) -#define UART_FCR_RX_THR_4 (0x40) -#define UART_FCR_RX_THR_6 (0x60) -#define UART_FCR_RX_THR_8 (0x80) -#define UART_FCR_RX_THR_10 (0xa0) -#define UART_FCR_RX_THR_12 (0xc0) -#define UART_FCR_RX_THR_14 (0xd0) -#define UART_FCR_TX_THR_MSK (0x1c) -#define UART_FCR_TX_THR_OFST (2) -#define UART_FCR_TX_THR_0 (0x00) -#define UART_FCR_TX_THR_2 (0x04) -#define UART_FCR_TX_THR_4 (0x08) -#define UART_FCR_TX_THR_8 (0x0c) -#define UART_FCR_TX_THR_10 (0x10) -#define UART_FCR_TX_THR_12 (0x14) -#define UART_FCR_TX_THR_14 (0x18) -#define UART_FCR_TX_THR_15 (0x1c) -#define UART_FCR_RC_MSK (0x02) -#define UART_FCR_RC_OFST (1) -#define UART_FCR_TC_MSK (0x01) -#define UART_FCR_TC_OFST (0) - -#define UART_IES(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x18 )) -#define UART_IES_ME_MSK (0x8) -#define UART_IES_ME_OFST (3) -#define UART_IES_TIE_MSK (0x4) -#define UART_IES_TIE_OFST (2) -#define UART_IES_TE_MSK (0x2) -#define UART_IES_TE_OFST (1) -#define UART_IES_RE_MSK (0x1) -#define UART_IES_RE_OFST (0) - -#define UART_IEC(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x1c )) -#define UART_IEC_ME_MSK (0x8) -#define UART_IEC_ME_OFST (3) -#define UART_IEC_TIE_MSK (0x4) -#define UART_IEC_TIE_OFST (2) -#define UART_IEC_TE_MSK (0x2) -#define UART_IEC_TE_OFST (1) -#define UART_IEC_RE_MSK (0x1) -#define UART_IEC_RE_OFST (0) - -#define UART_ISR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x20 )) -#define UART_ISR_MI_MSK (0x8) -#define UART_ISR_MI_OFST (3) -#define UART_ISR_TII_MSK (0x4) -#define UART_ISR_TII_OFST (2) -#define UART_ISR_TI_MSK (0x2) -#define UART_ISR_TI_OFST (1) -#define UART_ISR_RI_MSK (0x1) -#define UART_ISR_RI_OFST (0) - -#define UART_IID(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x24 )) -#define UART_IID_IID_MSK (0x7) -#define UART_IID_IID_OFST (0) - -#define UART_MC(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x28 )) -#define UART_MC_OE_MSK (0x40) -#define UART_MC_OE_OFST (6) -#define UART_MC_SP_MSK (0x20) -#define UART_MC_SP_OFST (5) -#define UART_MC_EP_MSK (0x10) -#define UART_MC_EP_OFST (4) -#define UART_MC_PE_MSK (0x08) -#define UART_MC_PE_OFST (3) -#define UART_MC_ST_MSK (0x04) -#define UART_MC_ST_ONE (0x0) -#define UART_MC_ST_TWO (0x04) -#define UART_MC_ST_OFST (2) -#define UART_MC_CLS_MSK (0x03) -#define UART_MC_CLS_OFST (0) -#define UART_MC_CLS_CHARLEN_5 (0) -#define UART_MC_CLS_CHARLEN_6 (1) -#define UART_MC_CLS_CHARLEN_7 (2) -#define UART_MC_CLS_CHARLEN_8 (3) - -#define UART_MCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x2c )) -#define UART_MCR_AC_MSK (0x80) -#define UART_MCR_AC_OFST (7) -#define UART_MCR_AR_MSK (0x40) -#define UART_MCR_AR_OFST (6) -#define UART_MCR_BR_MSK (0x20) -#define UART_MCR_BR_OFST (5) -#define UART_MCR_LB_MSK (0x10) -#define UART_MCR_LB_OFST (4) -#define UART_MCR_DCD_MSK (0x08) -#define UART_MCR_DCD_OFST (3) -#define UART_MCR_RI_MSK (0x04) -#define UART_MCR_RI_OFST (2) -#define UART_MCR_DTR_MSK (0x02) -#define UART_MCR_DTR_OFST (1) -#define UART_MCR_RTS_MSK (0x01) -#define UART_MCR_RTS_OFST (0) - -#define UART_MSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x30 )) -#define UART_MSR_DCD_MSK (0x80) -#define UART_MSR_DCD_OFST (7) -#define UART_MSR_RI_MSK (0x40) -#define UART_MSR_RI_OFST (6) -#define UART_MSR_DSR_MSK (0x20) -#define UART_MSR_DSR_OFST (5) -#define UART_MSR_CTS_MSK (0x10) -#define UART_MSR_CTS_OFST (4) -#define UART_MSR_DDCD_MSK (0x08) -#define UART_MSR_DDCD_OFST (3) -#define UART_MSR_TERI_MSK (0x04) -#define UART_MSR_TERI_OFST (2) -#define UART_MSR_DDSR_MSK (0x02) -#define UART_MSR_DDSR_OFST (1) -#define UART_MSR_DCTS_MSK (0x01) -#define UART_MSR_DCTS_OFST (0) - -#define UART_DIV_LO(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x34 )) -#define UART_DIV_LO_DIV_MSK (0xff) -#define UART_DIV_LO_DIV_OFST (0) - -#define UART_DIV_HI(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x38 )) -#define UART_DIV_HI_DIV_MSK (0xff) -#define UART_DIV_HI_DIV_OFST (0) - -#endif /* __UART00_H */ diff --git a/include/asm-arm/arch-epxa10db/uncompress.h b/include/asm-arm/arch-epxa10db/uncompress.h deleted file mode 100644 index fdfe0e6848f..00000000000 --- a/include/asm-arm/arch-epxa10db/uncompress.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * linux/include/asm-arm/arch-epxa10db/uncompress.h - * - * Copyright (C) 1999 ARM Limited - * Copyright (C) 2001 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include "asm/arch/platform.h" -#include "asm/hardware.h" -#define UART00_TYPE (volatile unsigned int*) -#include "asm/arch/uart00.h" - -/* - * This does not append a newline - */ -static void putstr(const char *s) -{ - while (*s) { - while ((*UART_TSR(EXC_UART00_BASE) & - UART_TSR_TX_LEVEL_MSK)==15) - barrier(); - - *UART_TD(EXC_UART00_BASE) = *s; - - if (*s == '\n') { - while ((*UART_TSR(EXC_UART00_BASE) & - UART_TSR_TX_LEVEL_MSK)==15) - barrier(); - - *UART_TD(EXC_UART00_BASE) = '\r'; - } - s++; - } -} - -/* - * nothing to do - */ -#define arch_decomp_setup() - -#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-epxa10db/vmalloc.h b/include/asm-arm/arch-epxa10db/vmalloc.h deleted file mode 100644 index 546fb7d2b6a..00000000000 --- a/include/asm-arm/arch-epxa10db/vmalloc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * linux/include/asm-arm/arch-epxa10db/vmalloc.h - * - * Copyright (C) 2000 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define VMALLOC_END (PAGE_OFFSET + 0x10000000) |