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-rw-r--r--arch/sh/Kconfig6
-rw-r--r--arch/sh/kernel/cpu/clock.c13
2 files changed, 1 insertions, 18 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 01bc7d589af..504d56f8ca7 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -396,14 +396,8 @@ source "arch/sh/boards/renesas/hs7751rvoip/Kconfig"
source "arch/sh/boards/renesas/rts7751r2d/Kconfig"
-config SH_PCLK_FREQ_BOOL
- bool "Set default pclk frequency"
- default y if !SH_RTC
- default n
-
config SH_PCLK_FREQ
int "Peripheral clock frequency (in Hz)"
- depends on SH_PCLK_FREQ_BOOL
default "50000000" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7780
default "60000000" if CPU_SUBTYPE_SH7751
default "33333333" if CPU_SUBTYPE_SH7300 || CPU_SUBTYPE_SH7770 || CPU_SUBTYPE_SH7760
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index 989e7fdd524..97fa37f42b8 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -38,9 +38,7 @@ static DECLARE_MUTEX(clock_list_sem);
static struct clk master_clk = {
.name = "master_clk",
.flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
-#ifdef CONFIG_SH_PCLK_FREQ_BOOL
.rate = CONFIG_SH_PCLK_FREQ,
-#endif
};
static struct clk module_clk = {
@@ -227,16 +225,7 @@ int __init clk_init(void)
{
int i, ret = 0;
- if (unlikely(!master_clk.rate))
- /*
- * NOTE: This will break if the default divisor has been
- * changed.
- *
- * No one should be changing the default on us however,
- * expect that a sane value for CONFIG_SH_PCLK_FREQ will
- * be defined in the event of a different divisor.
- */
- master_clk.rate = get_timer_frequency() * 4;
+ BUG_ON(unlikely(!master_clk.rate));
for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
struct clk *clk = onchip_clocks[i];