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-rw-r--r--arch/arm/configs/gta02_drm_defconfig2186
-rw-r--r--arch/arm/mach-s3c2442/mach-gta02.c3
-rw-r--r--drivers/gpu/drm/Kconfig8
-rw-r--r--drivers/gpu/drm/drm_bufs.c2
-rw-r--r--drivers/gpu/drm/drm_drv.c30
-rw-r--r--drivers/gpu/drm/drm_ioctl.c140
-rw-r--r--drivers/gpu/drm/drm_proc.c21
-rw-r--r--drivers/gpu/drm/drm_stub.c80
-rw-r--r--drivers/gpu/drm/drm_sysfs.c6
-rw-r--r--drivers/mfd/glamo/Kconfig25
-rw-r--r--drivers/mfd/glamo/Makefile6
-rw-r--r--drivers/mfd/glamo/glamo-buffer.c372
-rw-r--r--drivers/mfd/glamo/glamo-buffer.h60
-rw-r--r--drivers/mfd/glamo/glamo-cmdq.c524
-rw-r--r--drivers/mfd/glamo/glamo-cmdq.h49
-rw-r--r--drivers/mfd/glamo/glamo-core.c204
-rw-r--r--drivers/mfd/glamo/glamo-core.h40
-rw-r--r--drivers/mfd/glamo/glamo-display.c927
-rw-r--r--drivers/mfd/glamo/glamo-display.h39
-rw-r--r--drivers/mfd/glamo/glamo-drm-drv.c434
-rw-r--r--drivers/mfd/glamo/glamo-drm-private.h155
-rw-r--r--drivers/mfd/glamo/glamo-fb.c6
-rw-r--r--drivers/mfd/glamo/glamo-fence.c327
-rw-r--r--drivers/mfd/glamo/glamo-fence.h34
-rw-r--r--drivers/mfd/glamo/glamo-kms-fb.c539
-rw-r--r--drivers/mfd/glamo/glamo-kms-fb.h41
-rw-r--r--drivers/mfd/glamo/glamo-mci.c8
-rw-r--r--drivers/mfd/glamo/glamo-regs.h24
-rw-r--r--drivers/video/display/jbt6k74.c17
-rw-r--r--include/drm/Kbuild1
-rw-r--r--include/drm/drmP.h13
-rw-r--r--include/drm/glamo_drm.h153
32 files changed, 6263 insertions, 211 deletions
diff --git a/arch/arm/configs/gta02_drm_defconfig b/arch/arm/configs/gta02_drm_defconfig
new file mode 100644
index 00000000000..5349014e819
--- /dev/null
+++ b/arch/arm/configs/gta02_drm_defconfig
@@ -0,0 +1,2186 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29-rc3
+# Thu Jul 2 20:40:33 2009
+#
+CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+CONFIG_NO_IOPORT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_FIQ=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=18
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_ASHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=m
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=m
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+CONFIG_ARCH_S3C2410=y
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_W90X900 is not set
+CONFIG_PLAT_S3C24XX=y
+CONFIG_S3C2410_CLOCK=y
+CONFIG_CPU_S3C244X=y
+CONFIG_S3C24XX_PWM=y
+CONFIG_S3C24XX_GPIO_EXTRA=0
+CONFIG_S3C2410_DMA=y
+# CONFIG_S3C2410_DMA_DEBUG is not set
+# CONFIG_S3C24XX_ADC is not set
+CONFIG_MACH_SMDK=y
+CONFIG_MACH_NEO1973=y
+CONFIG_PLAT_S3C=y
+CONFIG_CPU_LLSERIAL_S3C2410=y
+CONFIG_CPU_LLSERIAL_S3C2440=y
+
+#
+# Boot options
+#
+# CONFIG_S3C_BOOT_WATCHDOG is not set
+# CONFIG_S3C_BOOT_ERROR_RESET is not set
+CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
+
+#
+# Power management
+#
+# CONFIG_S3C2410_PM_DEBUG is not set
+# CONFIG_S3C2410_PM_CHECK is not set
+CONFIG_S3C_LOWLEVEL_UART_PORT=2
+CONFIG_S3C_GPIO_SPACE=0
+CONFIG_S3C_GPIO_TRACK=y
+CONFIG_S3C_DMA=y
+CONFIG_S3C_PWM=y
+CONFIG_S3C_DEV_USB_HOST=y
+
+#
+# S3C2400 Machines
+#
+CONFIG_CPU_S3C2410=y
+CONFIG_CPU_S3C2410_DMA=y
+CONFIG_S3C2410_PM=y
+CONFIG_S3C2410_GPIO=y
+
+#
+# S3C2410 Machines
+#
+# CONFIG_ARCH_SMDK2410 is not set
+# CONFIG_ARCH_H1940 is not set
+# CONFIG_MACH_N30 is not set
+# CONFIG_ARCH_BAST is not set
+# CONFIG_MACH_OTOM is not set
+# CONFIG_MACH_AML_M5900 is not set
+# CONFIG_MACH_TCT_HAMMER is not set
+# CONFIG_MACH_VR1000 is not set
+CONFIG_MACH_QT2410=y
+# CONFIG_MACH_NEO1973_GTA01 is not set
+
+#
+# S3C2412 Machines
+#
+# CONFIG_MACH_JIVE is not set
+# CONFIG_MACH_SMDK2413 is not set
+# CONFIG_MACH_SMDK2412 is not set
+# CONFIG_MACH_VSTMS is not set
+CONFIG_CPU_S3C2440=y
+CONFIG_S3C2440_DMA=y
+
+#
+# S3C2440 Machines
+#
+# CONFIG_MACH_ANUBIS is not set
+# CONFIG_MACH_OSIRIS is not set
+# CONFIG_MACH_RX3715 is not set
+CONFIG_ARCH_S3C2440=y
+# CONFIG_MACH_NEXCODER_2440 is not set
+CONFIG_SMDK2440_CPU2440=y
+# CONFIG_MACH_AT2440EVB is not set
+# CONFIG_NEO1973_GTA02_2440 is not set
+CONFIG_CPU_S3C2442=y
+
+#
+# S3C2442 Machines
+#
+CONFIG_SMDK2440_CPU2442=y
+CONFIG_MACH_NEO1973_GTA02=y
+
+#
+# S3C2443 Machines
+#
+# CONFIG_MACH_SMDK2443 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=200
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="unused -- bootloader passes ATAG list"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_APM_EMULATION=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_NET_IPGRE_BROADCAST is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_TCP_MD5SIG=y
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+# CONFIG_NF_CT_PROTO_DCCP is not set
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+# CONFIG_NF_CT_PROTO_UDPLITE is not set
+# CONFIG_NF_CONNTRACK_AMANDA is not set
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+# CONFIG_NETFILTER_TPROXY is not set
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PROTO_SCTP=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+# CONFIG_NF_NAT_AMANDA is not set
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV6=m
+# CONFIG_IP6_NF_QUEUE is not set
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_TARGET_HL=m
+# CONFIG_IP6_NF_RAW is not set
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+# CONFIG_BRIDGE_EBT_IP6 is not set
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_ULOG=m
+# CONFIG_BRIDGE_EBT_NFLOG is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=y
+CONFIG_BRIDGE=y
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+# CONFIG_NET_SCH_MULTIQ is not set
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+# CONFIG_NET_SCH_DRR is not set
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_PERF=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=m
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_WIMAX is not set
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_LEDS=y
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_S3C2410=y
+CONFIG_MTD_NAND_S3C2410_DEBUG=y
+CONFIG_MTD_NAND_S3C2410_HWECC=y
+# CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+# CONFIG_MTD_QINFO_PROBE is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_UB=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+# CONFIG_USB_NET_SMSC95XX is not set
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_USB_HSO is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=640
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+CONFIG_KEYBOARD_STOWAWAY=m
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_KEYBOARD_NEO1973=y
+CONFIG_KEYBOARD_QT2410=y
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_FILTER=y
+CONFIG_TOUCHSCREEN_FILTER_GROUP=y
+CONFIG_TOUCHSCREEN_FILTER_MEDIAN=y
+CONFIG_TOUCHSCREEN_FILTER_MEAN=y
+CONFIG_TOUCHSCREEN_FILTER_LINEAR=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+CONFIG_TOUCHSCREEN_S3C2410=y
+# CONFIG_TOUCHSCREEN_S3C2410_DEBUG is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_PCAP7200 is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=m
+CONFIG_INPUT_LIS302DL=y
+CONFIG_INPUT_PCF50633_PMU=y
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_NR_TTY_DEVICES=8
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_UARTS=3
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_S3C2410=y
+CONFIG_SERIAL_S3C2440=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_S3C2410=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF50606 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+CONFIG_PCA9632=y
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_S3C24XX is not set
+CONFIG_SPI_S3C24XX_GPIO=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_PDA_POWER=y
+CONFIG_APM_POWER=y
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+CONFIG_CHARGER_PCF50633=y
+CONFIG_BATTERY_BQ27000_HDQ=y
+CONFIG_HDQ_GPIO_BITBANG=y
+# CONFIG_BATTERY_GTA01 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_S3C2410_WATCHDOG=m
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+CONFIG_MFD_PCF50633=y
+CONFIG_PCF50633_ADC=y
+CONFIG_PCF50633_GPIO=y
+# CONFIG_MFD_PCF50606 is not set
+CONFIG_MFD_GLAMO=y
+
+#
+# SMedia Glamo 336x/337x engine drivers
+#
+# CONFIG_MFD_GLAMO_FB is not set
+CONFIG_MFD_GLAMO_SPI_GPIO=y
+CONFIG_MFD_GLAMO_MCI=y
+CONFIG_MFD_GLAMO_DRM=y
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+CONFIG_DRM=y
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_S3C2410=y
+# CONFIG_FB_S3C2410_DEBUG is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_LTV350QV=y
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+# CONFIG_BACKLIGHT_PWM is not set
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+CONFIG_DISPLAY_JBT6K74=y
+# CONFIG_DISPLAY_L1K002 is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+# CONFIG_FONT_8x16 is not set
+CONFIG_FONT_6x11=y
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+CONFIG_SND_DEBUG=y
+# CONFIG_SND_DEBUG_VERBOSE is not set
+CONFIG_SND_PCM_XRUN_DEBUG=y
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_CAIAQ is not set
+CONFIG_SND_SOC=m
+CONFIG_SND_S3C24XX_SOC=m
+CONFIG_SND_S3C24XX_SOC_I2S=m
+CONFIG_SND_S3C24XX_SOC_NEO1973_GTA02_WM8753=m
+# CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650 is not set
+# CONFIG_SND_S3C24XX_SOC_S3C24XX_UDA134X is not set
+# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8731 is not set
+CONFIG_SND_SOC_I2C_AND_SPI=m
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_WM8753=m
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_HID_PID=y
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_NTRIG=y
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+# CONFIG_GREENASIA_FF is not set
+CONFIG_HID_TOPSEED=y
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=m
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+# CONFIG_USB_WDM is not set
+CONFIG_USB_TMC=m
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+# CONFIG_USB_STORAGE_ISD200 is not set
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_USB_STORAGE_ALAUDA=y
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+CONFIG_USB_STORAGE_KARMA=y
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+# CONFIG_USB_SERIAL_CH341 is not set
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP2101=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+# CONFIG_USB_SERIAL_IUU is not set
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+CONFIG_USB_SERIAL_SAFE_PADDED=y
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+CONFIG_USB_BERRY_CHARGE=m
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+CONFIG_USB_TRANCEVIBRATOR=m
+CONFIG_USB_IOWARRIOR=m
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+CONFIG_USB_GADGET_S3C2410=y
+CONFIG_USB_S3C2410=y
+CONFIG_USB_S3C2410_DEBUG=y
+# CONFIG_USB_GADGET_S3C_OTGD_HS is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_MIDI_GADGET=m
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+CONFIG_AR6000_WLAN=m
+# CONFIG_AR6000_WLAN_DEBUG is not set
+# CONFIG_AR6000_WLAN_RESET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_S3C=m
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_PCA955X is not set
+CONFIG_LEDS_NEO1973_VIBRATOR=y
+CONFIG_LEDS_NEO1973_GTA02=y
+# CONFIG_LEDS_LP5521 is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_LEDS_TRIGGER_NETDEV=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+CONFIG_RTC_DRV_PCF50633=y
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_S3C=m
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_DEBUG=y
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+CONFIG_REGULATOR_PCF50633=y
+CONFIG_UIO=y
+CONFIG_UIO_PDRV=y
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_MEILHAUS is not set
+# CONFIG_USB_IP_COMMON is not set
+# CONFIG_ECHO is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_INPUT_MIMIO is not set
+# CONFIG_TRANZPORT is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_RAM_CONSOLE=y
+CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y
+# CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION is not set
+# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set
+CONFIG_ANDROID_TIMED_GPIO=y
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+# CONFIG_ANDROID_WAKELOCK is not set
+CONFIG_ANDROID_PARANOID_NETWORK=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+CONFIG_SQUASHFS=m
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+# CONFIG_NFS_V4 is not set
+CONFIG_NFSD=m
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_LOCK_ALLOC=y
+# CONFIG_PROVE_LOCKING is not set
+CONFIG_LOCKDEP=y
+CONFIG_LOCK_STAT=y
+CONFIG_DEBUG_LOCKDEP=y
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+CONFIG_DEBUG_SG=y
+# CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_DETECTOR=y
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_LATENCYTOP=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_FIND_IRQ_BLOCKERS is not set
+CONFIG_DYNAMIC_PRINTK_DEBUG=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+CONFIG_DEBUG_S3C_UART=2
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+CONFIG_SECURITYFS=y
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_FIPS=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/mach-s3c2442/mach-gta02.c b/arch/arm/mach-s3c2442/mach-gta02.c
index 380effad4d4..42b8cea9ff1 100644
--- a/arch/arm/mach-s3c2442/mach-gta02.c
+++ b/arch/arm/mach-s3c2442/mach-gta02.c
@@ -1439,7 +1439,8 @@ static struct glamofb_platform_data gta02_glamo_pdata = {
.lower_margin = 16,
.hsync_len = 8,
.vsync_len = 2,
- .fb_mem_size = 0x400000, /* glamo has 8 megs of SRAM. we use 4 */
+ //.fb_mem_size = 0x400000, /* glamo has 8 megs of SRAM. we use 4 */
+ .fb_mem_size = 0x12c000, /* 640 x 480 x 4 = 1200 kiB */
.xres = {
.min = 240,
.max = 640,
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 5130b72d593..44f95952a8f 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -6,7 +6,7 @@
#
menuconfig DRM
tristate "Direct Rendering Manager (XFree86 4.1.0 and higher DRI support)"
- depends on (AGP || AGP=n) && PCI && !EMULATED_CMPXCHG && MMU
+ depends on (AGP || AGP=n) && !EMULATED_CMPXCHG && MMU
select I2C
select I2C_ALGOBIT
help
@@ -95,7 +95,7 @@ config DRM_I915_KMS
config DRM_MGA
tristate "Matrox g200/g400"
- depends on DRM
+ depends on DRM && PCI && AGP
help
Choose this option if you have a Matrox G200, G400 or G450 graphics
card. If M is selected, the module will be called mga. AGP
@@ -112,14 +112,14 @@ config DRM_SIS
config DRM_VIA
tristate "Via unichrome video cards"
- depends on DRM
+ depends on DRM && PCI
help
Choose this option if you have a Via unichrome or compatible video
chipset. If M is selected the module will be called via.
config DRM_SAVAGE
tristate "Savage video cards"
- depends on DRM
+ depends on DRM && PCI
help
Choose this option if you have a Savage3D/4/SuperSavage/Pro/Twister
chipset. If M is selected the module will be called savage.
diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
index 72c667f9bee..f56bc66c38a 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -141,7 +141,7 @@ static int drm_addmap_core(struct drm_device * dev, unsigned int offset,
switch (map->type) {
case _DRM_REGISTERS:
case _DRM_FRAME_BUFFER:
-#if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__) && !defined(__powerpc64__) && !defined(__x86_64__)
+#if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__) && !defined(__powerpc64__) && !defined(__x86_64__) && !defined(__arm__)
if (map->offset + (map->size-1) < map->offset ||
map->offset < virt_to_phys(high_memory)) {
drm_free(map, sizeof(*map), DRM_MEM_MAPS);
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 14c7a23dc15..4bc5cab825b 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -251,6 +251,7 @@ int drm_lastclose(struct drm_device * dev)
*/
int drm_init(struct drm_driver *driver)
{
+#ifdef CONFIG_PCI
struct pci_dev *pdev = NULL;
struct pci_device_id *pid;
int i;
@@ -280,12 +281,41 @@ int drm_init(struct drm_driver *driver)
drm_get_dev(pdev, pid, driver);
}
}
+#endif
return 0;
}
EXPORT_SYMBOL(drm_init);
/**
+ *
+ * Call this to associate a drm_driver with a platform_device.
+ *
+ * \return zero on success or a negative number on failure.
+ *
+ * This is a replacement for drm_init(), but for platform drivers.
+ * In this case, the caller must provide the matching platform_device
+ *
+ * since there is no physical bus to scan through.
+ *
+ * \sa drm_init
+ *
+ */
+
+int drm_platform_init(struct drm_driver *driver, struct platform_device *pdev,
+ void *priv)
+{
+ DRM_DEBUG("\n");
+
+ INIT_LIST_HEAD(&driver->device_list);
+
+ return drm_get_platform_dev(pdev, driver, priv);
+}
+
+EXPORT_SYMBOL(drm_platform_init);
+
+
+/**
* Called via cleanup_module() at module unload time.
*
* Cleans up all DRM device, calling drm_lastclose().
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 1fad76289e6..cebde45b638 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -83,8 +83,7 @@ int drm_setunique(struct drm_device *dev, void *data,
{
struct drm_unique *u = data;
struct drm_master *master = file_priv->master;
- int domain, bus, slot, func, ret;
-
+
if (master->unique_len || master->unique)
return -EBUSY;
@@ -101,29 +100,50 @@ int drm_setunique(struct drm_device *dev, void *data,
master->unique[master->unique_len] = '\0';
- dev->devname =
- drm_alloc(strlen(dev->driver->pci_driver.name) +
- strlen(master->unique) + 2, DRM_MEM_DRIVER);
- if (!dev->devname)
- return -ENOMEM;
-
- sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name,
- master->unique);
-
- /* Return error if the busid submitted doesn't match the device's actual
- * busid.
- */
- ret = sscanf(master->unique, "PCI:%d:%d:%d", &bus, &slot, &func);
- if (ret != 3)
- return -EINVAL;
- domain = bus >> 8;
- bus &= 0xff;
-
- if ((domain != drm_get_pci_domain(dev)) ||
- (bus != dev->pdev->bus->number) ||
- (slot != PCI_SLOT(dev->pdev->devfn)) ||
- (func != PCI_FUNC(dev->pdev->devfn)))
- return -EINVAL;
+ if ( !drm_core_is_platform(dev) ) {
+
+ /* PCI device */
+
+ int domain, bus, slot, func, ret;
+
+ dev->devname =
+ drm_alloc(strlen(dev->driver->pci_driver.name) +
+ strlen(master->unique) + 2, DRM_MEM_DRIVER);
+ if (!dev->devname)
+ return -ENOMEM;
+
+ sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name,
+ master->unique);
+
+ /* Return error if the busid submitted doesn't match the
+ * device's actual busid.
+ */
+ ret = sscanf(master->unique, "PCI:%d:%d:%d",
+ &bus, &slot, &func);
+ if (ret != 3)
+ return -EINVAL;
+ domain = bus >> 8;
+ bus &= 0xff;
+
+ if ((domain != drm_get_pci_domain(dev)) ||
+ (bus != dev->pdev->bus->number) ||
+ (slot != PCI_SLOT(dev->pdev->devfn)) ||
+ (func != PCI_FUNC(dev->pdev->devfn)))
+ return -EINVAL;
+
+ } else {
+
+ /* Platform device */
+ dev->devname =
+ drm_alloc(strlen(dev->driver->name) +
+ strlen(master->unique) + 2, DRM_MEM_DRIVER);
+ if (!dev->devname)
+ return -ENOMEM;
+
+ sprintf(dev->devname, "%s@%s", dev->driver->name,
+ master->unique);
+
+ }
return 0;
}
@@ -131,8 +151,7 @@ int drm_setunique(struct drm_device *dev, void *data,
static int drm_set_busid(struct drm_device *dev, struct drm_file *file_priv)
{
struct drm_master *master = file_priv->master;
- int len;
-
+
if (master->unique != NULL)
return -EBUSY;
@@ -142,25 +161,58 @@ static int drm_set_busid(struct drm_device *dev, struct drm_file *file_priv)
if (master->unique == NULL)
return -ENOMEM;
- len = snprintf(master->unique, master->unique_len, "pci:%04x:%02x:%02x.%d",
- drm_get_pci_domain(dev),
- dev->pdev->bus->number,
- PCI_SLOT(dev->pdev->devfn),
- PCI_FUNC(dev->pdev->devfn));
- if (len >= master->unique_len)
- DRM_ERROR("buffer overflow");
- else
- master->unique_len = len;
-
- dev->devname =
- drm_alloc(strlen(dev->driver->pci_driver.name) + master->unique_len +
- 2, DRM_MEM_DRIVER);
- if (dev->devname == NULL)
- return -ENOMEM;
+ if ( !drm_core_is_platform(dev) ) {
+
+ /* PCI device */
+
+ int len;
+
+ len = snprintf(master->unique, master->unique_len,
+ "pci:%04x:%02x:%02x.%d",
+ drm_get_pci_domain(dev),
+ dev->pdev->bus->number,
+ PCI_SLOT(dev->pdev->devfn),
+ PCI_FUNC(dev->pdev->devfn));
+
+ if (len >= master->unique_len)
+ DRM_ERROR("buffer overflow");
+ else
+ master->unique_len = len;
+
+ dev->devname =
+ drm_alloc(strlen(dev->driver->pci_driver.name)
+ + master->unique_len + 2, DRM_MEM_DRIVER);
+ if (dev->devname == NULL)
+ return -ENOMEM;
+
+ sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name,
+ master->unique);
+
+ } else {
+
+ /* Platform device */
+
+ int len;
+
+ len = snprintf(master->unique, master->unique_len,
+ "platform:%s", dev->platform_dev->name);
+
+ if (len >= master->unique_len)
+ DRM_ERROR("buffer overflow");
+ else
+ master->unique_len = len;
- sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name,
- master->unique);
+ dev->devname =
+ drm_alloc(strlen(dev->driver->name)
+ + master->unique_len + 2, DRM_MEM_DRIVER);
+ if (dev->devname == NULL)
+ return -ENOMEM;
+ sprintf(dev->devname, "%s@%s", dev->driver->name,
+ master->unique);
+
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/drm_proc.c b/drivers/gpu/drm/drm_proc.c
index 8df849f6683..255b12f9a15 100644
--- a/drivers/gpu/drm/drm_proc.c
+++ b/drivers/gpu/drm/drm_proc.c
@@ -214,14 +214,23 @@ static int drm_name_info(char *buf, char **start, off_t offset, int request,
*eof = 0;
if (master->unique) {
- DRM_PROC_PRINT("%s %s %s\n",
- dev->driver->pci_driver.name,
- pci_name(dev->pdev), master->unique);
+ if (drm_core_is_platform(dev)) {
+ DRM_PROC_PRINT("%s %s %s\n", dev->driver->name,
+ dev_name(&dev->platform_dev->dev), master->unique);
+ } else {
+ DRM_PROC_PRINT("%s %s %s\n",
+ dev->driver->pci_driver.name,
+ pci_name(dev->pdev), master->unique);
+ }
} else {
- DRM_PROC_PRINT("%s %s\n", dev->driver->pci_driver.name,
- pci_name(dev->pdev));
+ if (drm_core_is_platform(dev)) {
+ DRM_PROC_PRINT("%s %s\n", dev->driver->name,
+ dev_name(&dev->platform_dev->dev));
+ } else {
+ DRM_PROC_PRINT("%s %s\n", dev->driver->pci_driver.name,
+ pci_name(dev->pdev));
+ }
}
-
if (len > request + offset)
return request;
*eof = 1;
diff --git a/drivers/gpu/drm/drm_stub.c b/drivers/gpu/drm/drm_stub.c
index 46bb923b097..93ce6cc030f 100644
--- a/drivers/gpu/drm/drm_stub.c
+++ b/drivers/gpu/drm/drm_stub.c
@@ -213,12 +213,13 @@ static int drm_fill_in_dev(struct drm_device * dev, struct pci_dev *pdev,
idr_init(&dev->drw_idr);
dev->pdev = pdev;
- dev->pci_device = pdev->device;
- dev->pci_vendor = pdev->vendor;
-
+ if (pdev) {
+ dev->pci_device = pdev->device;
+ dev->pci_vendor = pdev->vendor;
#ifdef __alpha__
dev->hose = pdev->sysdata;
#endif
+ }
if (drm_ht_create(&dev->map_hash, 12)) {
return -ENOMEM;
@@ -418,6 +419,79 @@ err_g1:
return ret;
}
+ /**
+ *
+ * Register a platform device as a DRM device
+ *
+ * \param pdev - platform device structure
+ * \param driver - the matching drm_driver structure
+ * \return zero on success or a negative number on failure.
+ *
+ * Attempt to gets inter module "drm" information. If we are first
+ * then register the character device and inter module information.
+ * Try and register, if we fail to register, backout previous work.
+ *
+ * \sa drm_get_dev
+ */
+int drm_get_platform_dev(struct platform_device *pdev,
+ struct drm_driver *driver, void *priv)
+{
+ struct drm_device *dev;
+ int ret;
+#if 0
+ int len;
+#endif
+ DRM_DEBUG("\n");
+
+ dev = drm_calloc(1, sizeof(*dev), DRM_MEM_STUB);
+ if (!dev)
+ return -ENOMEM;
+ dev->dev_private = priv;
+
+ if ((ret = drm_fill_in_dev(dev, NULL, NULL, driver))) {
+ printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
+ goto err_g1;
+ }
+ dev->platform_dev = pdev;
+
+ if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+ ret = drm_get_minor(dev, &dev->control, DRM_MINOR_CONTROL);
+ if (ret)
+ goto err_g2;
+ }
+
+ if ((ret = drm_get_minor(dev, &dev->primary, DRM_MINOR_LEGACY)))
+ goto err_g3;
+
+ if (dev->driver->load) {
+ ret = dev->driver->load(dev, 0);
+ if (ret)
+ goto err_g3;
+ }
+
+ /* setup the grouping for the legacy output */
+ if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+ ret = drm_mode_group_init_legacy_group(dev, &dev->primary->mode_group);
+ if (ret)
+ goto err_g3;
+ }
+
+ list_add_tail(&dev->driver_item, &driver->device_list);
+
+ DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
+ driver->name, driver->major, driver->minor, driver->patchlevel,
+ driver->date, dev->primary->index);
+
+ return 0;
+
+err_g3:
+ drm_put_minor(&dev->primary);
+err_g2:
+err_g1:
+ drm_free(dev, sizeof(*dev), DRM_MEM_STUB);
+ return ret;
+}
+
/**
* Put a device minor number.
*
diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
index 5aa6780652a..44f7f16ebd6 100644
--- a/drivers/gpu/drm/drm_sysfs.c
+++ b/drivers/gpu/drm/drm_sysfs.c
@@ -477,7 +477,11 @@ int drm_sysfs_device_add(struct drm_minor *minor)
int i, j;
char *minor_str;
- minor->kdev.parent = &minor->dev->pdev->dev;
+ if (minor->dev->pdev) {
+ minor->kdev.parent = &minor->dev->pdev->dev;
+ } else {
+ minor->kdev.parent = &minor->dev->platform_dev->dev;
+ }
minor->kdev.class = drm_class;
minor->kdev.release = drm_sysfs_device_release;
minor->kdev.devt = minor->device;
diff --git a/drivers/mfd/glamo/Kconfig b/drivers/mfd/glamo/Kconfig
index efa16990d57..7db45288c38 100644
--- a/drivers/mfd/glamo/Kconfig
+++ b/drivers/mfd/glamo/Kconfig
@@ -1,12 +1,15 @@
config MFD_GLAMO
- bool "Smedia Glamo 336x/337x support"
+ bool "SMedia Glamo 336x/337x support"
help
This enables the core driver for the Smedia Glamo 336x/337x
multi-function device. It includes irq_chip demultiplex as
well as clock / power management and GPIO support.
+menu "SMedia Glamo 336x/337x engine drivers"
+ depends on MFD_GLAMO
+
config MFD_GLAMO_FB
- tristate "Smedia Glamo 336x/337x framebuffer support"
+ tristate "SMedia Glamo 336x/337x framebuffer support"
depends on FB && MFD_GLAMO
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
@@ -31,7 +34,6 @@ config MFD_GLAMO_FB_XGLAMO_WORKAROUND
If unsure, say N.
-
config MFD_GLAMO_SPI_GPIO
tristate "Glamo GPIO SPI bitbang support"
depends on MFD_GLAMO
@@ -57,3 +59,20 @@ config MFD_GLAMO_MCI
neo1973 GTA-02.
If unsure, say N.
+
+config MFD_GLAMO_DRM
+ tristate "Glamo direct rendering and kernel modesetting support"
+ depends on MFD_GLAMO && DRM
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+ help
+ Direct Rendering Manager interface for the S-Media Glamo chip, as
+ used in Openmoko FreeRunner (GTA02).
+
+ This DRM driver includes kernel modesetting (KMS) support. As such,
+ do not select MFD_GLAMO_FB above if you choose to enable this option.
+
+ If unsure, say N.
+
+endmenu
diff --git a/drivers/mfd/glamo/Makefile b/drivers/mfd/glamo/Makefile
index dc64d50fa13..fb37517fcaf 100644
--- a/drivers/mfd/glamo/Makefile
+++ b/drivers/mfd/glamo/Makefile
@@ -1,7 +1,8 @@
#
-# Makefile for the Smedia Glamo framebuffer driver
+# Makefile for the Smedia Glamo driver(s)
#
+
obj-$(CONFIG_MFD_GLAMO) += glamo-core.o glamo-gpio.o
obj-$(CONFIG_MFD_GLAMO_SPI) += glamo-spi.o
obj-$(CONFIG_MFD_GLAMO_SPI_GPIO) += glamo-spi-gpio.o
@@ -9,4 +10,7 @@ obj-$(CONFIG_MFD_GLAMO_SPI_GPIO) += glamo-spi-gpio.o
obj-$(CONFIG_MFD_GLAMO_FB) += glamo-fb.o
obj-$(CONFIG_MFD_GLAMO_SPI_FB) += glamo-lcm-spi.o
obj-$(CONFIG_MFD_GLAMO_MCI) += glamo-mci.o
+obj-$(CONFIG_MFD_GLAMO_DRM) += glamo-drm.o
+glamo-drm-objs := glamo-drm-drv.o glamo-cmdq.o glamo-buffer.o \
+ glamo-display.o glamo-kms-fb.o glamo-fence.o
diff --git a/drivers/mfd/glamo/glamo-buffer.c b/drivers/mfd/glamo/glamo-buffer.c
new file mode 100644
index 00000000000..2bf9fb538cd
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-buffer.c
@@ -0,0 +1,372 @@
+/*
+ * SMedia Glamo 336x/337x memory management
+ *
+ * Copyright (c) 2009 Thomas White <taw@bitwiz.org.uk>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ *
+ * Memory mapping functions based on i915_gem.c, to which the following
+ * notice applies:
+ *
+ * Copyright © 2008 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Eric Anholt <eric@anholt.net>
+ */
+
+
+#include <drm/drmP.h>
+#include <drm/glamo_drm.h>
+
+#include "glamo-drm-private.h"
+#include "glamo-cmdq.h" /* For glamo_cmdq_blank() */
+
+
+struct drm_gem_object *glamo_gem_object_alloc(struct drm_device *dev, int size,
+ int alignment)
+{
+ struct drm_gem_object *obj;
+ struct glamodrm_handle *gdrm;
+ struct drm_glamo_gem_object *gobj;
+
+ gdrm = dev->dev_private;
+
+ size = roundup(size, PAGE_SIZE);
+
+ obj = drm_gem_object_alloc(dev, size);
+ if (obj == NULL) return NULL;
+
+ /* See glamodrm_gem_init_object() below */
+ gobj = obj->driver_private;
+
+ /* Allocate memory for this object in VRAM */
+ gobj->block = drm_mm_search_free(gdrm->mmgr, size, alignment, 1);
+ if (!gobj->block) {
+ goto fail;
+ }
+ gobj->block = drm_mm_get_block(gobj->block, size, alignment);
+ if (!gobj->block) {
+ goto fail;
+ }
+
+ /* Arrange for the contents to be set to zero */
+ glamo_cmdq_blank(gdrm, obj);
+
+ return obj;
+
+fail:
+ mutex_lock(&dev->struct_mutex);
+ drm_gem_object_unreference(obj);
+ mutex_unlock(&dev->struct_mutex);
+ printk(KERN_INFO "[glamo-drm] Failed to allocate object\n");
+
+ return NULL;
+}
+
+
+int glamo_ioctl_gem_create(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ struct drm_glamo_gem_create *args = data;
+ struct drm_gem_object *obj;
+ int handle, ret, alignment, size;
+
+ /* Alignment must be a non-zero multiple of 2 */
+ alignment = args->alignment;
+ if ( alignment < 2 ) alignment = 2;
+ if ( alignment % 2 ) alignment *= 2;
+
+ /* Size must be similarly sanitised */
+ size = args->size;
+ if ( size < 2 ) size = 2;
+ if ( size % 2 ) size += 1;
+
+ /* Create an object */
+ obj = glamo_gem_object_alloc(dev, size, alignment);
+ if ( obj == NULL ) return -ENOMEM;
+
+ /* Create a handle for it */
+ ret = drm_gem_handle_create(file_priv, obj, &handle);
+ mutex_lock(&dev->struct_mutex);
+ drm_gem_object_handle_unreference(obj);
+ mutex_unlock(&dev->struct_mutex);
+ if (ret) goto fail;
+
+ /* Return */
+ args->handle = handle;
+ return 0;
+
+fail:
+ mutex_lock(&dev->struct_mutex);
+ drm_gem_object_unreference(obj);
+ mutex_unlock(&dev->struct_mutex);
+ printk(KERN_INFO "[glamo-drm] Failed to allocate object\n");
+ return ret;
+}
+
+
+int glamodrm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
+{
+ struct drm_gem_object *obj = vma->vm_private_data;
+ struct drm_device *dev = obj->dev;
+ struct drm_glamo_gem_object *gobj = obj->driver_private;
+ struct glamodrm_handle *gdrm = dev->dev_private;
+ pgoff_t page_offset;
+ unsigned long pfn;
+ int ret = 0;
+
+ /* We don't use vmf->pgoff since that has the fake offset */
+ page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
+ PAGE_SHIFT;
+
+ mutex_lock(&dev->struct_mutex);
+ pfn = ((gdrm->vram->start + GLAMO_OFFSET_FB + gobj->block->start)
+ >> PAGE_SHIFT) + page_offset;
+ ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
+ mutex_unlock(&dev->struct_mutex);
+
+ switch (ret) {
+ case -ENOMEM:
+ case -EAGAIN:
+ return VM_FAULT_OOM;
+ case -EFAULT:
+ case -EBUSY:
+ DRM_ERROR("can't insert pfn?? fault or busy...\n");
+ return VM_FAULT_SIGBUS;
+ default:
+ return VM_FAULT_NOPAGE;
+ }
+}
+
+
+static int glamo_gem_create_mmap_offset(struct drm_gem_object *obj)
+{
+ struct drm_device *dev = obj->dev;
+ struct drm_gem_mm *mm = dev->mm_private;
+ struct drm_glamo_gem_object *gobj = obj->driver_private;
+ struct drm_map_list *list;
+ struct drm_map *map;
+ int ret = 0;
+
+ /* Set the object up for mmap'ing */
+ list = &obj->map_list;
+ list->map = drm_calloc(1, sizeof(struct drm_map_list), DRM_MEM_DRIVER);
+ if (!list->map)
+ return -ENOMEM;
+
+ map = list->map;
+ map->type = _DRM_GEM;
+ map->size = obj->size;
+ map->handle = obj;
+
+ /* Get a DRM GEM mmap offset allocated... */
+ list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
+ obj->size / PAGE_SIZE, 0, 0);
+ if (!list->file_offset_node) {
+ DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
+ ret = -ENOMEM;
+ goto out_free_list;
+ }
+
+ list->file_offset_node = drm_mm_get_block(list->file_offset_node,
+ obj->size / PAGE_SIZE, 0);
+ if (!list->file_offset_node) {
+ ret = -ENOMEM;
+ goto out_free_list;
+ }
+
+ list->hash.key = list->file_offset_node->start;
+ if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
+ DRM_ERROR("failed to add to map hash\n");
+ goto out_free_mm;
+ }
+
+ /* By now we should be all set, any drm_mmap request on the offset
+ * below will get to our mmap & fault handler */
+ gobj->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
+
+ return 0;
+
+out_free_mm:
+ drm_mm_put_block(list->file_offset_node);
+out_free_list:
+ drm_free(list->map, sizeof(struct drm_map_list), DRM_MEM_DRIVER);
+
+ return ret;
+}
+
+
+int glamo_ioctl_gem_mmap(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ struct drm_glamo_gem_mmap *args = data;
+ struct drm_gem_object *obj;
+ struct drm_glamo_gem_object *gobj;
+ int ret;
+
+ obj = drm_gem_object_lookup(dev, file_priv, args->handle);
+ if (obj == NULL)
+ return -EBADF;
+
+ mutex_lock(&dev->struct_mutex);
+
+ gobj = obj->driver_private;
+ if (!gobj->mmap_offset) {
+ ret = glamo_gem_create_mmap_offset(obj);
+ if (ret) {
+ mutex_unlock(&dev->struct_mutex);
+ return ret;
+ }
+ }
+
+ args->offset = gobj->mmap_offset;
+
+ drm_gem_object_unreference(obj);
+ mutex_unlock(&dev->struct_mutex);
+
+ return 0;
+}
+
+
+int glamo_ioctl_gem_pin(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ printk(KERN_INFO "glamo_ioctl_gem_pin\n");
+ return 0;
+}
+
+
+int glamo_ioctl_gem_unpin(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ printk(KERN_INFO "glamo_ioctl_gem_unpin\n");
+ return 0;
+}
+
+
+int glamo_ioctl_gem_pread(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ printk(KERN_INFO "glamo_ioctl_gem_pread\n");
+ return 0;
+}
+
+
+int glamo_ioctl_gem_pwrite(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ printk(KERN_INFO "glamo_ioctl_gem_pwrite\n");
+ return 0;
+}
+
+
+int glamodrm_gem_init_object(struct drm_gem_object *obj)
+{
+ struct drm_glamo_gem_object *gobj;
+
+ /* Allocate a private structure */
+ gobj = drm_calloc(1, sizeof(*gobj), DRM_MEM_DRIVER);
+ if (!gobj) return -ENOMEM;
+
+ obj->driver_private = gobj;
+ gobj->obj = obj;
+
+ return 0;
+}
+
+
+void glamodrm_gem_free_object(struct drm_gem_object *obj)
+{
+ struct drm_glamo_gem_object *gobj;
+ struct drm_map_list *list;
+ struct drm_device *dev;
+ struct drm_gem_mm *mm;
+ struct drm_map *map;
+
+ dev = obj->dev;
+ mm = dev->mm_private;
+ gobj = obj->driver_private;
+
+ /* Free the VRAM */
+ if ( gobj->block != NULL ) {
+ drm_mm_put_block(gobj->block);
+ }
+
+ /* Release mappings */
+ list = &obj->map_list;
+ drm_ht_remove_item(&mm->offset_hash, &list->hash);
+ if (list->file_offset_node) {
+ drm_mm_put_block(list->file_offset_node);
+ list->file_offset_node = NULL;
+ }
+ map = list->map;
+ if (map) {
+ drm_free(map, sizeof(*map), DRM_MEM_DRIVER);
+ list->map = NULL;
+ }
+
+ /* Free the private structure */
+ drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
+}
+
+
+/* Memory management initialisation */
+int glamo_buffer_init(struct glamodrm_handle *gdrm)
+{
+ gdrm->mmgr = drm_calloc(1, sizeof(struct drm_mm), DRM_MEM_DRIVER);
+ drm_mm_init(gdrm->mmgr, 0, gdrm->vram_size);
+
+ /* Reserve a scratch buffer. We do this outside the protections
+ * of the other GEM code. To do this safely, the allocation must
+ * be a multiple of PAGE_SIZE. */
+ gdrm->scratch = drm_mm_search_free(gdrm->mmgr, PAGE_SIZE, 4, 1);
+ if ( gdrm->scratch ) {
+ gdrm->scratch = drm_mm_get_block(gdrm->scratch, PAGE_SIZE, 4);
+ }
+ if ( !gdrm->scratch ) {
+ printk(KERN_WARNING "[glamo-drm] Couldn't allocate"
+ " scratch buffer!\n");
+ }
+
+ return 0;
+}
+
+
+/* Memory management finalisation */
+int glamo_buffer_final(struct glamodrm_handle *gdrm)
+{
+ drm_mm_takedown(gdrm->mmgr);
+ drm_free(gdrm->mmgr , 1, DRM_MEM_DRIVER);
+ return 0;
+}
diff --git a/drivers/mfd/glamo/glamo-buffer.h b/drivers/mfd/glamo/glamo-buffer.h
new file mode 100644
index 00000000000..41f18fd7989
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-buffer.h
@@ -0,0 +1,60 @@
+/*
+ * SMedia Glamo 336x/337x memory management
+ *
+ * Copyright (c) 2009 Thomas White <taw@bitwiz.org.uk>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __GLAMO_BUFFER_H
+#define __GLAMO_BUFFER_H
+
+#include <drm/drmP.h>
+
+#include "glamo-drm-private.h"
+
+extern int glamo_buffer_init(struct glamodrm_handle *gdrm);
+extern int glamo_buffer_final(struct glamodrm_handle *gdrm);
+
+extern int glamodrm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
+
+extern int glamodrm_gem_init_object(struct drm_gem_object *obj);
+
+extern void glamodrm_gem_free_object(struct drm_gem_object *obj);
+
+extern struct drm_gem_object *glamo_gem_object_alloc(struct drm_device *dev,
+ int size, int alignment);
+
+extern int glamo_ioctl_gem_create(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
+
+extern int glamo_ioctl_gem_mmap(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
+
+extern int glamo_ioctl_gem_pin(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
+
+extern int glamo_ioctl_gem_unpin(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
+
+extern int glamo_ioctl_gem_pread(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
+
+extern int glamo_ioctl_gem_pwrite(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
+
+#endif /* __GLAMO_BUFFER_H */
diff --git a/drivers/mfd/glamo/glamo-cmdq.c b/drivers/mfd/glamo/glamo-cmdq.c
new file mode 100644
index 00000000000..f3dcc83b00f
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-cmdq.c
@@ -0,0 +1,524 @@
+/*
+ * SMedia Glamo 336x/337x command queue handling
+ *
+ * Copyright (C) 2008-2009 Thomas White <taw@bitwiz.org.uk>
+ * Copyright (C) 2009 Andreas Pokorny <andreas.pokorny@gmail.com>
+ * Based on xf86-video-glamo (see below for details)
+ *
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Command queue handling functions based on those from xf86-video-glamo, to
+ * which the following licence applies:
+ *
+ * Copyright 2007 OpenMoko, Inc.
+ * Copyright © 2009 Lars-Peter Clausen <lars@metafoo.de>
+ *
+ * This driver is based on Xati,
+ * Copyright 2004 Eric Anholt
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission. The copyright holders make no representations
+ * about the suitability of this software for any purpose. It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+
+
+#include <drm/drmP.h>
+#include <drm/glamo_drm.h>
+
+#include "glamo-core.h"
+#include "glamo-drm-private.h"
+#include "glamo-regs.h"
+
+
+static inline void reg_write(struct glamodrm_handle *gdrm,
+ u_int16_t reg, u_int16_t val)
+{
+ iowrite16(val, gdrm->reg_base + reg);
+}
+
+
+static inline u16 reg_read(struct glamodrm_handle *gdrm, u_int16_t reg)
+{
+ return ioread16(gdrm->reg_base + reg);
+}
+
+
+static u32 glamo_get_read(struct glamodrm_handle *gdrm)
+{
+ /* we could turn off clock here */
+ u32 ring_read = reg_read(gdrm, GLAMO_REG_CMDQ_READ_ADDRL);
+ ring_read |= (reg_read(gdrm, GLAMO_REG_CMDQ_READ_ADDRH) & 0x7) << 16;
+
+ return ring_read;
+}
+
+
+static u32 glamo_get_write(struct glamodrm_handle *gdrm)
+{
+ u32 ring_write = reg_read(gdrm, GLAMO_REG_CMDQ_WRITE_ADDRL);
+ ring_write |= (reg_read(gdrm, GLAMO_REG_CMDQ_WRITE_ADDRH) & 0x7) << 16;
+
+ return ring_write;
+}
+
+
+/* Add commands to the ring buffer */
+int glamo_add_to_ring(struct glamodrm_handle *gdrm, u16 *addr,
+ unsigned int count)
+{
+ size_t ring_write, ring_read;
+ size_t new_ring_write;
+
+ if ( count >= GLAMO_CMDQ_SIZE ) {
+ printk(KERN_WARNING "[glamo-drm] CmdQ submission too large\n");
+ return -EINVAL;
+ }
+
+ down(&gdrm->add_to_ring);
+
+ ring_write = glamo_get_write(gdrm);
+
+ /* Calculate where we'll end up */
+ new_ring_write = (ring_write + count) % GLAMO_CMDQ_SIZE;
+
+ /* Wait until there is enough space to queue the cmd buffer */
+ if (new_ring_write > ring_write) {
+ /* Loop while the read pointer is between the old and new
+ * positions */
+ do {
+ ring_read = glamo_get_read(gdrm);
+ } while (ring_read > ring_write && ring_read < new_ring_write);
+ } else {
+ /* Same, but kind of inside-out */
+ do {
+ ring_read = glamo_get_read(gdrm);
+ } while (ring_read > ring_write || ring_read < new_ring_write);
+ }
+
+ /* Are we about to wrap around? */
+ if (ring_write >= new_ring_write) {
+
+ u32 rest_size;
+
+ /* Wrap around */
+ rest_size = GLAMO_CMDQ_SIZE - ring_write; /* Space left */
+
+ /* Write from current position to end */
+ memcpy_toio(gdrm->cmdq_base+ring_write, addr, rest_size);
+
+ /* Write from start */
+ memcpy_toio(gdrm->cmdq_base, addr+(rest_size>>1),
+ count - rest_size);
+
+ /* ring_write being 0 will result in a deadlock because the
+ * cmdq read will never stop. To avoid such an behaviour insert
+ * an empty instruction. */
+ if (new_ring_write == 0) {
+ iowrite16(0x0000, gdrm->cmdq_base);
+ iowrite16(0x0000, gdrm->cmdq_base + 2);
+ new_ring_write = 4;
+ }
+
+ } else {
+
+ memcpy_toio(gdrm->cmdq_base+ring_write, addr, count);
+
+ }
+
+ reg_write(gdrm, GLAMO_REG_CMDQ_WRITE_ADDRH,
+ (new_ring_write >> 16) & 0x7f);
+ reg_write(gdrm, GLAMO_REG_CMDQ_WRITE_ADDRL,
+ new_ring_write & 0xffff);
+
+ if ( !(reg_read(gdrm, GLAMO_REG_CMDQ_STATUS) & 1<<3) ) {
+ printk(KERN_ERR "[glamo-drm] CmdQ decode failure.\n");
+ }
+
+ up(&gdrm->add_to_ring);
+
+ return 0;
+}
+
+
+/* Return true for a legal sequence of commands, otherwise false */
+static int glamo_sanitize_buffer(u16 *cmds, unsigned int count)
+{
+ /* XXX FIXME TODO: Implementation... */
+ return 1;
+}
+
+
+/* Substitute the real addresses in VRAM for any required buffer objects */
+static int glamo_do_relocation(struct glamodrm_handle *gdrm,
+ drm_glamo_cmd_buffer_t *cbuf, u16 *cmds,
+ struct drm_device *dev,
+ struct drm_file *file_priv)
+{
+ u32 *handles;
+ int *offsets;
+ int nobjs = cbuf->nobjs;
+ int i;
+
+ if ( nobjs > 32 ) return -EINVAL; /* Get real... */
+
+ handles = drm_alloc(nobjs*sizeof(u32), DRM_MEM_DRIVER);
+ if ( handles == NULL ) return -1;
+ if ( copy_from_user(handles, cbuf->objs, nobjs*sizeof(u32)) )
+ return -1;
+
+ offsets = drm_alloc(nobjs*sizeof(int), DRM_MEM_DRIVER);
+ if ( offsets == NULL ) return -1;
+ if ( copy_from_user(offsets, cbuf->obj_pos, nobjs*sizeof(int)) )
+ return -1;
+
+ for ( i=0; i<nobjs; i++ ) {
+
+ u32 handle = handles[i];
+ int offset = offsets[i];
+ struct drm_gem_object *obj;
+ struct drm_glamo_gem_object *gobj;
+ u32 addr;
+ u16 addr_low, addr_high;
+
+ if ( offset > cbuf->bufsz ) {
+ printk(KERN_WARNING "[glamo-drm] Offset out of range"
+ " for this relocation!\n");
+ goto fail;
+ }
+
+ obj = drm_gem_object_lookup(dev, file_priv, handle);
+ if ( obj == NULL ) return -1;
+
+ /* Unref the object now, or it'll never get freed.
+ * This should really happen after the GPU has finished
+ * the commands which are about to be submitted. */
+ drm_gem_object_unreference(obj);
+
+ gobj = obj->driver_private;
+ if ( gobj == NULL ) {
+ printk(KERN_WARNING "[glamo-drm] This object has no"
+ " private data!\n");
+ goto fail;
+ }
+
+ addr = GLAMO_OFFSET_FB + gobj->block->start;
+ addr_low = addr & 0xffff;
+ addr_high = (addr >> 16) & 0x7f;
+
+ /* FIXME: Should really check that the register is a
+ * valid one for this relocation. */
+
+ *(cmds+(offset/2)+1) = addr_low;
+ *(cmds+(offset/2)+3) = addr_high;
+
+ }
+
+ drm_free(handles, 1, DRM_MEM_DRIVER);
+ drm_free(offsets, 1, DRM_MEM_DRIVER);
+ return 0;
+
+fail:
+ drm_free(handles, 1, DRM_MEM_DRIVER);
+ drm_free(offsets, 1, DRM_MEM_DRIVER);
+ return -1;
+}
+
+
+/* This is DRM_IOCTL_GLAMO_CMDBUF */
+int glamo_ioctl_cmdbuf(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ int ret = 0;
+ struct glamodrm_handle *gdrm;
+ unsigned int count;
+ drm_glamo_cmd_buffer_t *cbuf = data;
+ u16 *cmds;
+
+ gdrm = dev->dev_private;
+
+ count = cbuf->bufsz;
+
+ if ( count > PAGE_SIZE ) return -EINVAL;
+
+ cmds = drm_alloc(count, DRM_MEM_DRIVER);
+ if ( cmds == NULL ) return -ENOMEM;
+ if ( copy_from_user(cmds, cbuf->buf, count) ) {
+ printk(KERN_WARNING "[glamo-drm] copy from user failed\n");
+ ret = -EINVAL;
+ goto cleanup;
+ }
+
+ /* Check the buffer isn't going to tell Glamo to enact naughtiness */
+ if ( !glamo_sanitize_buffer(cmds, count) ) {
+ printk(KERN_WARNING "[glamo-drm] sanitize buffer failed\n");
+ ret = -EINVAL;
+ goto cleanup;
+ }
+
+ /* Perform relocation, if necessary */
+ if ( cbuf->nobjs ) {
+ if ( glamo_do_relocation(gdrm, cbuf, cmds, dev, file_priv) )
+ {
+ printk(KERN_WARNING "[glamo-drm] Relocation failed\n");
+ ret = -EINVAL;
+ goto cleanup;
+ }
+ }
+
+ glamo_add_to_ring(gdrm, cmds, count);
+
+cleanup:
+ drm_free(cmds, 1, DRM_MEM_DRIVER);
+
+ return ret;
+}
+
+
+/* Return true for a legal sequence of commands, otherwise false */
+static int glamo_sanitize_burst(u16 base, u16 *cmds, unsigned int count)
+{
+ /* XXX FIXME TODO: Implementation... */
+ return 1;
+}
+
+
+static int glamo_relocate_burst(struct glamodrm_handle *gdrm,
+ drm_glamo_cmd_burst_t *cbuf, u16 *data,
+ struct drm_device *dev,
+ struct drm_file *file_priv)
+{
+ u32 *handles;
+ int *offsets;
+ int nobjs = cbuf->nobjs;
+ int i;
+
+ if ( nobjs > 32 ) return -EINVAL; /* Get real... */
+
+ handles = drm_alloc(nobjs*sizeof(u32), DRM_MEM_DRIVER);
+ if ( handles == NULL ) return -1;
+ if ( copy_from_user(handles, cbuf->objs, nobjs*sizeof(u32)) )
+ return -1;
+
+ offsets = drm_alloc(nobjs*sizeof(int), DRM_MEM_DRIVER);
+ if ( offsets == NULL ) return -1;
+ if ( copy_from_user(offsets, cbuf->obj_pos, nobjs*sizeof(int)) )
+ return -1;
+
+ for ( i=0; i<nobjs; i++ ) {
+
+ u32 handle = handles[i];
+ int offset = offsets[i];
+ struct drm_gem_object *obj;
+ struct drm_glamo_gem_object *gobj;
+ u32 addr;
+ u16 addr_low, addr_high;
+
+ if ( offset > cbuf->bufsz ) {
+ printk(KERN_WARNING "[glamo-drm] Offset out of range"
+ " for this relocation!\n");
+ goto fail;
+ }
+
+ obj = drm_gem_object_lookup(dev, file_priv, handle);
+ if ( obj == NULL ) return -1;
+
+ /* Unref the object now, or it'll never get freed.
+ * FIXME: This should really happen after the GPU has
+ * finished executing these commands. */
+ drm_gem_object_unreference(obj);
+
+ gobj = obj->driver_private;
+ if ( gobj == NULL ) {
+ printk(KERN_WARNING "[glamo-drm] This object has no"
+ " private data!\n");
+ goto fail;
+ }
+
+ addr = GLAMO_OFFSET_FB + gobj->block->start;
+ addr_low = addr & 0xffff;
+ addr_high = (addr >> 16) & 0x7f;
+
+ /* FIXME: Should really check that the register is a
+ * valid one for this relocation. */
+
+ *(data+(offset/2)+0) = addr_low;
+ *(data+(offset/2)+1) = addr_high;
+
+ }
+
+ drm_free(handles, 1, DRM_MEM_DRIVER);
+ drm_free(offsets, 1, DRM_MEM_DRIVER);
+ return 0;
+
+fail:
+ drm_free(handles, 1, DRM_MEM_DRIVER);
+ drm_free(offsets, 1, DRM_MEM_DRIVER);
+ return -1;
+}
+
+
+/* This is DRM_IOCTL_GLAMO_CMDBURST */
+int glamo_ioctl_cmdburst(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ int ret = 0;
+ struct glamodrm_handle *gdrm;
+ drm_glamo_cmd_burst_t *cbuf = data;
+ u16 *burst;
+ size_t burst_size;
+ size_t data_size;
+
+ gdrm = dev->dev_private;
+
+ data_size = cbuf->bufsz;
+ burst_size = data_size + 4; /* Add space for header */
+ if ( data_size % 4 ) burst_size += 2;
+ if ( burst_size > PAGE_SIZE ) return -EINVAL;
+ if ( burst_size % 4 ) return -EINVAL;
+
+ burst = drm_alloc(burst_size, DRM_MEM_DRIVER);
+ if ( burst == NULL ) return -ENOMEM;
+
+ /* Get data from userspace */
+ if ( copy_from_user(burst+2, cbuf->data, cbuf->bufsz) ) {
+ printk(KERN_WARNING "[glamo-drm] copy from user failed\n");
+ ret = -EINVAL;
+ goto cleanup;
+ }
+
+ /* Sanitise */
+ if ( !glamo_sanitize_burst(cbuf->base, burst+2, cbuf->bufsz) ) {
+ printk(KERN_WARNING "[glamo-drm] sanitize buffer failed\n");
+ ret = -EINVAL;
+ goto cleanup;
+ }
+
+ /* Relocate */
+ if ( cbuf->nobjs ) {
+ if ( glamo_relocate_burst(gdrm, cbuf, burst+2, dev, file_priv) )
+ {
+ printk(KERN_WARNING "[glamo-drm] Relocation failed\n");
+ ret = -EINVAL;
+ goto cleanup;
+ }
+ }
+
+ /* Add burst header */
+ burst[0] = 1<<15 | cbuf->base;
+ burst[1] = data_size / 2; /* -> 2-byte words */
+
+ /* Zero-pad if necessary */
+ if ( burst[1] & 0x01 ) {
+ burst[(burst_size/2)-1] = 0x0000;
+ }
+
+ /* Add to command queue */
+ glamo_add_to_ring(gdrm, burst, burst_size);
+
+cleanup:
+ drm_free(burst, 1, DRM_MEM_DRIVER);
+
+ return ret;
+}
+
+
+int glamo_cmdq_init(struct glamodrm_handle *gdrm)
+{
+ unsigned int i;
+
+ init_MUTEX(&gdrm->add_to_ring);
+
+ /* Enable 2D and 3D */
+ glamo_engine_enable(gdrm->glamo_core, GLAMO_ENGINE_2D);
+ glamo_engine_reset(gdrm->glamo_core, GLAMO_ENGINE_2D);
+
+ /* Start by zeroing the command queue memory */
+ for ( i=0; i<GLAMO_CMDQ_SIZE; i+=2 ) {
+ iowrite16(0x0000, gdrm->cmdq_base+i);
+ }
+
+ glamo_engine_enable(gdrm->glamo_core, GLAMO_ENGINE_CMDQ);
+ glamo_engine_reset(gdrm->glamo_core, GLAMO_ENGINE_CMDQ);
+
+ /* Set up command queue location */
+ reg_write(gdrm, GLAMO_REG_CMDQ_BASE_ADDRL,
+ GLAMO_OFFSET_CMDQ & 0xffff);
+ reg_write(gdrm, GLAMO_REG_CMDQ_BASE_ADDRH,
+ (GLAMO_OFFSET_CMDQ >> 16) & 0x7f);
+
+ /* Length of command queue in 1k blocks, minus one */
+ reg_write(gdrm, GLAMO_REG_CMDQ_LEN, (GLAMO_CMDQ_SIZE >> 10)-1);
+ reg_write(gdrm, GLAMO_REG_CMDQ_WRITE_ADDRH, 0);
+ reg_write(gdrm, GLAMO_REG_CMDQ_WRITE_ADDRL, 0);
+ reg_write(gdrm, GLAMO_REG_CMDQ_CONTROL,
+ 1 << 12 | /* Turbo flip (?) */
+ 5 << 8 | /* no interrupt */
+ 8 << 4); /* HQ threshold */
+
+ return 0;
+}
+
+
+int glamo_cmdq_shutdown(struct glamodrm_handle *gdrm)
+{
+ return 0;
+}
+
+
+void glamo_cmdq_suspend(struct glamodrm_handle *gdrm)
+{
+ /* Placeholder... */
+}
+
+
+void glamo_cmdq_resume(struct glamodrm_handle *gdrm)
+{
+ glamo_cmdq_init(gdrm);
+}
+
+
+/* Initialise an object's contents to zero.
+ * This is in glamo-cmdq.c in the hope that we can accelerate it later. */
+void glamo_cmdq_blank(struct glamodrm_handle *gdrm, struct drm_gem_object *obj)
+{
+ char __iomem *cookie;
+ struct drm_glamo_gem_object *gobj;
+ int i;
+
+ gobj = obj->driver_private;
+
+ cookie = ioremap(gdrm->vram->start + gobj->block->start, obj->size);
+ for ( i=0; i<obj->size; i+=2 ) {
+ iowrite16(0, cookie+i);
+ }
+ iounmap(cookie);
+}
diff --git a/drivers/mfd/glamo/glamo-cmdq.h b/drivers/mfd/glamo/glamo-cmdq.h
new file mode 100644
index 00000000000..510d1954c64
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-cmdq.h
@@ -0,0 +1,49 @@
+/* Smedia Glamo 336x/337x command queue handling
+ *
+ * Copyright (c) 2008-2009 Thomas White <taw@bitwiz.org.uk>
+ * Copyright (c) 2009 Andreas Pokorny <andreas.pokorny@gmail.com>
+ * Based on xf86-video-glamo
+ * Copyright 2007 OpenMoko, Inc.
+ * Copyright © 2009 Lars-Peter Clausen <lars@metafoo.de>
+ *
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __GLAMO_CMDQ_H
+#define __GLAMO_CMDQ_H
+
+#include <drm/drmP.h>
+
+#include "glamo-drm-private.h"
+
+extern int glamo_ioctl_cmdbuf(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
+extern int glamo_ioctl_cmdburst(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
+extern void glamo_cmdq_blank(struct glamodrm_handle *gdrm,
+ struct drm_gem_object *obj);
+
+extern int glamo_cmdq_init(struct glamodrm_handle *gdrm);
+extern int glamo_cmdq_shutdown(struct glamodrm_handle *gdrm);
+extern void glamo_cmdq_suspend(struct glamodrm_handle *gdrm);
+extern void glamo_cmdq_resume(struct glamodrm_handle *gdrm);
+
+extern int glamo_add_to_ring(struct glamodrm_handle *gdrm, u16 *addr,
+ unsigned int count);
+
+#endif /* __GLAMO_CMDQ_H */
diff --git a/drivers/mfd/glamo/glamo-core.c b/drivers/mfd/glamo/glamo-core.c
index 28dc1f309ac..3dcb3589084 100644
--- a/drivers/mfd/glamo/glamo-core.c
+++ b/drivers/mfd/glamo/glamo-core.c
@@ -175,119 +175,47 @@ static inline void glamo_vmem_read(struct glamo_core *glamo, u_int16_t *buf,
/***********************************************************************
* resources of sibling devices
***********************************************************************/
-
-#if 0
-static struct resource glamo_core_resources[] = {
+static struct resource glamo_graphics_resources[] = {
{
- .start = GLAMO_REGOFS_GENERIC,
- .end = GLAMO_REGOFS_GENERIC + 0x400,
- .flags = IORESOURCE_MEM,
+ .name = "glamo-cmdq-regs",
+ .start = GLAMO_REGOFS_CMDQUEUE,
+ .end = GLAMO_REGOFS_RISC - 1,
+ .flags = IORESOURCE_MEM,
}, {
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device glamo_core_dev = {
- .name = "glamo-core",
- .resource = &glamo_core_resources,
- .num_resources = ARRAY_SIZE(glamo_core_resources),
-};
-#endif
-
-static struct resource glamo_jpeg_resources[] = {
- {
- .start = GLAMO_REGOFS_JPEG,
- .end = GLAMO_REGOFS_MPEG - 1,
- .flags = IORESOURCE_MEM,
+ .name = "glamo-command-queue",
+ .start = GLAMO_MEM_BASE + GLAMO_OFFSET_CMDQ,
+ .end = GLAMO_MEM_BASE + GLAMO_OFFSET_CMDQ +
+ GLAMO_CMDQ_SIZE - 1,
+ .flags = IORESOURCE_MEM,
}, {
- .start = IRQ_GLAMO_JPEG,
- .end = IRQ_GLAMO_JPEG,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device glamo_jpeg_dev = {
- .name = "glamo-jpeg",
- .resource = glamo_jpeg_resources,
- .num_resources = ARRAY_SIZE(glamo_jpeg_resources),
-};
-
-static struct resource glamo_mpeg_resources[] = {
- {
- .start = GLAMO_REGOFS_MPEG,
- .end = GLAMO_REGOFS_LCD - 1,
+ .name = "glamo-fb-mem",
+ .start = GLAMO_MEM_BASE + GLAMO_OFFSET_FB,
+ .end = GLAMO_MEM_BASE + GLAMO_OFFSET_FB +
+ GLAMO_FB_SIZE - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = IRQ_GLAMO_MPEG,
- .end = IRQ_GLAMO_MPEG,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device glamo_mpeg_dev = {
- .name = "glamo-mpeg",
- .resource = glamo_mpeg_resources,
- .num_resources = ARRAY_SIZE(glamo_mpeg_resources),
-};
-
-static struct resource glamo_2d_resources[] = {
- {
- .start = GLAMO_REGOFS_2D,
- .end = GLAMO_REGOFS_3D - 1,
+ .name = "glamo-fb-regs",
+ .start = GLAMO_REGOFS_LCD,
+ .end = GLAMO_REGOFS_MMC - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = IRQ_GLAMO_2D,
- .end = IRQ_GLAMO_2D,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device glamo_2d_dev = {
- .name = "glamo-2d",
- .resource = glamo_2d_resources,
- .num_resources = ARRAY_SIZE(glamo_2d_resources),
-};
-
-static struct resource glamo_3d_resources[] = {
- {
- .start = GLAMO_REGOFS_3D,
- .end = GLAMO_REGOFS_END - 1,
- .flags = IORESOURCE_MEM,
- },
+ .name = "glamo-2d-regs",
+ .start = GLAMO_REGOFS_2D,
+ .end = GLAMO_REGOFS_3D- 1,
+ .flags = IORESOURCE_MEM,
+ }
};
-static struct platform_device glamo_3d_dev = {
- .name = "glamo-3d",
- .resource = glamo_3d_resources,
- .num_resources = ARRAY_SIZE(glamo_3d_resources),
+static struct platform_device glamo_graphics_dev = {
+ .name = "glamo-fb",
+ .resource = glamo_graphics_resources,
+ .num_resources = ARRAY_SIZE(glamo_graphics_resources),
};
static struct platform_device glamo_spigpio_dev = {
.name = "glamo-spi-gpio",
};
-static struct resource glamo_fb_resources[] = {
- /* FIXME: those need to be incremented by parent base */
- {
- .name = "glamo-fb-regs",
- .start = GLAMO_REGOFS_LCD,
- .end = GLAMO_REGOFS_MMC - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "glamo-fb-mem",
- .start = GLAMO_OFFSET_FB,
- .end = GLAMO_OFFSET_FB + GLAMO_FB_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device glamo_fb_dev = {
- .name = "glamo-fb",
- .resource = glamo_fb_resources,
- .num_resources = ARRAY_SIZE(glamo_fb_resources),
-};
static struct resource glamo_mmc_resources[] = {
{
@@ -300,9 +228,9 @@ static struct resource glamo_mmc_resources[] = {
.end = IRQ_GLAMO_MMC,
.flags = IORESOURCE_IRQ,
}, { /* our data buffer for MMC transfers */
- .start = GLAMO_OFFSET_FB + GLAMO_FB_SIZE,
- .end = GLAMO_OFFSET_FB + GLAMO_FB_SIZE +
- GLAMO_MMC_BUFFER_SIZE - 1,
+ .start = GLAMO_MEM_BASE + GLAMO_OFFSET_MMC,
+ .end = GLAMO_MEM_BASE + GLAMO_OFFSET_MMC +
+ GLAMO_MMC_BUFFER_SIZE - 1,
.flags = IORESOURCE_MEM
},
};
@@ -426,6 +354,24 @@ static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
}
+void glamo_clear_irq(struct glamo_core *glamo, unsigned int irq)
+{
+ /* set interrupt source */
+ __reg_write(glamo, GLAMO_REG_IRQ_CLEAR, irq);
+}
+
+
+void glamo_enable_irq(struct glamo_core *glamo, unsigned int irq)
+{
+ u_int16_t tmp;
+
+ /* set bit in enable register */
+ tmp = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE);
+ tmp |= irq;
+ __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, tmp);
+}
+
+
static ssize_t regs_write(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
@@ -538,6 +484,8 @@ int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
__reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
GLAMO_HOSTBUS2_MMIO_EN_2D,
GLAMO_HOSTBUS2_MMIO_EN_2D);
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
+ GLAMO_CLOCK_GEN51_EN_DIV_GCLK, 0xffff);
break;
case GLAMO_ENGINE_CMDQ:
__reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
@@ -545,6 +493,8 @@ int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
__reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
GLAMO_HOSTBUS2_MMIO_EN_CQ,
GLAMO_HOSTBUS2_MMIO_EN_CQ);
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
+ GLAMO_CLOCK_GEN51_EN_DIV_MCLK, 0xffff);
break;
/* FIXME: Implementation */
default:
@@ -675,6 +625,11 @@ struct glamo_script reset_regs[] = {
[GLAMO_ENGINE_JPEG] = {
GLAMO_REG_CLOCK_JPEG, GLAMO_CLOCK_JPEG_RESET
},
+ /* The following is defined as "Reset command queue", nothing to do
+ * with the 2D engine. */
+ [GLAMO_ENGINE_CMDQ] = {
+ GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_CQ_RESET
+ },
};
void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine)
@@ -983,7 +938,7 @@ static void glamo_power(struct glamo_core *glamo,
{
int n;
unsigned long flags;
-
+
spin_lock_irqsave(&glamo->lock, flags);
dev_info(&glamo->pdev->dev, "***** glamo_power -> %d\n", new_state);
@@ -1308,52 +1263,33 @@ static int __init glamo_probe(struct platform_device *pdev)
glamo->pdata->glamo_irq_is_wired;
/* start creating the siblings */
-
- glamo_2d_dev.dev.parent = &pdev->dev;
- mangle_mem_resources(glamo_2d_dev.resource,
- glamo_2d_dev.num_resources, glamo->mem);
- platform_device_register(&glamo_2d_dev);
-
- glamo_3d_dev.dev.parent = &pdev->dev;
- mangle_mem_resources(glamo_3d_dev.resource,
- glamo_3d_dev.num_resources, glamo->mem);
- platform_device_register(&glamo_3d_dev);
-
- glamo_jpeg_dev.dev.parent = &pdev->dev;
- mangle_mem_resources(glamo_jpeg_dev.resource,
- glamo_jpeg_dev.num_resources, glamo->mem);
- platform_device_register(&glamo_jpeg_dev);
-
- glamo_mpeg_dev.dev.parent = &pdev->dev;
- mangle_mem_resources(glamo_mpeg_dev.resource,
- glamo_mpeg_dev.num_resources, glamo->mem);
- platform_device_register(&glamo_mpeg_dev);
-
glamo->pdata->glamo = glamo;
- glamo_fb_dev.dev.parent = &pdev->dev;
- glamo_fb_dev.dev.platform_data = glamo->pdata;
- mangle_mem_resources(glamo_fb_dev.resource,
- glamo_fb_dev.num_resources, glamo->mem);
- platform_device_register(&glamo_fb_dev);
+ /* Command queue device (for DRM) */
+ glamo_graphics_dev.dev.parent = &pdev->dev;
+ glamo_graphics_dev.dev.platform_data = glamo->pdata;
+ mangle_mem_resources(glamo_graphics_dev.resource,
+ glamo_graphics_dev.num_resources, glamo->mem);
+ platform_device_register(&glamo_graphics_dev);
+
+ /* GPIO */
glamo->pdata->spigpio_info->glamo = glamo;
glamo_spigpio_dev.dev.parent = &pdev->dev;
glamo_spigpio_dev.dev.platform_data = glamo->pdata->spigpio_info;
platform_device_register(&glamo_spigpio_dev);
+ /* MMC */
glamo_mmc_dev = glamo->pdata->mmc_dev;
glamo_mmc_dev->name = "glamo-mci";
glamo_mmc_dev->dev.parent = &pdev->dev;
glamo_mmc_dev->resource = glamo_mmc_resources;
- glamo_mmc_dev->num_resources = ARRAY_SIZE(glamo_mmc_resources);
-
- /* we need it later to give to the engine enable and disable */
+ glamo_mmc_dev->num_resources = ARRAY_SIZE(glamo_mmc_resources);
glamo_mci_def_pdata.pglamo = glamo;
mangle_mem_resources(glamo_mmc_dev->resource,
glamo_mmc_dev->num_resources, glamo->mem);
platform_device_register(glamo_mmc_dev);
- /* only request the generic, hostbus and memory controller MMIO */
+ /* Only request the generic, hostbus and memory controller MMIO */
glamo->mem = request_mem_region(glamo->mem->start,
GLAMO_REGOFS_VIDCAP, "glamo-core");
if (!glamo->mem) {
@@ -1395,8 +1331,10 @@ static int glamo_remove(struct platform_device *pdev)
}
platform_set_drvdata(pdev, NULL);
- platform_device_unregister(&glamo_fb_dev);
platform_device_unregister(glamo->pdata->mmc_dev);
+ /* FIXME: Don't we need to unregister these as well?
+ * platform_device_unregister(glamo->pdata->graphics_dev);
+ * platform_device_unregister(glamo->pdata->gpio_dev); */
iounmap(glamo->base);
release_mem_region(glamo->mem->start, GLAMO_REGOFS_VIDCAP);
glamo_handle = NULL;
diff --git a/drivers/mfd/glamo/glamo-core.h b/drivers/mfd/glamo/glamo-core.h
index 8e09564bc3f..1fe16df2642 100644
--- a/drivers/mfd/glamo/glamo-core.h
+++ b/drivers/mfd/glamo/glamo-core.h
@@ -3,18 +3,34 @@
#include <asm/system.h>
-/* for the time being, we put the on-screen framebuffer into the lowest
- * VRAM space. This should make the code easily compatible with the various
- * 2MB/4MB/8MB variants of the Smedia chips */
-#define GLAMO_OFFSET_VRAM 0x800000
-#define GLAMO_OFFSET_FB (GLAMO_OFFSET_VRAM)
-
/* we only allocate the minimum possible size for the framebuffer to make
* sure we have sufficient memory for other functions of the chip */
-//#define GLAMO_FB_SIZE (640*480*4) /* == 0x12c000 */
+/* FIXME: this should be autodetected */
#define GLAMO_INTERNAL_RAM_SIZE 0x800000
-#define GLAMO_MMC_BUFFER_SIZE (64 * 1024)
-#define GLAMO_FB_SIZE (GLAMO_INTERNAL_RAM_SIZE - GLAMO_MMC_BUFFER_SIZE)
+/* Arbitrarily determined amount for the hardware cursor */
+#define GLAMO_CURSOR_SIZE (4096)
+#define GLAMO_MMC_BUFFER_SIZE (64 * 1024) /* 64k MMC buffer */
+#define GLAMO_CMDQ_SIZE (128 * 1024) /* 128k ring buffer */
+/* Remaining memory will be used for 2D and 3D graphics */
+#define GLAMO_FB_SIZE (GLAMO_INTERNAL_RAM_SIZE \
+ - GLAMO_CURSOR_SIZE \
+ - GLAMO_MMC_BUFFER_SIZE \
+ - GLAMO_CMDQ_SIZE)
+/* A 640x480, 16bpp, double-buffered framebuffer */
+#if (GLAMO_FB_SIZE < (640 * 480 * 4)) /* == 0x12c000 */
+#error Not enough Glamo VRAM for framebuffer!
+#endif
+
+/* for the time being, we put the on-screen framebuffer into the lowest
+ * VRAM space. This should make the code easily compatible with the various
+ * 2MB/4MB/8MB variants of the Smedia chips
+ * glamo-fb.c assumes FB comes first, followed by cursor, so DON'T MOVE THEM
+ * (see glamo_regs[] in glamo-fb.c for more information) */
+#define GLAMO_MEM_BASE (0x800000)
+#define GLAMO_OFFSET_FB (0x000000)
+#define GLAMO_OFFSET_CURSOR (GLAMO_OFFSET_FB + GLAMO_FB_SIZE)
+#define GLAMO_OFFSET_MMC (GLAMO_OFFSET_CURSOR + GLAMO_CURSOR_SIZE)
+#define GLAMO_OFFSET_CMDQ (GLAMO_OFFSET_MMC + GLAMO_MMC_BUFFER_SIZE)
struct glamo_core {
int irq;
@@ -60,7 +76,8 @@ enum glamo_engine {
GLAMO_ENGINE_RISC1,
GLAMO_ENGINE_SPI,
#endif
- __NUM_GLAMO_ENGINES
+ __NUM_GLAMO_ENGINES,
+ GLAMO_ENGINE_ALL
};
struct glamo_mci_pdata {
@@ -83,6 +100,9 @@ void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine);
int glamo_engine_reclock(struct glamo_core *glamo,
enum glamo_engine engine, int ps);
+extern void glamo_clear_irq(struct glamo_core *glamo, unsigned int irq);
+extern void glamo_enable_irq(struct glamo_core *glamo, unsigned int irq);
+
void glamo_engine_clkreg_set(struct glamo_core *glamo,
enum glamo_engine engine,
u_int16_t mask, u_int16_t val);
diff --git a/drivers/mfd/glamo/glamo-display.c b/drivers/mfd/glamo/glamo-display.c
new file mode 100644
index 00000000000..702533f9f10
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-display.c
@@ -0,0 +1,927 @@
+/*
+ * SMedia Glamo 336x/337x display
+ *
+ * Copyright (C) 2008-2009 Thomas White <taw@bitwiz.org.uk>
+ *
+ * Based on glamo-fb.c (C) 2007-2008 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * Based on intel_display.c and intel_crt.c from drivers/gpu/drm/i915
+ * to which the following licence applies:
+ *
+ * Copyright © 2006-2007 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Eric Anholt <eric@anholt.net>
+ *
+ */
+
+#define DEBUG 1
+
+#include <drm/drmP.h>
+#include <drm/glamo_drm.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_crtc.h>
+
+#include "glamo-core.h"
+#include "glamo-drm-private.h"
+#include "glamo-regs.h"
+#include "glamo-kms-fb.h"
+#include <linux/glamofb.h>
+
+
+#define GLAMO_LCD_WIDTH_MASK 0x03FF
+#define GLAMO_LCD_HEIGHT_MASK 0x03FF
+#define GLAMO_LCD_PITCH_MASK 0x07FE
+#define GLAMO_LCD_HV_TOTAL_MASK 0x03FF
+#define GLAMO_LCD_HV_RETR_START_MASK 0x03FF
+#define GLAMO_LCD_HV_RETR_END_MASK 0x03FF
+#define GLAMO_LCD_HV_RETR_DISP_START_MASK 0x03FF
+#define GLAMO_LCD_HV_RETR_DISP_END_MASK 0x03FF
+
+
+struct glamofb_par {
+ struct drm_device *dev;
+ struct drm_display_mode *our_mode;
+ struct glamo_framebuffer *glamo_fb;
+ int crtc_count;
+ /* crtc currently bound to this */
+ uint32_t crtc_ids[2];
+};
+
+
+static int reg_read_lcd(struct glamodrm_handle *gdrm, u_int16_t reg)
+{
+ int i = 0;
+
+ for (i = 0; i != 2; i++)
+ nop();
+
+ return ioread16(gdrm->lcd_base + reg);
+}
+
+
+static void reg_write_lcd(struct glamodrm_handle *gdrm,
+ u_int16_t reg, u_int16_t val)
+{
+ int i = 0;
+
+ for (i = 0; i != 2; i++)
+ nop();
+
+ iowrite16(val, gdrm->lcd_base + reg);
+}
+
+
+static void reg_set_bit_mask_lcd(struct glamodrm_handle *gdrm,
+ u_int16_t reg, u_int16_t mask,
+ u_int16_t val)
+{
+ u_int16_t tmp;
+
+ val &= mask;
+
+ tmp = reg_read_lcd(gdrm, reg);
+ tmp &= ~mask;
+ tmp |= val;
+ reg_write_lcd(gdrm, reg, tmp);
+}
+
+
+/* Note that this has nothing at all to do with the engine command queue
+ * in glamo-cmdq.c */
+static inline int glamo_lcd_cmdq_empty(struct glamodrm_handle *gdrm)
+{
+ /* DGCMdQempty -- 1 == command queue is empty */
+ return reg_read_lcd(gdrm, GLAMO_REG_LCD_STATUS1) & (1 << 15);
+}
+
+
+/* call holding gfb->lock_cmd when locking, until you unlock */
+int glamo_lcd_cmd_mode(struct glamodrm_handle *gdrm, int on)
+{
+ int timeout = 2000000;
+
+ if (gdrm->glamo_core->suspending) {
+ dev_err(&gdrm->glamo_core->pdev->dev,
+ "IGNORING glamofb_cmd_mode while"
+ " suspended\n");
+ return -EBUSY;
+ }
+
+ dev_dbg(gdrm->dev, "glamofb_cmd_mode(on=%d)\n", on);
+ if (on) {
+
+ while ((!glamo_lcd_cmdq_empty(gdrm)) && (timeout--))
+ /* yield() */;
+ if (timeout < 0) {
+ printk(KERN_ERR "*************"
+ " LCD command queue never got empty "
+ "*************\n");
+ return -EIO;
+ }
+
+ /* display the entire frame then switch to command */
+ reg_write_lcd(gdrm, GLAMO_REG_LCD_COMMAND1,
+ GLAMO_LCD_CMD_TYPE_DISP |
+ GLAMO_LCD_CMD_DATA_FIRE_VSYNC);
+
+ /* wait until lcd idle */
+ timeout = 2000000;
+ while ((!reg_read_lcd(gdrm, GLAMO_REG_LCD_STATUS2) & (1 << 12))
+ && (timeout--))
+ /* yield() */;
+ if (timeout < 0) {
+ printk(KERN_ERR"*************"
+ " LCD never idle "
+ "*************\n");
+ return -EIO;
+ }
+
+ mdelay(100);
+
+ } else {
+ /* RGB interface needs vsync/hsync */
+ int mode;
+ mode = reg_read_lcd(gdrm, GLAMO_REG_LCD_MODE3);
+ if ( mode & GLAMO_LCD_MODE3_RGB)
+ reg_write_lcd(gdrm, GLAMO_REG_LCD_COMMAND1,
+ GLAMO_LCD_CMD_TYPE_DISP |
+ GLAMO_LCD_CMD_DATA_DISP_SYNC);
+
+ reg_write_lcd(gdrm, GLAMO_REG_LCD_COMMAND1,
+ GLAMO_LCD_CMD_TYPE_DISP |
+ GLAMO_LCD_CMD_DATA_DISP_FIRE);
+ }
+
+ return 0;
+}
+
+
+static struct glamo_script lcd_init_script[] = {
+ { GLAMO_REG_LCD_MODE1, 0x0020 },
+ /* no display rotation, no hardware cursor, no dither, no gamma,
+ * no retrace flip, vsync low-active, hsync low active,
+ * no TVCLK, no partial display, hw dest color from fb,
+ * no partial display mode, LCD1, software flip, */
+ { GLAMO_REG_LCD_MODE2, 0x9020 },
+ /* video flip, no ptr, no ptr, dhclk off,
+ * normal mode, no cpuif,
+ * res, serial msb first, single fb, no fr ctrl,
+ * cpu if bits all zero, no crc
+ * 0000 0000 0010 0000 */
+ { GLAMO_REG_LCD_MODE3, 0x0b40 },
+ /* src data rgb565, res, 18bit rgb666
+ * 000 01 011 0100 0000 */
+ { GLAMO_REG_LCD_POLARITY, 0x440c },
+ /* DE high active, no cpu/lcd if, cs0 force low, a0 low active,
+ * np cpu if, 9bit serial data, sclk rising edge latch data
+ * 01 00 0 100 0 000 01 0 0 */
+ /* The following values assume 640*480@16bpp */
+ /* The addresses are both wrong, but get overwritten very soon */
+ { GLAMO_REG_LCD_A_BASE1, 0x0000 }, /* display A base address 15:0 */
+ { GLAMO_REG_LCD_A_BASE2, 0x0000 }, /* display A base address 22:16 */
+ { GLAMO_REG_LCD_B_BASE1, 0x6000 }, /* display B base address 15:0 */
+ { GLAMO_REG_LCD_B_BASE2, 0x0009 }, /* display B base address 22:16 */
+ { GLAMO_REG_LCD_CURSOR_BASE1, 0xC000 }, /* cursor base address 15:0 */
+ { GLAMO_REG_LCD_CURSOR_BASE2, 0x0012 }, /* cursor base address 22:16 */
+ { GLAMO_REG_LCD_COMMAND2, 0x0000 }, /* display page A */
+};
+
+
+static int glamo_run_lcd_script(struct glamodrm_handle *gdrm,
+ struct glamo_script *script, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ struct glamo_script *line = &script[i];
+
+ if (line->reg == 0xffff)
+ return 0;
+ else if (line->reg == 0xfffe)
+ msleep(line->val);
+ else
+ reg_write_lcd(gdrm, script[i].reg, script[i].val);
+ }
+
+ return 0;
+}
+
+
+#if 0
+static void notify_blank(struct drm_crtc *crtc, int mode)
+{
+ struct fb_event event;
+
+ event.info = info;
+ event.data = &blank_mode;
+ fb_notifier_call_chain(FB_EVENT_CONBLANK, &event);
+}
+#endif
+
+
+extern void jbt6k74_action(int val);
+
+
+/* Power on/off */
+static void glamo_crtc_dpms(struct drm_crtc *crtc, int mode)
+{
+ struct glamodrm_handle *gdrm;
+ struct glamo_crtc *glamo_crtc = to_glamo_crtc(crtc);
+
+ gdrm = glamo_crtc->gdrm;
+
+ switch (mode) {
+ case DRM_MODE_DPMS_OFF:
+ /* LCM need notification before pixel clock is stopped */
+ jbt6k74_action(0);
+
+ /* disable the pixel clock */
+ glamo_engine_clkreg_set(gdrm->glamo_core, GLAMO_ENGINE_LCD,
+ GLAMO_CLOCK_LCD_EN_DCLK, 0);
+ glamo_crtc->blank_mode = mode;
+ break;
+ case DRM_MODE_DPMS_ON:
+ /* enable the pixel clock if off */
+ if (glamo_crtc->blank_mode == DRM_MODE_DPMS_OFF)
+ glamo_engine_clkreg_set(gdrm->glamo_core,
+ GLAMO_ENGINE_LCD,
+ GLAMO_CLOCK_LCD_EN_DCLK,
+ GLAMO_CLOCK_LCD_EN_DCLK);
+ jbt6k74_action(1);
+ glamo_crtc->blank_mode = mode;
+ break;
+ }
+}
+
+
+static bool glamo_crtc_mode_fixup(struct drm_crtc *crtc,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ return true;
+}
+
+
+static void glamo_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
+ struct drm_framebuffer *old_fb)
+{
+ struct glamodrm_handle *gdrm;
+ struct glamo_crtc *gcrtc;
+ struct glamo_framebuffer *gfb;
+ struct drm_gem_object *obj;
+ struct drm_glamo_gem_object *gobj;
+ u32 addr;
+ u16 addr_low, addr_high;
+
+ if (!crtc->fb) {
+ DRM_DEBUG("No FB bound\n");
+ return;
+ }
+
+ /* Dig out our handle */
+ gcrtc = to_glamo_crtc(crtc);
+ gdrm = gcrtc->gdrm; /* Here it is! */
+
+ gfb = to_glamo_framebuffer(crtc->fb);
+ obj = gfb->obj;
+ gobj = obj->driver_private;
+
+ addr = GLAMO_OFFSET_FB + gobj->block->start;
+ addr_low = addr & 0xffff;
+ addr_high = ((addr >> 16) & 0x7f) | 0x4000;
+
+ glamo_lcd_cmd_mode(gdrm, 1);
+ reg_write_lcd(gdrm, GLAMO_REG_LCD_A_BASE1, addr_low);
+ reg_write_lcd(gdrm, GLAMO_REG_LCD_A_BASE2, addr_high);
+ glamo_lcd_cmd_mode(gdrm, 0);
+}
+
+
+static void glamo_crtc_mode_set(struct drm_crtc *crtc,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode,
+ int x, int y,
+ struct drm_framebuffer *old_fb)
+{
+ struct glamodrm_handle *gdrm;
+ struct glamo_crtc *gcrtc;
+ int retr_start, retr_end, disp_start, disp_end;
+ int ps;
+
+ /* Dig out our handle */
+ gcrtc = to_glamo_crtc(crtc);
+ gdrm = gcrtc->gdrm; /* Here it is! */
+
+ glamo_lcd_cmd_mode(gdrm, 1);
+ ps = mode->clock / 1000; /* Hz -> kHz */
+ ps = 1000000000UL / ps; /* kHz -> ps */
+
+ glamo_engine_reclock(gdrm->glamo_core, GLAMO_ENGINE_LCD, ps);
+ gdrm->saved_clock = ps;
+
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_WIDTH,
+ GLAMO_LCD_WIDTH_MASK, mode->hdisplay);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HEIGHT,
+ GLAMO_LCD_HEIGHT_MASK, mode->vdisplay);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_PITCH,
+ GLAMO_LCD_PITCH_MASK, mode->hdisplay*2);
+
+ /* Convert "X modeline timings" into "Glamo timings" */
+ retr_start = 0;
+ retr_end = retr_start + mode->hsync_end - mode->hsync_start;
+ disp_start = mode->htotal - mode->hsync_start;
+ disp_end = disp_start + mode->hdisplay;
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_TOTAL,
+ GLAMO_LCD_HV_TOTAL_MASK, mode->htotal);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_START,
+ GLAMO_LCD_HV_RETR_START_MASK, retr_start);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_END,
+ GLAMO_LCD_HV_RETR_END_MASK, retr_end);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_START,
+ GLAMO_LCD_HV_RETR_DISP_START_MASK, disp_start);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_END,
+ GLAMO_LCD_HV_RETR_DISP_END_MASK, disp_end);
+
+ /* The same in the vertical direction */
+ retr_start = 0;
+ retr_end = retr_start + mode->vsync_end - mode->vsync_start;
+ disp_start = mode->vtotal - mode->vsync_start;
+ disp_end = disp_start + mode->vdisplay;
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_TOTAL,
+ GLAMO_LCD_HV_TOTAL_MASK, mode->vtotal);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_START,
+ GLAMO_LCD_HV_RETR_START_MASK, retr_start);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_END,
+ GLAMO_LCD_HV_RETR_END_MASK, retr_end);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_START,
+ GLAMO_LCD_HV_RETR_DISP_START_MASK, disp_start);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_END,
+ GLAMO_LCD_HV_RETR_DISP_END_MASK, disp_end);
+
+ glamo_lcd_cmd_mode(gdrm, 0);
+
+ glamo_crtc_mode_set_base(crtc, 0, 0, old_fb);
+
+}
+
+
+static void glamo_crtc_prepare(struct drm_crtc *crtc)
+{
+}
+
+
+static void glamo_crtc_commit(struct drm_crtc *crtc)
+{
+}
+
+
+static int glamo_crtc_cursor_set(struct drm_crtc *crtc,
+ struct drm_file *file_priv,
+ uint32_t handle,
+ uint32_t width, uint32_t height)
+{
+ return 0;
+}
+
+
+static int glamo_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
+{
+ return 0;
+}
+
+
+static void glamo_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
+ u16 *blue, uint32_t size)
+{
+}
+
+
+static void glamo_crtc_destroy(struct drm_crtc *crtc)
+{
+ struct glamo_crtc *glamo_crtc = to_glamo_crtc(crtc);
+ drm_crtc_cleanup(crtc);
+ kfree(glamo_crtc);
+}
+
+
+static enum drm_connector_status
+glamo_connector_detect(struct drm_connector *connector)
+{
+ /* One hopes it hasn't been de-soldered... */
+ return connector_status_connected;
+}
+
+
+static void glamo_connector_destroy(struct drm_connector *connector)
+{
+ drm_sysfs_connector_remove(connector);
+ drm_connector_cleanup(connector);
+ kfree(connector);
+}
+
+
+static int glamo_connector_get_modes(struct drm_connector *connector)
+{
+ struct drm_display_mode *mode;
+ struct glamofb_platform_data *mach_info;
+ struct glamo_output *goutput = to_glamo_output(connector);
+ struct glamodrm_handle *gdrm = goutput->gdrm;
+
+ /* Dig out the record which will tell us about the hardware */
+ mach_info = gdrm->glamo_core->pdev->dev.platform_data;
+
+ mode = drm_mode_create(connector->dev);
+ if (!mode)
+ return 0;
+ /* Fill in 'mode' here */
+ mode->type = DRM_MODE_TYPE_DEFAULT | DRM_MODE_TYPE_PREFERRED;
+
+ /* Convert framebuffer timings into KMS timings */
+ mode->clock = 1000000000UL / mach_info->pixclock; /* ps -> kHz */
+ mode->clock *= 1000; /* kHz -> Hz */
+ mode->hdisplay = mach_info->xres.defval;
+ mode->hsync_start = mach_info->right_margin + mode->hdisplay;
+ mode->hsync_end = mode->hsync_start + mach_info->hsync_len;
+ mode->htotal = mode->hsync_end + mach_info->left_margin;
+ mode->hskew = 0;
+
+ mode->vdisplay = mach_info->yres.defval;
+ mode->vsync_start = mach_info->lower_margin + mode->vdisplay;
+ mode->vsync_end = mode->vsync_start + mach_info->vsync_len;
+ mode->vtotal = mode->vsync_end + mach_info->upper_margin;
+ mode->vscan = 0;
+
+ mode->width_mm = mach_info->width;
+ mode->height_mm = mach_info->height;
+
+ drm_mode_set_name(mode);
+ drm_mode_probed_add(connector, mode);
+
+ return 1; /* one mode, for now */
+}
+
+
+static int glamo_connector_set_property(struct drm_connector *connector,
+ struct drm_property *property,
+ uint64_t value)
+{
+ return 0;
+}
+
+
+static int glamo_connector_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
+ return MODE_NO_DBLESCAN;
+
+ return MODE_OK;
+}
+
+
+struct drm_encoder *
+glamo_connector_best_encoder(struct drm_connector *connector)
+{
+ struct glamo_output *glamo_output = to_glamo_output(connector);
+ return &glamo_output->enc;
+}
+
+
+static void glamo_encoder_dpms(struct drm_encoder *encoder, int mode)
+{
+}
+
+
+static bool glamo_encoder_mode_fixup(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ return true;
+}
+
+
+void glamo_encoder_prepare(struct drm_encoder *encoder)
+{
+}
+
+
+void glamo_encoder_commit(struct drm_encoder *encoder)
+{
+}
+
+
+static void glamo_encoder_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+}
+
+
+static void glamo_encoder_destroy(struct drm_encoder *encoder)
+{
+ drm_encoder_cleanup(encoder);
+}
+
+
+static void glamo_framebuffer_destroy(struct drm_framebuffer *fb)
+{
+ struct glamo_framebuffer *glamo_fb = to_glamo_framebuffer(fb);
+ struct drm_device *dev = fb->dev;
+
+ drm_framebuffer_cleanup(fb);
+ mutex_lock(&dev->struct_mutex);
+ drm_gem_object_unreference(glamo_fb->obj);
+ mutex_unlock(&dev->struct_mutex);
+
+ kfree(glamo_fb);
+}
+
+static int glamo_framebuffer_create_handle(struct drm_framebuffer *fb,
+ struct drm_file *file_priv,
+ unsigned int *handle)
+{
+ struct glamo_framebuffer *glamo_fb = to_glamo_framebuffer(fb);
+ struct drm_gem_object *object = glamo_fb->obj;
+
+ return drm_gem_handle_create(file_priv, object, handle);
+}
+
+
+static const struct drm_framebuffer_funcs glamo_fb_funcs = {
+ .destroy = glamo_framebuffer_destroy,
+ .create_handle = glamo_framebuffer_create_handle,
+};
+
+
+int glamo_framebuffer_create(struct drm_device *dev,
+ struct drm_mode_fb_cmd *mode_cmd,
+ struct drm_framebuffer **fb,
+ struct drm_gem_object *obj)
+{
+ struct glamo_framebuffer *glamo_fb;
+ int ret;
+
+ glamo_fb = kzalloc(sizeof(*glamo_fb), GFP_KERNEL);
+ if (!glamo_fb)
+ return -ENOMEM;
+
+ ret = drm_framebuffer_init(dev, &glamo_fb->base, &glamo_fb_funcs);
+ if (ret) {
+ DRM_ERROR("framebuffer init failed %d\n", ret);
+ return ret;
+ }
+
+ drm_helper_mode_fill_fb_struct(&glamo_fb->base, mode_cmd);
+
+ glamo_fb->obj = obj;
+
+ *fb = &glamo_fb->base;
+
+ return 0;
+}
+
+
+static struct drm_framebuffer *
+glamo_user_framebuffer_create(struct drm_device *dev,
+ struct drm_file *filp,
+ struct drm_mode_fb_cmd *mode_cmd)
+{
+ struct drm_gem_object *obj;
+ struct drm_framebuffer *fb;
+ int ret;
+
+ obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
+ if (!obj)
+ return NULL;
+
+ ret = glamo_framebuffer_create(dev, mode_cmd, &fb, obj);
+ if (ret) {
+ drm_gem_object_unreference(obj);
+ return NULL;
+ }
+
+ return fb;
+}
+
+
+int glamo_fbchanged(struct drm_device *dev)
+{
+ return 0;
+}
+
+
+/* CRTC functions */
+static const struct drm_crtc_funcs glamo_crtc_funcs = {
+ .cursor_set = glamo_crtc_cursor_set,
+ .cursor_move = glamo_crtc_cursor_move,
+ .gamma_set = glamo_crtc_gamma_set,
+ .set_config = drm_crtc_helper_set_config,
+ .destroy = glamo_crtc_destroy,
+};
+
+
+/* CRTC helper functions */
+static const struct drm_crtc_helper_funcs glamo_crtc_helper_funcs = {
+ .dpms = glamo_crtc_dpms,
+ .mode_fixup = glamo_crtc_mode_fixup,
+ .mode_set = glamo_crtc_mode_set,
+ .mode_set_base = glamo_crtc_mode_set_base,
+ .prepare = glamo_crtc_prepare,
+ .commit = glamo_crtc_commit,
+};
+
+
+/* Connector functions */
+static const struct drm_connector_funcs glamo_connector_funcs = {
+ .detect = glamo_connector_detect,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .destroy = glamo_connector_destroy,
+ .set_property = glamo_connector_set_property,
+};
+
+
+/* Connector helper functions */
+static const struct drm_connector_helper_funcs glamo_connector_helper_funcs = {
+ .mode_valid = glamo_connector_mode_valid,
+ .get_modes = glamo_connector_get_modes,
+ .best_encoder = glamo_connector_best_encoder,
+};
+
+
+/* Encoder functions */
+static const struct drm_encoder_funcs glamo_encoder_funcs = {
+ .destroy = glamo_encoder_destroy,
+};
+
+
+/* Encoder helper functions */
+static const struct drm_encoder_helper_funcs glamo_encoder_helper_funcs = {
+ .dpms = glamo_encoder_dpms,
+ .mode_fixup = glamo_encoder_mode_fixup,
+ .prepare = glamo_encoder_prepare,
+ .commit = glamo_encoder_commit,
+ .mode_set = glamo_encoder_mode_set,
+};
+
+
+/* Mode functions */
+static const struct drm_mode_config_funcs glamo_mode_funcs = {
+ .fb_create = glamo_user_framebuffer_create,
+ .fb_changed = glamo_fbchanged
+};
+
+
+static struct drm_mode_set kernelfb_mode;
+
+
+/* Restore's the kernel's fbcon mode, used for panic path */
+void glamo_display_restore(void)
+{
+ drm_crtc_helper_set_config(&kernelfb_mode);
+}
+
+
+static int glamo_display_panic(struct notifier_block *n, unsigned long ununsed,
+ void *panic_str)
+{
+ DRM_ERROR("panic occurred, switching back to text console\n");
+
+ glamo_display_restore();
+ return 0;
+}
+
+
+static struct notifier_block paniced = {
+ .notifier_call = glamo_display_panic,
+};
+
+
+int glamo_display_init(struct drm_device *dev)
+{
+ struct glamodrm_handle *gdrm;
+ struct glamo_crtc *glamo_crtc;
+ struct glamo_output *glamo_output;
+ struct drm_connector *connector;
+ struct glamo_framebuffer *glamo_fb;
+ struct fb_info *info;
+ struct glamofb_par *par;
+ struct drm_mode_set *modeset;
+
+ gdrm = dev->dev_private;
+
+ glamo_engine_enable(gdrm->glamo_core, GLAMO_ENGINE_LCD);
+ glamo_engine_reset(gdrm->glamo_core, GLAMO_ENGINE_LCD);
+
+ /* Initial setup of the LCD controller */
+ glamo_run_lcd_script(gdrm, lcd_init_script,
+ ARRAY_SIZE(lcd_init_script));
+
+ drm_mode_config_init(dev);
+
+ dev->mode_config.min_width = 240;
+ dev->mode_config.min_height = 320;
+ dev->mode_config.max_width = 480;
+ dev->mode_config.max_height = 640;
+
+ dev->mode_config.funcs = (void *)&glamo_mode_funcs;
+
+ /* Initialise our CRTC object.
+ * Only one connector per CRTC. We know this: it's kind of soldered. */
+ glamo_crtc = kzalloc(sizeof(struct glamo_crtc)
+ + sizeof(struct drm_connector *), GFP_KERNEL);
+ if (glamo_crtc == NULL) return 1;
+ glamo_crtc->gdrm = gdrm;
+ glamo_crtc->blank_mode = DRM_MODE_DPMS_OFF;
+ drm_crtc_init(dev, &glamo_crtc->base, &glamo_crtc_funcs);
+ drm_crtc_helper_add(&glamo_crtc->base, &glamo_crtc_helper_funcs);
+
+ glamo_crtc->mode_set.crtc = &glamo_crtc->base;
+ glamo_crtc->mode_set.connectors =
+ (struct drm_connector **)(glamo_crtc + 1);
+ glamo_crtc->mode_set.num_connectors = 0;
+
+ /* Create our "output" object: consists of an output and an encoder */
+ glamo_output = kzalloc(sizeof(struct glamo_output), GFP_KERNEL);
+ if (glamo_output == NULL) return 1;
+ connector = &glamo_output->base;
+ glamo_output->gdrm = gdrm;
+
+ /* Initialise the connector */
+ drm_connector_init(dev, connector, &glamo_connector_funcs,
+ DRM_MODE_CONNECTOR_Unknown);
+ drm_sysfs_connector_add(connector);
+ connector->interlace_allowed = 0;
+ connector->doublescan_allowed = 0;
+
+ /* Initialise the encoder */
+ drm_encoder_init(dev, &glamo_output->enc, &glamo_encoder_funcs,
+ DRM_MODE_ENCODER_DAC);
+ glamo_output->enc.possible_crtcs = 1 << 0;
+ drm_mode_connector_attach_encoder(&glamo_output->base,
+ &glamo_output->enc);
+
+ drm_encoder_helper_add(&glamo_output->enc, &glamo_encoder_helper_funcs);
+ drm_connector_helper_add(connector, &glamo_connector_helper_funcs);
+
+ drm_helper_initial_config(dev, false);
+
+ if (list_empty(&dev->mode_config.fb_kernel_list)) {
+ int ret, cols, cols_g;
+ cols_g = reg_read_lcd(gdrm, GLAMO_REG_LCD_MODE3) & 0xc000;
+ switch ( cols_g ) {
+ case GLAMO_LCD_SRC_RGB565 :
+ cols = GLAMO_FB_RGB565; break;
+ case GLAMO_LCD_SRC_ARGB1555 :
+ cols = GLAMO_FB_ARGB1555; break;
+ case GLAMO_LCD_SRC_ARGB4444 :
+ cols = GLAMO_FB_ARGB4444; break;
+ default :
+ printk(KERN_WARNING "Unrecognised LCD colour mode\n");
+ cols = GLAMO_FB_RGB565; break; /* Take a guess */
+ }
+ ret = glamofb_create(dev, 480, 640, 480, 640, cols, &glamo_fb);
+ if (ret) return -EINVAL;
+ }
+
+ info = glamo_fb->base.fbdev;
+ par = info->par;
+
+ modeset = &glamo_crtc->mode_set;
+ modeset->fb = &glamo_fb->base;
+ modeset->connectors[0] = connector;
+
+ par->crtc_ids[0] = glamo_crtc->base.base.id;
+
+ modeset->num_connectors = 1;
+ modeset->mode = modeset->crtc->desired_mode;
+
+ par->crtc_count = 1;
+
+ if (register_framebuffer(info) < 0)
+ return -EINVAL;
+
+ printk(KERN_INFO "[glamo-drm] fb%d: %s frame buffer device\n",
+ info->node, info->fix.id);
+
+ /* Switch back to kernel console on panic */
+ kernelfb_mode = *modeset;
+ atomic_notifier_chain_register(&panic_notifier_list, &paniced);
+ printk(KERN_INFO "[glamo-drm] Registered panic notifier\n");
+
+ return 0;
+}
+
+
+void glamo_display_suspend(struct glamodrm_handle *gdrm)
+{
+ jbt6k74_action(0);
+
+ gdrm->saved_width = reg_read_lcd(gdrm, GLAMO_REG_LCD_WIDTH);
+ gdrm->saved_height = reg_read_lcd(gdrm, GLAMO_REG_LCD_HEIGHT);
+ gdrm->saved_pitch = reg_read_lcd(gdrm, GLAMO_REG_LCD_PITCH);
+ gdrm->saved_htotal = reg_read_lcd(gdrm, GLAMO_REG_LCD_HORIZ_TOTAL);
+ gdrm->saved_hrtrst = reg_read_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_START);
+ gdrm->saved_hrtren = reg_read_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_END);
+ gdrm->saved_hdspst = reg_read_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_START);
+ gdrm->saved_hdspen = reg_read_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_END);
+ gdrm->saved_vtotal = reg_read_lcd(gdrm, GLAMO_REG_LCD_VERT_TOTAL);
+ gdrm->saved_vrtrst = reg_read_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_START);
+ gdrm->saved_vrtren = reg_read_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_END);
+ gdrm->saved_vdspst = reg_read_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_START);
+ gdrm->saved_vdspen = reg_read_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_END);
+}
+
+
+void glamo_display_resume(struct glamodrm_handle *gdrm)
+{
+ /* Reinitialise the LCD controller */
+ jbt6k74_action(0);
+ mdelay(5);
+
+ glamo_engine_enable(gdrm->glamo_core, GLAMO_ENGINE_LCD);
+ glamo_engine_reset(gdrm->glamo_core, GLAMO_ENGINE_LCD);
+ glamo_run_lcd_script(gdrm, lcd_init_script,
+ ARRAY_SIZE(lcd_init_script));
+
+ /* Enable pixel clock */
+ glamo_engine_clkreg_set(gdrm->glamo_core,
+ GLAMO_ENGINE_LCD,
+ GLAMO_CLOCK_LCD_EN_DCLK,
+ GLAMO_CLOCK_LCD_EN_DCLK);
+
+ /* Restore timings */
+ glamo_lcd_cmd_mode(gdrm, 1);
+ glamo_engine_reclock(gdrm->glamo_core, GLAMO_ENGINE_LCD,
+ gdrm->saved_clock);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_WIDTH, GLAMO_LCD_WIDTH_MASK,
+ gdrm->saved_width);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HEIGHT, GLAMO_LCD_HEIGHT_MASK,
+ gdrm->saved_height);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_PITCH, GLAMO_LCD_PITCH_MASK,
+ gdrm->saved_pitch);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_TOTAL,
+ GLAMO_LCD_HV_TOTAL_MASK, gdrm->saved_htotal);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_START,
+ GLAMO_LCD_HV_RETR_START_MASK, gdrm->saved_hrtrst);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_RETR_END,
+ GLAMO_LCD_HV_RETR_END_MASK, gdrm->saved_hrtren);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_START,
+ GLAMO_LCD_HV_RETR_DISP_START_MASK,
+ gdrm->saved_hdspst);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_HORIZ_DISP_END,
+ GLAMO_LCD_HV_RETR_DISP_END_MASK,
+ gdrm->saved_hdspen);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_TOTAL,
+ GLAMO_LCD_HV_TOTAL_MASK, gdrm->saved_vtotal);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_START,
+ GLAMO_LCD_HV_RETR_START_MASK, gdrm->saved_vrtrst);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_RETR_END,
+ GLAMO_LCD_HV_RETR_END_MASK, gdrm->saved_vrtren);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_START,
+ GLAMO_LCD_HV_RETR_DISP_START_MASK,
+ gdrm->saved_vdspst);
+ reg_set_bit_mask_lcd(gdrm, GLAMO_REG_LCD_VERT_DISP_END,
+ GLAMO_LCD_HV_RETR_DISP_END_MASK,
+ gdrm->saved_vdspen);
+ glamo_lcd_cmd_mode(gdrm, 0);
+
+ jbt6k74_action(1);
+}
diff --git a/drivers/mfd/glamo/glamo-display.h b/drivers/mfd/glamo/glamo-display.h
new file mode 100644
index 00000000000..d6f21bcb0c0
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-display.h
@@ -0,0 +1,39 @@
+/* Smedia Glamo 336x/337x Display
+ *
+ * Copyright (c) 2008-2009 Thomas White <taw@bitwiz.org.uk>
+ *
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __GLAMO_DISPLAY_H
+#define __GLAMO_DISPLAY_H
+
+#include <drm/drmP.h>
+#include "glamo-drm-private.h"
+
+extern int glamo_display_init(struct drm_device *dev);
+
+extern int glamo_framebuffer_create(struct drm_device *dev,
+ struct drm_mode_fb_cmd *mode_cmd,
+ struct drm_framebuffer **fb,
+ struct drm_gem_object *obj);
+
+extern void glamo_display_suspend(struct glamodrm_handle *gdrm);
+extern void glamo_display_resume(struct glamodrm_handle *gdrm);
+
+#endif /* __GLAMO_DISPLAY_H */
diff --git a/drivers/mfd/glamo/glamo-drm-drv.c b/drivers/mfd/glamo/glamo-drm-drv.c
new file mode 100644
index 00000000000..6b78ea726aa
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-drm-drv.c
@@ -0,0 +1,434 @@
+/* Smedia Glamo 336x/337x Graphics Driver
+ *
+ * Copyright (C) 2009 Openmoko, Inc. Jorge Luis Zapata <turran@openmoko.com>
+ * Copyright (C) 2008-2009 Thomas White <taw@bitwiz.org.uk>
+ * Copyright (C) 2009 Andreas Pokorny <andreas.pokorny@gmail.com>
+ *
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <drm/drmP.h>
+#include <drm/glamo_drm.h>
+#include <linux/glamofb.h>
+
+#include "glamo-core.h"
+#include "glamo-cmdq.h"
+#include "glamo-buffer.h"
+#include "glamo-drm-private.h"
+#include "glamo-display.h"
+#include "glamo-kms-fb.h"
+#include "glamo-fence.h"
+
+#define DRIVER_AUTHOR "Openmoko, Inc."
+#define DRIVER_NAME "glamo-drm"
+#define DRIVER_DESC "SMedia Glamo 3362"
+#define DRIVER_DATE "20090614"
+
+#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
+
+
+static int glamo_ioctl_swap(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ printk(KERN_INFO "glamo_ioctl_swap\n");
+ return 0;
+}
+
+
+static int glamo_ioctl_gem_info(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ printk(KERN_INFO "glamo_ioctl_gem_info\n");
+ return 0;
+}
+
+
+struct drm_ioctl_desc glamo_ioctls[] = {
+ DRM_IOCTL_DEF(DRM_GLAMO_CMDBUF, glamo_ioctl_cmdbuf, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_GLAMO_SWAP, glamo_ioctl_swap, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_GLAMO_CMDBURST, glamo_ioctl_cmdburst, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_GLAMO_GEM_INFO, glamo_ioctl_gem_info, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_GLAMO_GEM_CREATE, glamo_ioctl_gem_create, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_GLAMO_GEM_MMAP, glamo_ioctl_gem_mmap, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_GLAMO_GEM_PIN, glamo_ioctl_gem_pin, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_GLAMO_GEM_UNPIN, glamo_ioctl_gem_unpin, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_GLAMO_GEM_PREAD, glamo_ioctl_gem_pread, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_GLAMO_GEM_PWRITE, glamo_ioctl_gem_pwrite, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_GLAMO_GEM_WAIT_RENDERING,
+ glamo_ioctl_wait_rendering, DRM_AUTH),
+};
+
+
+static int glamodrm_firstopen(struct drm_device *dev)
+{
+ DRM_DEBUG("\n");
+ return 0;
+}
+
+
+static int glamodrm_open(struct drm_device *dev, struct drm_file *fh)
+{
+ DRM_DEBUG("\n");
+ return 0;
+}
+
+
+static void glamodrm_preclose(struct drm_device *dev, struct drm_file *fh)
+{
+ DRM_DEBUG("\n");
+}
+
+static void glamodrm_postclose(struct drm_device *dev, struct drm_file *fh)
+{
+ DRM_DEBUG("\n");
+}
+
+
+static void glamodrm_lastclose(struct drm_device *dev)
+{
+ DRM_DEBUG("\n");
+}
+
+
+static int glamodrm_master_create(struct drm_device *dev,
+ struct drm_master *master)
+{
+ DRM_DEBUG("\n");
+
+ return 0;
+}
+
+
+static void glamodrm_master_destroy(struct drm_device *dev,
+ struct drm_master *master)
+{
+ DRM_DEBUG("\n");
+}
+
+
+static int glamodrm_load(struct drm_device *dev, unsigned long flags)
+{
+ struct glamodrm_handle *gdrm;
+ gdrm = dev->dev_private;
+
+ glamo_buffer_init(gdrm);
+ glamo_cmdq_init(gdrm);
+ glamo_fence_init(gdrm);
+ glamo_display_init(dev);
+
+ return 0;
+}
+
+
+static int glamodrm_unload(struct drm_device *dev)
+{
+ struct glamodrm_handle *gdrm;
+
+ gdrm = dev->dev_private;
+
+ glamo_engine_disable(gdrm->glamo_core, GLAMO_ENGINE_2D);
+ glamo_engine_disable(gdrm->glamo_core, GLAMO_ENGINE_3D);
+ glamo_buffer_final(gdrm);
+ glamo_fence_shutdown(gdrm);
+
+ return 0;
+}
+
+
+static struct vm_operations_struct glamodrm_gem_vm_ops = {
+ .fault = glamodrm_gem_fault,
+};
+
+static struct drm_driver glamodrm_drm_driver = {
+ .driver_features = DRIVER_IS_PLATFORM | DRIVER_GEM | DRIVER_MODESET,
+ .firstopen = glamodrm_firstopen,
+ .load = glamodrm_load,
+ .unload = glamodrm_unload,
+ .open = glamodrm_open,
+ .preclose = glamodrm_preclose,
+ .postclose = glamodrm_postclose,
+ .lastclose = glamodrm_lastclose,
+ .reclaim_buffers = drm_core_reclaim_buffers,
+ .get_map_ofs = drm_core_get_map_ofs,
+ .get_reg_ofs = drm_core_get_reg_ofs,
+ .master_create = glamodrm_master_create,
+ .master_destroy = glamodrm_master_destroy,
+ .gem_init_object = glamodrm_gem_init_object,
+ .gem_free_object = glamodrm_gem_free_object,
+ .gem_vm_ops = &glamodrm_gem_vm_ops,
+ .ioctls = glamo_ioctls,
+ .fops = {
+ .owner = THIS_MODULE,
+ .open = drm_open,
+ .release = drm_release,
+ .ioctl = drm_ioctl,
+ .mmap = drm_gem_mmap,
+ .poll = drm_poll,
+ .fasync = drm_fasync,
+ },
+ .major = 0,
+ .minor = 1,
+ .patchlevel = 0,
+ .name = DRIVER_NAME,
+ .desc = DRIVER_DESC,
+ .date = DRIVER_DATE,
+};
+
+
+static int glamodrm_probe(struct platform_device *pdev)
+{
+ int rc;
+ struct glamodrm_handle *gdrm;
+ struct glamofb_platform_data *mach_info;
+
+ printk(KERN_INFO "[glamo-drm] SMedia Glamo Direct Rendering Support\n");
+
+ gdrm = kmalloc(sizeof(*gdrm), GFP_KERNEL);
+ if ( !gdrm )
+ return -ENOMEM;
+ platform_set_drvdata(pdev, gdrm);
+ mach_info = pdev->dev.platform_data;
+ gdrm->glamo_core = mach_info->glamo;
+ gdrm->dev = &pdev->dev;
+
+ /* Find the command queue registers */
+ gdrm->reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if ( !gdrm->reg ) {
+ dev_err(&pdev->dev, "Unable to find cmdq registers.\n");
+ rc = -ENOENT;
+ goto out_free;
+ }
+ gdrm->reg = request_mem_region(gdrm->reg->start,
+ RESSIZE(gdrm->reg), pdev->name);
+ if ( !gdrm->reg ) {
+ dev_err(&pdev->dev, "failed to request MMIO region\n");
+ rc = -ENOENT;
+ goto out_free;
+ }
+ gdrm->reg_base = ioremap(gdrm->reg->start, RESSIZE(gdrm->reg));
+ if ( !gdrm->reg_base ) {
+ dev_err(&pdev->dev, "failed to ioremap() MMIO registers\n");
+ rc = -ENOENT;
+ goto out_release_regs;
+ }
+
+ /* Find the command queue itself */
+ gdrm->cmdq = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if ( !gdrm->cmdq ) {
+ dev_err(&pdev->dev, "Unable to find command queue.\n");
+ rc = -ENOENT;
+ goto out_unmap_regs;
+ }
+ gdrm->cmdq = request_mem_region(gdrm->cmdq->start,
+ RESSIZE(gdrm->cmdq), pdev->name);
+ if ( !gdrm->cmdq ) {
+ dev_err(&pdev->dev, "failed to request command queue region\n");
+ rc = -ENOENT;
+ goto out_unmap_regs;
+ }
+ gdrm->cmdq_base = ioremap(gdrm->cmdq->start, RESSIZE(gdrm->cmdq));
+ if ( !gdrm->cmdq_base ) {
+ dev_err(&pdev->dev, "failed to ioremap() command queue\n");
+ rc = -ENOENT;
+ goto out_release_cmdq;
+ }
+
+ /* Find the VRAM */
+ gdrm->vram = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ if ( !gdrm->vram ) {
+ dev_err(&pdev->dev, "Unable to find VRAM.\n");
+ rc = -ENOENT;
+ goto out_unmap_cmdq;
+ }
+ gdrm->vram = request_mem_region(gdrm->vram->start,
+ RESSIZE(gdrm->vram), pdev->name);
+ if ( !gdrm->vram ) {
+ dev_err(&pdev->dev, "failed to request VRAM region\n");
+ rc = -ENOENT;
+ goto out_unmap_cmdq;
+ }
+
+ /* Find the LCD controller */
+ gdrm->lcd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 3);
+ if ( !gdrm->lcd_regs ) {
+ dev_err(&pdev->dev, "Unable to find LCD registers.\n");
+ rc = -ENOENT;
+ goto out_release_vram;
+ }
+ gdrm->lcd_regs = request_mem_region(gdrm->lcd_regs->start,
+ RESSIZE(gdrm->lcd_regs),
+ pdev->name);
+ if ( !gdrm->lcd_regs ) {
+ dev_err(&pdev->dev, "failed to request LCD registers\n");
+ rc = -ENOENT;
+ goto out_release_vram;
+ }
+ gdrm->lcd_base = ioremap(gdrm->lcd_regs->start, RESSIZE(gdrm->lcd_regs));
+ if ( !gdrm->lcd_base ) {
+ dev_err(&pdev->dev, "failed to ioremap() LCD registers\n");
+ rc = -ENOENT;
+ goto out_release_lcd;
+ }
+
+ /* Find the 2D engine */
+ gdrm->twod_regs = platform_get_resource(pdev, IORESOURCE_MEM, 4);
+ if ( !gdrm->twod_regs ) {
+ dev_err(&pdev->dev, "Unable to find 2D registers.\n");
+ rc = -ENOENT;
+ goto out_unmap_lcd;
+ }
+ gdrm->twod_regs = request_mem_region(gdrm->twod_regs->start,
+ RESSIZE(gdrm->twod_regs),
+ pdev->name);
+ if ( !gdrm->twod_regs ) {
+ dev_err(&pdev->dev, "failed to request 2D registers\n");
+ rc = -ENOENT;
+ goto out_unmap_lcd;
+ }
+ gdrm->twod_base = ioremap(gdrm->twod_regs->start, RESSIZE(gdrm->twod_regs));
+ if ( !gdrm->twod_base ) {
+ dev_err(&pdev->dev, "failed to ioremap() 2D registers\n");
+ rc = -ENOENT;
+ goto out_release_2d;
+ }
+
+ gdrm->vram_size = GLAMO_FB_SIZE;
+ printk(KERN_INFO "[glamo-drm] %lli bytes of VRAM\n",
+ (long long int)gdrm->vram_size);
+
+ /* Initialise DRM */
+ drm_platform_init(&glamodrm_drm_driver, pdev, (void *)gdrm);
+
+ return 0;
+
+out_release_2d:
+ release_mem_region(gdrm->twod_regs->start, RESSIZE(gdrm->twod_regs));
+out_unmap_lcd:
+ iounmap(gdrm->lcd_base);
+out_release_lcd:
+ release_mem_region(gdrm->lcd_regs->start, RESSIZE(gdrm->lcd_regs));
+out_unmap_cmdq:
+ iounmap(gdrm->cmdq_base);
+out_release_cmdq:
+ release_mem_region(gdrm->cmdq->start, RESSIZE(gdrm->cmdq));
+out_release_vram:
+ release_mem_region(gdrm->vram->start, RESSIZE(gdrm->vram));
+out_unmap_regs:
+ iounmap(gdrm->reg_base);
+out_release_regs:
+ release_mem_region(gdrm->reg->start, RESSIZE(gdrm->reg));
+out_free:
+ kfree(gdrm);
+ pdev->dev.driver_data = NULL;
+ return rc;
+}
+
+
+static int glamodrm_remove(struct platform_device *pdev)
+{
+ struct glamodrm_handle *gdrm = platform_get_drvdata(pdev);
+
+ glamo_buffer_final(gdrm);
+ glamo_cmdq_shutdown(gdrm);
+
+ drm_exit(&glamodrm_drm_driver);
+
+ platform_set_drvdata(pdev, NULL);
+
+ /* Release registers */
+ iounmap(gdrm->reg_base);
+ release_mem_region(gdrm->reg->start, RESSIZE(gdrm->reg));
+
+ /* Release VRAM */
+// iounmap(gdrm->vram_base);
+ release_mem_region(gdrm->vram->start, RESSIZE(gdrm->vram));
+
+ /* Release command queue */
+ iounmap(gdrm->cmdq_base);
+ release_mem_region(gdrm->cmdq->start, RESSIZE(gdrm->cmdq));
+
+ /* Release 2D engine */
+ iounmap(gdrm->twod_base);
+ release_mem_region(gdrm->twod_regs->start, RESSIZE(gdrm->twod_regs));
+
+ kfree(gdrm);
+
+ return 0;
+}
+
+
+static int glamodrm_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct glamodrm_handle *gdrm = platform_get_drvdata(pdev);
+
+ glamo_kmsfb_suspend(gdrm);
+ glamo_display_suspend(gdrm);
+ glamo_cmdq_suspend(gdrm);
+
+ /* glamo_core.c will suspend the engines for us */
+
+ return 0;
+}
+
+
+static int glamodrm_resume(struct platform_device *pdev)
+{
+ struct glamodrm_handle *gdrm = platform_get_drvdata(pdev);
+
+ glamo_cmdq_resume(gdrm);
+ glamo_display_resume(gdrm);
+ glamo_kmsfb_resume(gdrm);
+
+ return 0;
+}
+
+
+static struct platform_driver glamodrm_driver = {
+ .probe = glamodrm_probe,
+ .remove = glamodrm_remove,
+ .suspend = glamodrm_suspend,
+ .resume = glamodrm_resume,
+ .driver = {
+ .name = "glamo-fb",
+ .owner = THIS_MODULE,
+ },
+};
+
+
+static int __devinit glamodrm_init(void)
+{
+ glamodrm_drm_driver.num_ioctls = DRM_ARRAY_SIZE(glamo_ioctls);
+ return platform_driver_register(&glamodrm_driver);
+}
+
+
+static void __exit glamodrm_exit(void)
+{
+ platform_driver_unregister(&glamodrm_driver);
+}
+
+
+module_init(glamodrm_init);
+module_exit(glamodrm_exit);
+
+MODULE_AUTHOR(DRIVER_AUTHOR);
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/glamo/glamo-drm-private.h b/drivers/mfd/glamo/glamo-drm-private.h
new file mode 100644
index 00000000000..02ae7e9fd2e
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-drm-private.h
@@ -0,0 +1,155 @@
+/* Smedia Glamo 336x/337x DRM private bits
+ *
+ * Copyright (C) 2008-2009 Thomas White <taw@bitwiz.org.uk>
+ * Copyright (C) 2009 Andreas Pokorny <andreas.pokorny@gmail.com>
+ * Based on xf86-video-glamo
+ * Copyright 2007 OpenMoko, Inc.
+ * Copyright © 2009 Lars-Peter Clausen <lars@metafoo.de>
+ *
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __GLAMO_DRMPRIV_H
+#define __GLAMO_DRMPRIV_H
+
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/semaphore.h>
+#include <linux/spinlock.h>
+#include <linux/wait.h>
+
+#include "glamo-core.h"
+
+
+/* Memory to allocate for the framebuffer.
+ * The rest is reserved for the DRM memory manager */
+#define GLAMO_FRAMEBUFFER_ALLOCATION (2*480*640)
+
+
+struct glamodrm_handle {
+
+ /* This device */
+ struct device *dev;
+
+ /* The parent device handle */
+ struct glamo_core *glamo_core;
+
+ /* Framebuffer handle for the console (i.e. /dev/fb0) */
+ struct fb_info *fb;
+
+ /* Command queue registers */
+ struct resource *reg;
+ char __iomem *reg_base;
+
+ /* VRAM region */
+ struct resource *vram;
+
+ /* Command queue region */
+ struct resource *cmdq;
+ char __iomem *cmdq_base;
+
+ /* LCD controller registers */
+ struct resource *lcd_regs;
+ char __iomem *lcd_base;
+
+ /* 2D engine registers */
+ struct resource *twod_regs;
+ char __iomem *twod_base;
+
+ ssize_t vram_size;
+
+ /* Memory management */
+ struct drm_mm *mmgr;
+
+ /* semaphore against concurrent ioctl */
+ struct semaphore add_to_ring;
+
+ /* Saved state */
+ u_int16_t saved_clock;
+ u_int16_t saved_width;
+ u_int16_t saved_height;
+ u_int16_t saved_pitch;
+ u_int16_t saved_htotal;
+ u_int16_t saved_hrtrst;
+ u_int16_t saved_hrtren;
+ u_int16_t saved_hdspst;
+ u_int16_t saved_hdspen;
+ u_int16_t saved_vtotal;
+ u_int16_t saved_vrtrst;
+ u_int16_t saved_vrtren;
+ u_int16_t saved_vdspst;
+ u_int16_t saved_vdspen;
+
+ /* Fencing */
+ atomic_t curr_seq; /* The last used stamp number */
+ struct list_head fence_list; /* List of active fences */
+ rwlock_t fence_list_lock; /* Lock to protect fence_list */
+ wait_queue_head_t fence_queue; /* Waitqueue */
+ struct tasklet_struct fence_tl; /* Tasklet for fence IRQ */
+
+ /* A scratch block */
+ struct drm_mm_node *scratch;
+};
+
+
+/* Private data. This is where we keep our memory management bits */
+struct drm_glamo_gem_object {
+ struct drm_gem_object *obj; /* The GEM object this refers to */
+ struct drm_mm_node *block; /* Block handle for drm_mm */
+ uint64_t mmap_offset;
+};
+
+
+struct glamo_crtc {
+ struct drm_crtc base;
+ struct glamodrm_handle *gdrm;
+ /* a mode_set for fbdev users on this crtc */
+ struct drm_mode_set mode_set;
+ int blank_mode;
+};
+
+
+struct glamo_framebuffer {
+ struct drm_framebuffer base;
+ struct drm_gem_object *obj;
+};
+
+
+struct glamo_output {
+ struct drm_connector base;
+ struct drm_encoder enc;
+ struct glamodrm_handle *gdrm;
+};
+
+
+/* Colour mode for KMS framebuffer */
+enum {
+ GLAMO_FB_RGB565,
+ GLAMO_FB_ARGB1555,
+ GLAMO_FB_ARGB4444
+};
+
+
+#define to_glamo_crtc(x) container_of(x, struct glamo_crtc, base)
+#define to_glamo_output(x) container_of(x, struct glamo_output, base)
+#define enc_to_glamo_output(x) container_of(x, struct glamo_output, enc)
+#define to_glamo_framebuffer(x) container_of(x, struct glamo_framebuffer, base)
+
+
+#endif /* __GLAMO_DRMPRIV_H */
diff --git a/drivers/mfd/glamo/glamo-fb.c b/drivers/mfd/glamo/glamo-fb.c
index 21165d97fb2..f2f92bcfe66 100644
--- a/drivers/mfd/glamo/glamo-fb.c
+++ b/drivers/mfd/glamo/glamo-fb.c
@@ -734,6 +734,12 @@ static int glamofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
struct glamofb_handle *glamo = info->par;
unsigned long flags;
+ /* Reject if the cursor is too big to fit in the memory allocated in
+ * glamo-core.h */
+
+ if ((cursor->image.width * cursor->image.height) > GLAMO_CURSOR_SIZE )
+ return -EINVAL;
+
spin_lock_irqsave(&glamo->lock_cmd, flags);
reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_SIZE,
diff --git a/drivers/mfd/glamo/glamo-fence.c b/drivers/mfd/glamo/glamo-fence.c
new file mode 100644
index 00000000000..178de2ab282
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-fence.c
@@ -0,0 +1,327 @@
+/*
+ * SMedia Glamo 336x/337x fence objects
+ *
+ * Copyright (c) 2009 Thomas White <taw@bitwiz.org.uk>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ *
+ * Loosely based on radeon_fence.c, to which the following notice applies:
+ *
+ * Copyright 2009 Jerome Glisse.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ */
+/*
+ * Authors:
+ * Jerome Glisse <glisse@freedesktop.org>
+ * Dave Airlie
+ */
+
+
+#include <drm/drmP.h>
+#include <drm/glamo_drm.h>
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/lockdep.h>
+
+#include "glamo-drm-private.h"
+#include "glamo-regs.h"
+#include "glamo-core.h"
+#include "glamo-cmdq.h"
+
+
+static struct lock_class_key glamo_fence_lock_key;
+
+
+struct glamo_fence
+{
+ struct list_head list;
+ uint16_t seq; /* Wait for at least this ID */
+ int signalled; /* Non-zero when fence has passed */
+ struct glamodrm_handle *gdrm;
+};
+
+
+static void glamo_fence_emit(struct glamo_fence *fence)
+{
+ u16 fring[6];
+
+ fring[0] = 0x8000 | GLAMO_REG_2D_ID1;
+ fring[1] = 3;
+ fence->seq = atomic_inc_return(&fence->gdrm->curr_seq);
+ if ( fence->seq > 1<<14 ) {
+ atomic_set(&fence->gdrm->curr_seq, 0);
+ fence->seq = atomic_inc_return(&fence->gdrm->curr_seq);
+ }
+ fring[2] = 1<<15 | fence->seq;
+ fring[3] = 0; /* Unused */
+ fring[4] = 0; /* Unused */
+ fring[5] = 0; /* Padding */
+
+ glamo_add_to_ring(fence->gdrm, fring, 12);
+}
+
+
+static void glamo_fence_enable(struct glamodrm_handle *gdrm)
+{
+ glamo_enable_irq(gdrm->glamo_core, GLAMO_IRQ_2D);
+}
+
+
+static inline u16 reg_read_2d(struct glamodrm_handle *gdrm, u_int16_t reg)
+{
+ /* For command queue, the address is given relative to
+ * the overall base of Glamo. This isn't the case here. */
+ return ioread16(gdrm->twod_base + reg-GLAMO_REGOFS_2D);
+}
+
+
+static inline u16 reg_read_cmdq(struct glamodrm_handle *gdrm, u_int16_t reg)
+{
+ return ioread16(gdrm->reg_base + reg);
+}
+
+
+static void glamo_cmdq_wait(struct glamodrm_handle *gdrm,
+ enum glamo_engine engine)
+{
+ u16 mask, val, status;
+ int i;
+
+ switch (engine)
+ {
+ case GLAMO_ENGINE_ALL:
+ mask = 1 << 2;
+ val = mask;
+ break;
+ default:
+ return;
+ }
+
+ for ( i=0; i<1000; i++ ) {
+ status = reg_read_cmdq(gdrm, GLAMO_REG_CMDQ_STATUS);
+ if ((status & mask) == val) break;
+ mdelay(1);
+ }
+ if ( i == 1000 ) {
+ size_t ring_read;
+ printk(KERN_WARNING "[glamo-drm] CmdQ timeout!\n");
+ printk(KERN_WARNING "[glamo-drm] status = %x\n", status);
+ ring_read = reg_read_cmdq(gdrm, GLAMO_REG_CMDQ_READ_ADDRL);
+ ring_read |= ((reg_read_cmdq(gdrm, GLAMO_REG_CMDQ_READ_ADDRH)
+ & 0x7) << 16);
+ printk(KERN_INFO "[glamo-drm] ring_read now 0x%x\n",
+ ring_read);
+ }
+}
+
+
+static void glamo_fence_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+ struct glamodrm_handle *gdrm = desc->handler_data;
+
+ if (!gdrm) {
+ printk(KERN_ERR "[glamo-drm] 2D IRQ called with no data\n");
+ return;
+ }
+ glamo_clear_irq(gdrm->glamo_core, GLAMO_IRQ_2D);
+
+ tasklet_schedule(&gdrm->fence_tl);
+}
+
+
+/* This is nasty. I'm sorry. */
+static void glamo_fence_debodge(struct glamodrm_handle *gdrm)
+{
+ struct list_head *tmp;
+
+ printk(KERN_ERR "[glamo-drm] Attempting to recover...\n");
+
+ glamo_cmdq_wait(gdrm, GLAMO_ENGINE_ALL);
+ glamo_engine_reset(gdrm->glamo_core, GLAMO_ENGINE_2D);
+
+ read_lock(&gdrm->fence_list_lock);
+ list_for_each(tmp, &gdrm->fence_list) {
+
+ struct glamo_fence *fence;
+
+ fence = list_entry(tmp, struct glamo_fence, list);
+
+ if ( fence->signalled != 1 ) {
+ printk(KERN_ERR "[glamo-drm] Fence seq#%i was not"
+ " signalled\n", fence->seq);
+ }
+ fence->signalled = 1;
+
+ }
+ read_unlock(&gdrm->fence_list_lock);
+
+ wake_up_all(&gdrm->fence_queue);
+}
+
+
+static void glamo_fence_tl(unsigned long data)
+{
+ struct glamodrm_handle *gdrm = (struct glamodrm_handle *)data;
+ int wake = 0;
+ u16 seq;
+ struct list_head *tmp;
+
+
+ seq = reg_read_2d(gdrm, GLAMO_REG_2D_ID1) & 0x7fff;
+
+ read_lock(&gdrm->fence_list_lock);
+ list_for_each(tmp, &gdrm->fence_list) {
+
+ struct glamo_fence *fence;
+
+ fence = list_entry(tmp, struct glamo_fence, list);
+ if ( seq >= fence->seq ) {
+ fence->signalled = 1;
+ wake = 1;
+ }
+
+ }
+ read_unlock(&gdrm->fence_list_lock);
+
+ if ( wake ) wake_up_all(&gdrm->fence_queue);
+}
+
+
+static struct glamo_fence *glamo_fence_new(struct glamodrm_handle *gdrm)
+{
+ struct glamo_fence *fence;
+ unsigned long irq_flags;
+
+ fence = drm_calloc(1, sizeof(*fence), DRM_MEM_DRIVER);
+ fence->signalled = 0;
+ fence->gdrm = gdrm;
+
+ /* Add to list */
+ write_lock_irqsave(&gdrm->fence_list_lock, irq_flags);
+ list_add(&fence->list, &gdrm->fence_list);
+ write_unlock_irqrestore(&gdrm->fence_list_lock, irq_flags);
+
+ return fence;
+}
+
+
+static struct glamo_fence *glamo_fence_destroy(struct glamo_fence *fence)
+{
+ unsigned long irq_flags;
+ struct glamodrm_handle *gdrm = fence->gdrm;
+
+ /* Remove from list */
+ write_lock_irqsave(&gdrm->fence_list_lock, irq_flags);
+ list_del(&fence->list);
+ write_unlock_irqrestore(&gdrm->fence_list_lock, irq_flags);
+
+ drm_free(fence, 1, DRM_MEM_DRIVER);
+
+ return fence;
+}
+
+
+int glamo_ioctl_wait_rendering(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ struct glamodrm_handle *gdrm;
+ struct drm_glamo_gem_wait_rendering *args = data;
+ struct glamo_fence *fence;
+ int r;
+
+ gdrm = dev->dev_private;
+
+ if ( !args->have_handle ) {
+ glamo_cmdq_wait(gdrm, GLAMO_ENGINE_ALL);
+ return 0;
+ }
+
+ fence = glamo_fence_new(gdrm);
+ if ( fence == NULL ) {
+ printk(KERN_WARNING "[glamo-drm] Couldn't allocate fence -"
+ " falling back to busy wait.\n");
+ glamo_cmdq_wait(gdrm, GLAMO_ENGINE_ALL);
+ return 0;
+ }
+
+ glamo_fence_emit(fence);
+
+ /* Wait... */
+ r = wait_event_interruptible_timeout(gdrm->fence_queue,
+ fence->signalled, HZ);
+ if ( r == 0 ) {
+ printk(KERN_ERR "[glamo-drm] Timeout!\n");
+ glamo_fence_debodge(gdrm);
+ }
+
+ glamo_fence_destroy(fence);
+
+ return 0;
+}
+
+
+void glamo_fence_init(struct glamodrm_handle *gdrm)
+{
+ unsigned long irq_flags;
+
+ gdrm->fence_list_lock = __RW_LOCK_UNLOCKED(gdrm->fence_list_lock);
+ lockdep_set_class(&gdrm->fence_list_lock, &glamo_fence_lock_key);
+ init_waitqueue_head(&gdrm->fence_queue);
+
+ atomic_set(&gdrm->curr_seq, 0);
+
+ write_lock_irqsave(&gdrm->fence_list_lock, irq_flags);
+ INIT_LIST_HEAD(&gdrm->fence_list);
+ write_unlock_irqrestore(&gdrm->fence_list_lock, irq_flags);
+
+ tasklet_init(&gdrm->fence_tl, glamo_fence_tl, (unsigned long)gdrm);
+
+ /* Set up IRQ */
+ set_irq_handler(IRQ_GLAMO(GLAMO_IRQIDX_2D), glamo_fence_irq_handler);
+ set_irq_data(IRQ_GLAMO(GLAMO_IRQIDX_2D), gdrm);
+
+ glamo_fence_enable(gdrm);
+}
+
+
+void glamo_fence_shutdown(struct glamodrm_handle *gdrm)
+{
+ set_irq_handler(IRQ_GLAMO(GLAMO_IRQIDX_CMDQUEUE), handle_level_irq);
+ wake_up_all(&gdrm->fence_queue);
+ tasklet_kill(&gdrm->fence_tl);
+}
diff --git a/drivers/mfd/glamo/glamo-fence.h b/drivers/mfd/glamo/glamo-fence.h
new file mode 100644
index 00000000000..deda9956f40
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-fence.h
@@ -0,0 +1,34 @@
+/*
+ * SMedia Glamo 336x/337x fence objects
+ *
+ * Copyright (c) 2009 Thomas White <taw@bitwiz.org.uk>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef __GLAMO_FENCE_H
+#define __GLAMO_FENCE_H
+
+#include <drm/drmP.h>
+
+#include "glamo-drm-private.h"
+
+extern void glamo_fence_init(struct glamodrm_handle *gdrm);
+extern void glamo_fence_shutdown(struct glamodrm_handle *gdrm);
+
+extern int glamo_ioctl_wait_rendering(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
+
+#endif /* __GLAMO_FENCE_H */
diff --git a/drivers/mfd/glamo/glamo-kms-fb.c b/drivers/mfd/glamo/glamo-kms-fb.c
new file mode 100644
index 00000000000..e5b84310848
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-kms-fb.c
@@ -0,0 +1,539 @@
+/*
+ * SMedia Glamo 336x/337x KMS Framebuffer
+ *
+ * Copyright (C) 2009 Thomas White <taw@bitwiz.org.uk>
+ *
+ * Based on glamo-fb.c (C) 2007-2008 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * Based on intel_fb.c from drivers/gpu/drm/i915
+ * to which the following licence applies:
+ *
+ * Copyright © 2006-2007 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Eric Anholt <eric@anholt.net>
+ *
+ */
+
+
+#include <drm/drmP.h>
+#include <drm/glamo_drm.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_crtc.h>
+
+#include "glamo-core.h"
+#include "glamo-drm-private.h"
+#include "glamo-display.h"
+#include "glamo-buffer.h"
+
+
+struct glamofb_par {
+ struct drm_device *dev;
+ struct drm_display_mode *our_mode;
+ struct glamo_framebuffer *glamo_fb;
+ int crtc_count;
+ /* crtc currently bound to this */
+ uint32_t crtc_ids[2];
+};
+
+
+static int glamofb_setcolreg(unsigned regno, unsigned red, unsigned green,
+ unsigned blue, unsigned transp,
+ struct fb_info *info)
+{
+ struct glamofb_par *par = info->par;
+ struct drm_device *dev = par->dev;
+ struct drm_crtc *crtc;
+ int i;
+
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+ struct glamo_crtc *glamo_crtc = to_glamo_crtc(crtc);
+ struct drm_mode_set *modeset = &glamo_crtc->mode_set;
+ struct drm_framebuffer *fb = modeset->fb;
+
+ for (i = 0; i < par->crtc_count; i++)
+ if (crtc->base.id == par->crtc_ids[i])
+ break;
+
+ if (i == par->crtc_count)
+ continue;
+
+
+ if (regno > 255)
+ return 1;
+
+ if (regno < 16) {
+ switch (fb->depth) {
+ case 15:
+ fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) |
+ ((green & 0xf800) >> 6) |
+ ((blue & 0xf800) >> 11);
+ break;
+ case 16:
+ fb->pseudo_palette[regno] = (red & 0xf800) |
+ ((green & 0xfc00) >> 5) |
+ ((blue & 0xf800) >> 11);
+ break;
+ case 24:
+ case 32:
+ fb->pseudo_palette[regno] = ((red & 0xff00) << 8) |
+ (green & 0xff00) |
+ ((blue & 0xff00) >> 8);
+ break;
+ }
+ }
+ }
+ return 0;
+}
+
+static int glamofb_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ struct glamofb_par *par = info->par;
+ struct glamo_framebuffer *glamo_fb = par->glamo_fb;
+ struct drm_framebuffer *fb = &glamo_fb->base;
+ int depth;
+
+ /* Need to resize the fb object !!! */
+ if (var->xres > fb->width || var->yres > fb->height) {
+ DRM_ERROR("Cannot resize framebuffer object (%dx%d > %dx%d)\n",
+ var->xres,var->yres,fb->width,fb->height);
+ DRM_ERROR("Need resizing code.\n");
+ return -EINVAL;
+ }
+
+ switch (var->bits_per_pixel) {
+ case 16:
+ depth = (var->green.length == 6) ? 16 : 15;
+ break;
+ case 32:
+ depth = (var->transp.length > 0) ? 32 : 24;
+ break;
+ default:
+ depth = var->bits_per_pixel;
+ break;
+ }
+
+ switch (depth) {
+ case 16:
+ var->red.offset = 11;
+ var->green.offset = 5;
+ var->blue.offset = 0;
+ var->red.length = 5;
+ var->green.length = 6;
+ var->blue.length = 5;
+ var->transp.length = 0;
+ var->transp.offset = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/* this will let fbcon do the mode init */
+/* FIXME: take mode config lock? */
+static int glamofb_set_par(struct fb_info *info)
+{
+ struct glamofb_par *par = info->par;
+ struct drm_device *dev = par->dev;
+ struct fb_var_screeninfo *var = &info->var;
+ int i;
+
+ DRM_DEBUG("%d %d\n", var->xres, var->pixclock);
+
+ if (var->pixclock != -1) {
+
+ DRM_ERROR("PIXEL CLOCK SET\n");
+ return -EINVAL;
+ } else {
+ struct drm_crtc *crtc;
+ int ret;
+
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+ struct glamo_crtc *glamo_crtc = to_glamo_crtc(crtc);
+
+ for (i = 0; i < par->crtc_count; i++)
+ if (crtc->base.id == par->crtc_ids[i])
+ break;
+
+ if (i == par->crtc_count)
+ continue;
+
+ if (crtc->fb == glamo_crtc->mode_set.fb) {
+ mutex_lock(&dev->mode_config.mutex);
+ ret = crtc->funcs->set_config(&glamo_crtc->mode_set);
+ mutex_unlock(&dev->mode_config.mutex);
+ if (ret)
+ return ret;
+ }
+ }
+ return 0;
+ }
+}
+
+static int glamofb_pan_display(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ struct glamofb_par *par = info->par;
+ struct drm_device *dev = par->dev;
+ struct drm_mode_set *modeset;
+ struct drm_crtc *crtc;
+ struct glamo_crtc *glamo_crtc;
+ int ret = 0;
+ int i;
+
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+ for (i = 0; i < par->crtc_count; i++)
+ if (crtc->base.id == par->crtc_ids[i])
+ break;
+
+ if (i == par->crtc_count)
+ continue;
+
+ glamo_crtc = to_glamo_crtc(crtc);
+ modeset = &glamo_crtc->mode_set;
+
+ modeset->x = var->xoffset;
+ modeset->y = var->yoffset;
+
+ if (modeset->num_connectors) {
+ mutex_lock(&dev->mode_config.mutex);
+ ret = crtc->funcs->set_config(modeset);
+ mutex_unlock(&dev->mode_config.mutex);
+ if (!ret) {
+ info->var.xoffset = var->xoffset;
+ info->var.yoffset = var->yoffset;
+ }
+ }
+ }
+
+ return ret;
+}
+
+static void glamofb_on(struct fb_info *info)
+{
+ struct glamofb_par *par = info->par;
+ struct drm_device *dev = par->dev;
+ struct drm_crtc *crtc;
+ struct drm_encoder *encoder;
+ int i;
+
+ /*
+ * For each CRTC in this fb, find all associated encoders
+ * and turn them off, then turn off the CRTC.
+ */
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+ struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+
+ for (i = 0; i < par->crtc_count; i++)
+ if (crtc->base.id == par->crtc_ids[i])
+ break;
+
+ crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
+
+ /* Found a CRTC on this fb, now find encoders */
+ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+ if (encoder->crtc == crtc) {
+ struct drm_encoder_helper_funcs *encoder_funcs;
+ encoder_funcs = encoder->helper_private;
+ encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
+ }
+ }
+ }
+}
+
+static void glamofb_off(struct fb_info *info, int dpms_mode)
+{
+ struct glamofb_par *par = info->par;
+ struct drm_device *dev = par->dev;
+ struct drm_crtc *crtc;
+ struct drm_encoder *encoder;
+ int i;
+
+ /*
+ * For each CRTC in this fb, find all associated encoders
+ * and turn them off, then turn off the CRTC.
+ */
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+ struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+
+ for (i = 0; i < par->crtc_count; i++)
+ if (crtc->base.id == par->crtc_ids[i])
+ break;
+
+ /* Found a CRTC on this fb, now find encoders */
+ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+ if (encoder->crtc == crtc) {
+ struct drm_encoder_helper_funcs *encoder_funcs;
+ encoder_funcs = encoder->helper_private;
+ encoder_funcs->dpms(encoder, dpms_mode);
+ }
+ }
+ if (dpms_mode == DRM_MODE_DPMS_OFF)
+ crtc_funcs->dpms(crtc, dpms_mode);
+ }
+}
+
+static int glamofb_blank(int blank, struct fb_info *info)
+{
+ switch (blank) {
+ case FB_BLANK_UNBLANK:
+ glamofb_on(info);
+ break;
+ case FB_BLANK_NORMAL:
+ glamofb_off(info, DRM_MODE_DPMS_STANDBY);
+ break;
+ case FB_BLANK_HSYNC_SUSPEND:
+ glamofb_off(info, DRM_MODE_DPMS_STANDBY);
+ break;
+ case FB_BLANK_VSYNC_SUSPEND:
+ glamofb_off(info, DRM_MODE_DPMS_SUSPEND);
+ break;
+ case FB_BLANK_POWERDOWN:
+ glamofb_off(info, DRM_MODE_DPMS_OFF);
+ break;
+ }
+ return 0;
+}
+
+static struct fb_ops glamofb_ops = {
+ .owner = THIS_MODULE,
+ .fb_check_var = glamofb_check_var,
+ .fb_set_par = glamofb_set_par,
+ .fb_setcolreg = glamofb_setcolreg,
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+ .fb_pan_display = glamofb_pan_display,
+ .fb_blank = glamofb_blank,
+};
+
+
+#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
+
+
+/* Here, we create a GEM object of the correct size, and then turn it into
+ * /dev/fbX so that the kernel can put a console on it. */
+int glamofb_create(struct drm_device *dev, uint32_t fb_width,
+ uint32_t fb_height, uint32_t surface_width,
+ uint32_t surface_height, int colour_mode,
+ struct glamo_framebuffer **glamo_fb_p)
+{
+ struct fb_info *info;
+ struct glamofb_par *par;
+ struct drm_framebuffer *fb;
+ struct glamo_framebuffer *glamo_fb;
+ struct drm_mode_fb_cmd mode_cmd;
+ struct drm_gem_object *fbo = NULL;
+ struct drm_glamo_gem_object *gobj;
+ struct device *device = &dev->platform_dev->dev;
+ struct glamodrm_handle *gdrm;
+ int size, ret;
+ unsigned long offs;
+
+ gdrm = dev->dev_private;
+
+ mode_cmd.width = surface_width;
+ mode_cmd.height = surface_height;
+
+ mode_cmd.bpp = 16;
+ mode_cmd.pitch = ALIGN(mode_cmd.width * ((mode_cmd.bpp + 1) / 8), 64);
+ mode_cmd.depth = 16;
+
+ size = mode_cmd.pitch * mode_cmd.height;
+ size = ALIGN(size, PAGE_SIZE);
+ if ( size > GLAMO_FRAMEBUFFER_ALLOCATION ) {
+ printk(KERN_ERR "[glamo-drm] Not enough memory for fb\n");
+ ret = -ENOMEM;
+ goto out;
+ }
+ fbo = glamo_gem_object_alloc(dev, GLAMO_FRAMEBUFFER_ALLOCATION, 2);
+ if (!fbo) {
+ printk(KERN_ERR "[glamo-drm] Failed to allocate framebuffer\n");
+ ret = -ENOMEM;
+ goto out;
+ }
+ gobj = fbo->driver_private;
+
+ mutex_lock(&dev->struct_mutex);
+
+ ret = glamo_framebuffer_create(dev, &mode_cmd, &fb, fbo);
+ if (ret) {
+ DRM_ERROR("failed to allocate fb.\n");
+ goto out_unref;
+ }
+
+ list_add(&fb->filp_head, &dev->mode_config.fb_kernel_list);
+
+ glamo_fb = to_glamo_framebuffer(fb);
+ *glamo_fb_p = glamo_fb;
+
+ info = framebuffer_alloc(sizeof(struct glamofb_par), device);
+ if (!info) {
+ ret = -ENOMEM;
+ goto out_unref;
+ }
+
+ par = info->par;
+
+ strcpy(info->fix.id, "glamodrmfb");
+ info->fix.type = FB_TYPE_PACKED_PIXELS;
+ info->fix.visual = FB_VISUAL_TRUECOLOR;
+ info->fix.type_aux = 0;
+ info->fix.xpanstep = 1; /* doing it in hw */
+ info->fix.ypanstep = 1; /* doing it in hw */
+ info->fix.ywrapstep = 0;
+ info->fix.accel = FB_ACCEL_GLAMO;
+ info->fix.type_aux = 0;
+ info->flags = FBINFO_DEFAULT;
+
+ info->fbops = &glamofb_ops;
+
+ info->fix.line_length = fb->pitch;
+
+ info->flags = FBINFO_DEFAULT;
+
+ offs = gobj->block->start;
+ info->screen_base = ioremap(gdrm->vram->start + offs + GLAMO_OFFSET_FB,
+ GLAMO_FRAMEBUFFER_ALLOCATION);
+ if (!info->screen_base) {
+ printk(KERN_ERR "[glamo-drm] Couldn't map framebuffer!\n");
+ ret = -ENOSPC;
+ goto out_unref;
+ }
+ info->fix.smem_start = (unsigned long)gdrm->vram->start + offs;
+ info->fix.smem_len = size;
+ info->screen_size = size;
+
+ info->pseudo_palette = fb->pseudo_palette;
+ info->var.xres_virtual = fb->width;
+ info->var.yres_virtual = fb->height;
+ info->var.bits_per_pixel = fb->bits_per_pixel;
+ info->var.xoffset = 0;
+ info->var.yoffset = 0;
+ info->var.activate = FB_ACTIVATE_NOW;
+ info->var.height = -1;
+ info->var.width = -1;
+ info->var.xres = fb_width;
+ info->var.yres = fb_height;
+
+ info->fix.mmio_start = 0;
+ info->fix.mmio_len = 0;
+
+ info->pixmap.size = 64*1024;
+ info->pixmap.buf_align = 8;
+ info->pixmap.access_align = 32;
+ info->pixmap.flags = FB_PIXMAP_SYSTEM;
+ info->pixmap.scan_align = 1;
+
+ switch (fb->depth) {
+ case 16:
+ switch ( colour_mode ) {
+ case GLAMO_FB_RGB565:
+ info->var.red.offset = 11;
+ info->var.green.offset = 5;
+ info->var.blue.offset = 0;
+ info->var.red.length = 5;
+ info->var.green.length = 6;
+ info->var.blue.length = 5;
+ info->var.transp.length = 0;
+ break;
+ case GLAMO_FB_ARGB1555:
+ info->var.transp.offset = 15;
+ info->var.red.offset = 10;
+ info->var.green.offset = 5;
+ info->var.blue.offset = 0;
+ info->var.transp.length = 1;
+ info->var.red.length = 5;
+ info->var.green.length = 5;
+ info->var.blue.length = 5;
+ break;
+ case GLAMO_FB_ARGB4444:
+ info->var.transp.offset = 12;
+ info->var.red.offset = 8;
+ info->var.green.offset = 4;
+ info->var.blue.offset = 0;
+ info->var.transp.length = 4;
+ info->var.red.length = 4;
+ info->var.green.length = 4;
+ info->var.blue.length = 4;
+ break;
+ }
+ break;
+ case 24:
+ case 32:
+ default:
+ /* The Smedia Glamo doesn't support anything but 16bit color */
+ printk(KERN_ERR "[glamo-drm] Only 16bpp is supported.\n");
+ return -EINVAL;
+ }
+
+ fb->fbdev = info;
+ par->glamo_fb = glamo_fb;
+ par->dev = dev;
+ gdrm->fb = info;
+
+ info->var.pixclock = -1;
+
+ printk(KERN_INFO "[glamo-drm] Allocated %dx%d fb: bo %p\n",
+ glamo_fb->base.width, glamo_fb->base.height, fbo);
+ mutex_unlock(&dev->struct_mutex);
+ return 0;
+
+out_unref:
+ drm_gem_object_unreference(fbo);
+ mutex_unlock(&dev->struct_mutex);
+out:
+ return ret;
+}
+
+
+void glamo_kmsfb_suspend(struct glamodrm_handle *gdrm)
+{
+ fb_set_suspend(gdrm->fb, 1);
+}
+
+
+void glamo_kmsfb_resume(struct glamodrm_handle *gdrm)
+{
+ fb_set_suspend(gdrm->fb, 0);
+}
diff --git a/drivers/mfd/glamo/glamo-kms-fb.h b/drivers/mfd/glamo/glamo-kms-fb.h
new file mode 100644
index 00000000000..1960e766fe1
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-kms-fb.h
@@ -0,0 +1,41 @@
+/*
+ * SMedia Glamo 336x/337x KMS framebuffer
+ *
+ * Copyright (C) 2009 Thomas White <taw@bitwiz.org.uk>
+ *
+ * Based on glamo-fb.c (C) 2007-2008 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __GLAMO_KMS_FB_H
+#define __GLAMO_KMS_FB_H
+
+#include <drm/drmP.h>
+#include "glamo-drm-private.h"
+
+extern int glamofb_create(struct drm_device *dev, uint32_t fb_width,
+ uint32_t fb_height, uint32_t surface_width,
+ uint32_t surface_height, int colour_mode,
+ struct glamo_framebuffer **glamo_fb_p);
+
+extern void glamo_kmsfb_suspend(struct glamodrm_handle *gdrm);
+extern void glamo_kmsfb_resume(struct glamodrm_handle *gdrm);
+
+#endif /* __GLAMO_KMS_FB_H */
diff --git a/drivers/mfd/glamo/glamo-mci.c b/drivers/mfd/glamo/glamo-mci.c
index acf16360cfd..a3b4c5e4962 100644
--- a/drivers/mfd/glamo/glamo-mci.c
+++ b/drivers/mfd/glamo/glamo-mci.c
@@ -573,15 +573,15 @@ static int glamo_mci_prepare_pio(struct glamo_mci_host *host,
* Read is halfway up the buffer and write is at the start
*/
if (data->flags & MMC_DATA_READ) {
- writew((u16)(GLAMO_FB_SIZE + (RESSIZE(host->mem_data) / 2)),
+ writew((u16)(GLAMO_OFFSET_MMC + (RESSIZE(host->mem_data) / 2)),
host->base + GLAMO_REG_MMC_WDATADS1);
- writew((u16)((GLAMO_FB_SIZE +
+ writew((u16)((GLAMO_OFFSET_MMC +
(RESSIZE(host->mem_data) / 2)) >> 16),
host->base + GLAMO_REG_MMC_WDATADS2);
} else {
- writew((u16)GLAMO_FB_SIZE, host->base +
+ writew((u16)GLAMO_OFFSET_MMC, host->base +
GLAMO_REG_MMC_RDATADS1);
- writew((u16)(GLAMO_FB_SIZE >> 16), host->base +
+ writew((u16)(GLAMO_OFFSET_MMC >> 16), host->base +
GLAMO_REG_MMC_RDATADS2);
}
diff --git a/drivers/mfd/glamo/glamo-regs.h b/drivers/mfd/glamo/glamo-regs.h
index 2328b8ac989..7876cdff1fe 100644
--- a/drivers/mfd/glamo/glamo-regs.h
+++ b/drivers/mfd/glamo/glamo-regs.h
@@ -629,4 +629,28 @@ enum glamo_core_revisions {
GLAMO_CORE_REV_A3 = 0x0003,
};
+enum glamo_register_cq {
+ GLAMO_REG_CMDQ_BASE_ADDRL = 0x00,
+ GLAMO_REG_CMDQ_BASE_ADDRH = 0x02,
+ GLAMO_REG_CMDQ_LEN = 0x04,
+ GLAMO_REG_CMDQ_WRITE_ADDRL = 0x06,
+ GLAMO_REG_CMDQ_WRITE_ADDRH = 0x08,
+ GLAMO_REG_CMDQ_FLIP = 0x0a,
+ GLAMO_REG_CMDQ_CONTROL = 0x0c,
+ GLAMO_REG_CMDQ_READ_ADDRL = 0x0e,
+ GLAMO_REG_CMDQ_READ_ADDRH = 0x10,
+ GLAMO_REG_CMDQ_STATUS = 0x12,
+};
+
+#define REG_2D(x) (GLAMO_REGOFS_2D+(x))
+
+enum glamo_register_2d {
+ GLAMO_REG_2D_DST_X = REG_2D(0x0a),
+ GLAMO_REG_2D_COMMAND1 = REG_2D(0x3a),
+ GLAMO_REG_2D_STATUS = REG_2D(0x42),
+ GLAMO_REG_2D_ID1 = REG_2D(0x44),
+ GLAMO_REG_2D_ID2 = REG_2D(0x46),
+ GLAMO_REG_2D_ID3 = REG_2D(0x48),
+};
+
#endif /* _GLAMO_REGS_H */
diff --git a/drivers/video/display/jbt6k74.c b/drivers/video/display/jbt6k74.c
index 5d7a6519de9..fba69b52f17 100644
--- a/drivers/video/display/jbt6k74.c
+++ b/drivers/video/display/jbt6k74.c
@@ -622,6 +622,21 @@ static int fb_notifier_callback(struct notifier_block *self,
return 0;
}
+struct jbt_info *jbt_global;
+void jbt6k74_action(int val)
+{
+ if ( !jbt_global ) {
+ printk(KERN_CRIT "JBT not initialised!!!\n");
+ return;
+ }
+ if ( val == 0 ) {
+ jbt6k74_enter_state(jbt_global, JBT_STATE_SLEEP);
+ } else {
+ jbt6k74_enter_state(jbt_global, jbt_global->normal_state);
+ }
+}
+EXPORT_SYMBOL_GPL(jbt6k74_action);
+
/* linux device model infrastructure */
static int __devinit jbt_probe(struct spi_device *spi)
@@ -646,6 +661,8 @@ static int __devinit jbt_probe(struct spi_device *spi)
if (!jbt)
return -ENOMEM;
+ jbt_global = jbt;
+
jbt->spi_dev = spi;
jbt->normal_state = JBT_STATE_NORMAL;
jbt->state = JBT_STATE_DEEP_STANDBY;
diff --git a/include/drm/Kbuild b/include/drm/Kbuild
index b940fdfa3b2..48b7b5533f1 100644
--- a/include/drm/Kbuild
+++ b/include/drm/Kbuild
@@ -8,3 +8,4 @@ unifdef-y += radeon_drm.h
unifdef-y += sis_drm.h
unifdef-y += savage_drm.h
unifdef-y += via_drm.h
+unifdef-y += glamo_drm.h
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 8190b9bcc2d..6e14efad777 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -58,6 +58,7 @@
#include <linux/mm.h>
#include <linux/cdev.h>
#include <linux/mutex.h>
+#include <linux/platform_device.h>
#if defined(__alpha__) || defined(__powerpc__)
#include <asm/pgtable.h> /* For pte_wrprotect */
#endif
@@ -106,6 +107,7 @@ struct drm_device;
#define DRIVER_IRQ_VBL2 0x800
#define DRIVER_GEM 0x1000
#define DRIVER_MODESET 0x2000
+#define DRIVER_IS_PLATFORM 0x4000
/***********************************************************************/
/** \name Begin the DRM... */
@@ -916,6 +918,7 @@ struct drm_device {
wait_queue_head_t buf_writers; /**< Processes waiting to ctx switch */
struct drm_agp_head *agp; /**< AGP data */
+ struct platform_device *platform_dev; /**< platform device structure */
struct pci_dev *pdev; /**< PCI device structure */
int pci_vendor; /**< PCI vendor id */
@@ -1026,12 +1029,20 @@ static inline int drm_mtrr_del(int handle, unsigned long offset,
}
#endif
+static inline int drm_core_is_platform(struct drm_device *dev)
+{
+ return drm_core_check_feature(dev, DRIVER_IS_PLATFORM);
+}
+
/******************************************************************/
/** \name Internal function definitions */
/*@{*/
/* Driver support (drm_drv.h) */
extern int drm_init(struct drm_driver *driver);
+extern int drm_platform_init(struct drm_driver *driver,
+ struct platform_device *pdev,
+ void *dev_private);
extern void drm_exit(struct drm_driver *driver);
extern int drm_ioctl(struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg);
@@ -1252,6 +1263,8 @@ extern struct drm_master *drm_master_get(struct drm_master *master);
extern void drm_master_put(struct drm_master **master);
extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
struct drm_driver *driver);
+extern int drm_get_platform_dev(struct platform_device *pdev,
+ struct drm_driver *driver, void *priv);
extern int drm_put_dev(struct drm_device *dev);
extern int drm_put_minor(struct drm_minor **minor);
extern unsigned int drm_debug;
diff --git a/include/drm/glamo_drm.h b/include/drm/glamo_drm.h
new file mode 100644
index 00000000000..4c194dcdf7d
--- /dev/null
+++ b/include/drm/glamo_drm.h
@@ -0,0 +1,153 @@
+/* glamo_drm.h -- Public header for the Glamo driver
+ *
+ * Copyright 2009 Thomas White
+ * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
+ * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
+ * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Thomas White <taw@bitwiz.org.uk>
+ * Kevin E. Martin <martin@valinux.com>
+ * Gareth Hughes <gareth@valinux.com>
+ * Keith Whitwell <keith@tungstengraphics.com>
+ */
+
+#ifndef __GLAMO_DRM_H__
+#define __GLAMO_DRM_H__
+
+#include "drm.h"
+
+#define GLAMO_GEM_DOMAIN_VRAM (0x1)
+
+/* Glamo specific ioctls */
+#define DRM_GLAMO_CMDBUF 0x01
+#define DRM_GLAMO_SWAP 0x02
+#define DRM_GLAMO_CMDBURST 0x03
+
+#define DRM_GLAMO_GEM_INFO 0x1c
+#define DRM_GLAMO_GEM_CREATE 0x1d
+#define DRM_GLAMO_GEM_MMAP 0x1e
+#define DRM_GLAMO_GEM_PIN 0x1f
+#define DRM_GLAMO_GEM_UNPIN 0x20
+#define DRM_GLAMO_GEM_PREAD 0x21
+#define DRM_GLAMO_GEM_PWRITE 0x22
+#define DRM_GLAMO_GEM_WAIT_RENDERING 0x24
+
+#define DRM_IOCTL_GLAMO_CMDBUF DRM_IOW(DRM_COMMAND_BASE + DRM_GLAMO_CMDBUF, drm_glamo_cmd_buffer_t)
+#define DRM_IOCTL_GLAMO_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_GLAMO_SWAP)
+#define DRM_IOCTL_GLAMO_CMDBURST DRM_IOW(DRM_COMMAND_BASE + DRM_GLAMO_CMDBURST, drm_glamo_cmd_burst_t)
+
+#define DRM_IOCTL_GLAMO_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_GLAMO_GEM_INFO, struct drm_glamo_gem_info)
+#define DRM_IOCTL_GLAMO_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_GLAMO_GEM_CREATE, struct drm_glamo_gem_create)
+#define DRM_IOCTL_GLAMO_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_GLAMO_GEM_MMAP, struct drm_glamo_gem_mmap)
+#define DRM_IOCTL_GLAMO_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_GLAMO_GEM_PIN, struct drm_glamo_gem_pin)
+#define DRM_IOCTL_GLAMO_GEM_UNPIN DRM_IOWR(DRM_COMMAND_BASE + DRM_GLAMO_GEM_UNPIN, struct drm_glamo_gem_unpin)
+#define DRM_IOCTL_GLAMO_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_GLAMO_GEM_PREAD, struct drm_glamo_gem_pread)
+#define DRM_IOCTL_GLAMO_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_GLAMO_GEM_PWRITE, struct drm_glamo_gem_pwrite)
+#define DRM_IOCTL_GLAMO_GEM_WAIT_RENDERING DRM_IOW(DRM_COMMAND_BASE + DRM_GLAMO_GEM_WAIT_RENDERING, struct drm_glamo_gem_wait_rendering)
+
+
+/* Simple command submission - a list of 16-bit address-data pairs */
+typedef struct drm_glamo_cmd_buffer {
+ unsigned int bufsz; /* Size of buffer, in bytes */
+ char __user *buf; /* Buffer of stuff to go onto the ring buffer */
+ unsigned int *obj_pos; /* Offsets (in bytes) at which to put objs */
+ uint32_t *objs; /* List of buffer object (handles) to use */
+ unsigned int nobjs; /* Number of objects referenced */
+ int nbox;
+ struct drm_clip_rect __user *boxes;
+} drm_glamo_cmd_buffer_t;
+
+
+/* Burst command submission - base address and data:
+ * - Data can be 32-bit (more easily)
+ * - Easier for the kernel to validate */
+typedef struct drm_glamo_cmd_burst {
+ uint16_t base; /* Base address (command) */
+ int bufsz; /* Size of data, in bytes */
+ uint16_t *data; /* Pointer to data */
+ unsigned int *obj_pos; /* Offsets (in bytes) at which to put objs */
+ uint32_t *objs; /* List of buffer object (handles) to use */
+ unsigned int nobjs; /* Number of objects referenced */
+} drm_glamo_cmd_burst_t;
+
+struct drm_glamo_gem_info {
+ uint64_t vram_start;
+ uint64_t vram_size;
+};
+
+struct drm_glamo_gem_create {
+ uint64_t size;
+ uint64_t alignment;
+ uint32_t handle;
+ uint32_t initial_domain; // to allow VRAM to be created
+ uint32_t no_backing_store;
+};
+
+struct drm_glamo_gem_mmap {
+ uint32_t handle; /* Handle goes in... */
+ uint64_t offset; /* ...offset comes out */
+};
+
+struct drm_glamo_gem_wait_rendering {
+ uint32_t handle;
+ int have_handle;
+};
+
+struct drm_glamo_gem_pin {
+ uint32_t handle;
+ uint32_t pin_domain;
+ uint64_t alignment;
+ uint64_t offset;
+};
+
+struct drm_glamo_gem_unpin {
+ uint32_t handle;
+ uint32_t pad;
+};
+
+struct drm_glamo_gem_pread {
+ /** Handle for the object being read. */
+ uint32_t handle;
+ uint32_t pad;
+ /** Offset into the object to read from */
+ uint64_t offset;
+ /** Length of data to read */
+ uint64_t size;
+ /** Pointer to write the data into. */
+ uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */
+};
+
+struct drm_glamo_gem_pwrite {
+ /** Handle for the object being written to. */
+ uint32_t handle;
+ uint32_t pad;
+ /** Offset into the object to write to */
+ uint64_t offset;
+ /** Length of data to write */
+ uint64_t size;
+ /** Pointer to read the data from. */
+ uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */
+};
+
+#endif