diff options
Diffstat (limited to 'arch/arm/mach-stmp37xx/include/mach/regs-apbx.h')
| -rw-r--r-- | arch/arm/mach-stmp37xx/include/mach/regs-apbx.h | 172 |
1 files changed, 88 insertions, 84 deletions
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h index a14ddb97639..6d080cd5b70 100644 --- a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h +++ b/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h @@ -1,5 +1,5 @@ /* - * STMP APBX Register Definitions + * stmp37xx: APBX register definitions * * Copyright (c) 2008 Freescale Semiconductor * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. @@ -18,92 +18,96 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef _INCLUDE_ASM_ARCH_REGS_APBX_H -#define _INCLUDE_ASM_ARCH_REGS_APBX_H +#ifndef _MACH_REGS_APBX +#define _MACH_REGS_APBX -#include <mach/stmp3xxx_regs.h> +#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000) -#ifndef REGS_APBX_BASE -#define REGS_APBX_BASE (REGS_BASE + 0x00024000) -#endif +#define HW_APBX_CTRL0 0x0 +#define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000 +#define BP_APBX_CTRL0_RESET_CHANNEL 16 +#define BM_APBX_CTRL0_CLKGATE 0x40000000 +#define BM_APBX_CTRL0_SFTRST 0x80000000 + +#define HW_APBX_CTRL1 0x10 + +#define HW_APBX_DEVSEL 0x20 + +#define HW_APBX_CH0_NXTCMDAR (0x50 + 0 * 0x70) +#define HW_APBX_CH1_NXTCMDAR (0x50 + 1 * 0x70) +#define HW_APBX_CH2_NXTCMDAR (0x50 + 2 * 0x70) +#define HW_APBX_CH3_NXTCMDAR (0x50 + 3 * 0x70) +#define HW_APBX_CH4_NXTCMDAR (0x50 + 4 * 0x70) +#define HW_APBX_CH5_NXTCMDAR (0x50 + 5 * 0x70) +#define HW_APBX_CH6_NXTCMDAR (0x50 + 6 * 0x70) +#define HW_APBX_CH7_NXTCMDAR (0x50 + 7 * 0x70) +#define HW_APBX_CH8_NXTCMDAR (0x50 + 8 * 0x70) +#define HW_APBX_CH9_NXTCMDAR (0x50 + 9 * 0x70) +#define HW_APBX_CH10_NXTCMDAR (0x50 + 10 * 0x70) +#define HW_APBX_CH11_NXTCMDAR (0x50 + 11 * 0x70) +#define HW_APBX_CH12_NXTCMDAR (0x50 + 12 * 0x70) +#define HW_APBX_CH13_NXTCMDAR (0x50 + 13 * 0x70) +#define HW_APBX_CH14_NXTCMDAR (0x50 + 14 * 0x70) +#define HW_APBX_CH15_NXTCMDAR (0x50 + 15 * 0x70) -HW_REGISTER(HW_APBX_CTRL0, REGS_APBX_BASE, 0x00) -#define BP_APBX_CTRL0_SFTRST 31 -#define BM_APBX_CTRL0_SFTRST 0x80000000 -#define BP_APBX_CTRL0_CLKGATE 30 -#define BM_APBX_CTRL0_CLKGATE 0x40000000 -#define BP_APBX_CTRL0_RESET_CHANNEL 16 -#define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000 -#define BF_APBX_CTRL0_RESET_CHANNEL(v) \ - (((v) << BP_APBX_CTRL0_RESET_CHANNEL) & BM_APBX_CTRL0_RESET_CHANNEL) -HW_REGISTER(HW_APBX_CTRL1, REGS_APBX_BASE, 0x10) -HW_REGISTER_0(HW_APBX_DEVSEL, REGS_APBX_BASE, 0x20) -#define BP_APBX_DEVSEL_CH7 28 -#define BM_APBX_DEVSEL_CH7 0xF0000000 -#define BF_APBX_DEVSEL_CH7(v) \ - (((v) << BP_APBX_DEVSEL_CH7) & BM_APBX_DEVSEL_CH7) -#define BV_APBX_DEVSEL_CH7__USE_UART 0x0 -#define BV_APBX_DEVSEL_CH7__USE_IRDA 0x1 -#define BP_APBX_DEVSEL_CH6 24 -#define BM_APBX_DEVSEL_CH6 0x0F000000 -#define BF_APBX_DEVSEL_CH6(v) \ - (((v) << BP_APBX_DEVSEL_CH6) & BM_APBX_DEVSEL_CH6) -#define BV_APBX_DEVSEL_CH6__USE_UART 0x0 -#define BV_APBX_DEVSEL_CH6__USE_IRDA 0x1 -#define BP_APBX_CTRL1_CH7_AHB_ERROR_IRQ 23 -#define BM_APBX_CTRL1_CH7_AHB_ERROR_IRQ 0x00800000 -#define BP_APBX_CTRL1_CH6_AHB_ERROR_IRQ 22 -#define BM_APBX_CTRL1_CH6_AHB_ERROR_IRQ 0x00400000 -#define BP_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN 15 -#define BM_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00008000 -#define BP_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN 14 -#define BM_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00004000 +#define HW_APBX_CHn_NXTCMDAR 0x50 +#define BM_APBX_CHn_CMD_MODE 0x00000003 +#define BP_APBX_CHn_CMD_MODE 0x00000001 +#define BV_APBX_CHn_CMD_MODE_NOOP 0 +#define BV_APBX_CHn_CMD_MODE_WRITE 1 +#define BV_APBX_CHn_CMD_MODE_READ 2 +#define BV_APBX_CHn_CMD_MODE_SENSE 3 +#define BM_APBX_CHn_CMD_COMMAND 0x00000003 +#define BP_APBX_CHn_CMD_COMMAND 0 +#define BM_APBX_CHn_CMD_CHAIN 0x00000004 +#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 +#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 +#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 +#define BP_APBX_CHn_CMD_CMDWORDS 12 +#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BP_APBX_CHn_CMD_XFER_COUNT 16 -HW_REGISTER_RO_INDEXED(HW_APBX_CHn_CURCMDAR, REGS_APBX_BASE, 0x40, 0x70) -HW_REGISTER_0_INDEXED(HW_APBX_CHn_NXTCMDAR, REGS_APBX_BASE, 0x50, 0x70) -#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR 0 -#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF -#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v) ((u32) v) -HW_REGISTER_RO_INDEXED(HW_APBX_CHn_CMD, REGS_APBX_BASE, 0x60, 0x70) -#define BP_APBX_CHn_CMD_XFER_COUNT 16 -#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 -#define BF_APBX_CHn_CMD_XFER_COUNT(v) \ - (((v) << BP_APBX_CHn_CMD_XFER_COUNT) & BM_APBX_CHn_CMD_XFER_COUNT) -#define BP_APBX_CHn_CMD_CMDWORDS 12 -#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 -#define BF_APBX_CHn_CMD_CMDWORDS(v) \ - (((v) << BP_APBX_CHn_CMD_CMDWORDS) & BM_APBX_CHn_CMD_CMDWORDS) -#define BP_APBX_CHn_CMD_WAIT4ENDCMD 7 -#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 -#define BP_APBX_CHn_CMD_SEMAPHORE 6 -#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 -#define BP_APBX_CHn_CMD_IRQONCMPLT 3 -#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 -#define BP_APBX_CHn_CMD_CHAIN 2 -#define BM_APBX_CHn_CMD_CHAIN 0x00000004 -#define BM_APBX_CHn_CMD_DMA_READ 0x00000003 -#define BP_APBX_CHn_CMD_DMA_READ 0 -#define BF_APBX_CHn_CMD_DMA_READ(v) \ - (((v) << BP_APBX_CHn_CMD_DMA_READ) & BM_APBX_CHn_CMD_DMA_READ) -#define BP_APBX_CHn_CMD_COMMAND 0 -#define BM_APBX_CHn_CMD_COMMAND 0x00000003 -#define BF_APBX_CHn_CMD_COMMAND(v) \ - (((v) << BP_APBX_CHn_CMD_COMMAND) & BM_APBX_CHn_CMD_COMMAND) -#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 -#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1 -#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2 +#define HW_APBX_CH0_BAR (0x70 + 0 * 0x70) +#define HW_APBX_CH1_BAR (0x70 + 1 * 0x70) +#define HW_APBX_CH2_BAR (0x70 + 2 * 0x70) +#define HW_APBX_CH3_BAR (0x70 + 3 * 0x70) +#define HW_APBX_CH4_BAR (0x70 + 4 * 0x70) +#define HW_APBX_CH5_BAR (0x70 + 5 * 0x70) +#define HW_APBX_CH6_BAR (0x70 + 6 * 0x70) +#define HW_APBX_CH7_BAR (0x70 + 7 * 0x70) +#define HW_APBX_CH8_BAR (0x70 + 8 * 0x70) +#define HW_APBX_CH9_BAR (0x70 + 9 * 0x70) +#define HW_APBX_CH10_BAR (0x70 + 10 * 0x70) +#define HW_APBX_CH11_BAR (0x70 + 11 * 0x70) +#define HW_APBX_CH12_BAR (0x70 + 12 * 0x70) +#define HW_APBX_CH13_BAR (0x70 + 13 * 0x70) +#define HW_APBX_CH14_BAR (0x70 + 14 * 0x70) +#define HW_APBX_CH15_BAR (0x70 + 15 * 0x70) -HW_REGISTER_RO_INDEXED(HW_APBX_CHn_BAR, REGS_APBX_BASE, 0x70, 0x70) -HW_REGISTER_0_INDEXED(HW_APBX_CHn_SEMA, REGS_APBX_BASE, 0x80, 0x70) -#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 -#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF -#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) \ - (((v) << BP_APBX_CHn_SEMA_INCREMENT_SEMA) & \ - BM_APBX_CHn_SEMA_INCREMENT_SEMA) -#define BP_APBX_CHn_SEMA_PHORE 16 -#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 -HW_REGISTER_RO_INDEXED(HW_APBX_CHn_DEBUG1, REGS_APBX_BASE, 0x90, 0x70) -HW_REGISTER_RO_INDEXED(HW_APBX_CHn_DEBUG2, REGS_APBX_BASE, 0xA0, 0x70) -HW_REGISTER_RO(HW_APBX_VERSION, REGS_APBX_BASE, 0x3F0) +#define HW_APBX_CHn_BAR 0x70 -#endif /* _INCLUDE_ASM_ARCH_REGS_APBX_H */ +#define HW_APBX_CH0_SEMA (0x80 + 0 * 0x70) +#define HW_APBX_CH1_SEMA (0x80 + 1 * 0x70) +#define HW_APBX_CH2_SEMA (0x80 + 2 * 0x70) +#define HW_APBX_CH3_SEMA (0x80 + 3 * 0x70) +#define HW_APBX_CH4_SEMA (0x80 + 4 * 0x70) +#define HW_APBX_CH5_SEMA (0x80 + 5 * 0x70) +#define HW_APBX_CH6_SEMA (0x80 + 6 * 0x70) +#define HW_APBX_CH7_SEMA (0x80 + 7 * 0x70) +#define HW_APBX_CH8_SEMA (0x80 + 8 * 0x70) +#define HW_APBX_CH9_SEMA (0x80 + 9 * 0x70) +#define HW_APBX_CH10_SEMA (0x80 + 10 * 0x70) +#define HW_APBX_CH11_SEMA (0x80 + 11 * 0x70) +#define HW_APBX_CH12_SEMA (0x80 + 12 * 0x70) +#define HW_APBX_CH13_SEMA (0x80 + 13 * 0x70) +#define HW_APBX_CH14_SEMA (0x80 + 14 * 0x70) +#define HW_APBX_CH15_SEMA (0x80 + 15 * 0x70) + +#define HW_APBX_CHn_SEMA 0x80 +#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 +#define BP_APBX_CHn_SEMA_PHORE 16 + +#endif |