diff options
Diffstat (limited to 'arch/arm')
164 files changed, 12724 insertions, 5293 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9d02cdb15b2..65bf774a26f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -253,6 +253,14 @@ config ARCH_CLPS711X help Support for Cirrus Logic 711x/721x based boards. +config ARCH_GEMINI + bool "Cortina Systems Gemini" + select CPU_FA526 + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + help + Support for the Cortina Systems Gemini family SoCs + config ARCH_EBSA110 bool "EBSA-110" select CPU_SA110 @@ -277,14 +285,6 @@ config ARCH_EP93XX help This enables support for the Cirrus EP93xx series of CPUs. -config ARCH_GEMINI - bool "Cortina Systems Gemini" - select CPU_FA526 - select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB - help - Support for the Cortina Systems Gemini family SoCs - config ARCH_FOOTBRIDGE bool "FootBridge" select CPU_SA110 @@ -293,6 +293,17 @@ config ARCH_FOOTBRIDGE Support for systems based on the DC21285 companion chip ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. +config ARCH_MXC + bool "Freescale MXC/iMX-based" + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select ARCH_MTD_XIP + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + select HAVE_CLK + help + Support for Freescale MXC/iMX-based family of processors + config ARCH_NETX bool "Hilscher NetX based" select CPU_ARM926T @@ -309,15 +320,6 @@ config ARCH_H720X help This enables support for systems based on the Hynix HMS720x -config ARCH_IMX - bool "IMX" - select CPU_ARM920T - select GENERIC_GPIO - select GENERIC_TIME - select GENERIC_CLOCKEVENTS - help - Support for Motorola's i.MX family of processors (MX1, MXL). - config ARCH_IOP13XX bool "IOP13xx-based" depends on MMU @@ -405,28 +407,6 @@ config ARCH_KIRKWOOD Support for the following Marvell Kirkwood series SoCs: 88F6180, 88F6192 and 88F6281. -config ARCH_KS8695 - bool "Micrel/Kendin KS8695" - select CPU_ARM922T - select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB - help - Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based - System-on-Chip devices. - -config ARCH_NS9XXX - bool "NetSilicon NS9xxx" - select CPU_ARM926T - select GENERIC_GPIO - select GENERIC_TIME - select GENERIC_CLOCKEVENTS - select HAVE_CLK - help - Say Y here if you intend to run this kernel on a NetSilicon NS9xxx - System. - - <http://www.digi.com/products/microprocessors/index.jsp> - config ARCH_LOKI bool "Marvell Loki (88RC8480)" select CPU_FEROCEON @@ -448,17 +428,6 @@ config ARCH_MV78XX0 Support for the following Marvell MV78xx0 series SoCs: MV781x0, MV782x0. -config ARCH_MXC - bool "Freescale MXC/iMX-based" - select GENERIC_TIME - select GENERIC_CLOCKEVENTS - select ARCH_MTD_XIP - select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB - select HAVE_CLK - help - Support for Freescale MXC/iMX-based family of processors - config ARCH_ORION5X bool "Marvell Orion" depends on MMU @@ -473,6 +442,49 @@ config ARCH_ORION5X Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), Orion-2 (5281), Orion-1-90 (6183). +config ARCH_MMP + bool "Marvell PXA168/910" + depends on MMU + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + select HAVE_CLK + select COMMON_CLKDEV + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select TICK_ONESHOT + select PLAT_PXA + help + Support for Marvell's PXA168/910 processor line. + +config ARCH_KS8695 + bool "Micrel/Kendin KS8695" + select CPU_ARM922T + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + help + Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based + System-on-Chip devices. + +config ARCH_NS9XXX + bool "NetSilicon NS9xxx" + select CPU_ARM926T + select GENERIC_GPIO + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select HAVE_CLK + help + Say Y here if you intend to run this kernel on a NetSilicon NS9xxx + System. + + <http://www.digi.com/products/microprocessors/index.jsp> + +config ARCH_W90X900 + bool "Nuvoton W90X900 CPU" + select CPU_ARM926T + help + Support for Nuvoton (Winbond logic dept.) ARM9 processor,You + can login www.mcuos.com or www.nuvoton.com to know more. + config ARCH_PNX4008 bool "Philips Nexperia PNX4008 Mobile" select CPU_ARM926T @@ -495,19 +507,16 @@ config ARCH_PXA help Support for Intel/Marvell's PXA2xx/PXA3xx processor line. -config ARCH_MMP - bool "Marvell PXA168/910" - depends on MMU - select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB - select HAVE_CLK - select COMMON_CLKDEV +config ARCH_MSM + bool "Qualcomm MSM" + select CPU_V6 select GENERIC_TIME select GENERIC_CLOCKEVENTS - select TICK_ONESHOT - select PLAT_PXA help - Support for Marvell's PXA168/910 processor line. + Support for Qualcomm MSM7K based systems. This runs on the ARM11 + apps processor of the MSM7K and depends on a shared memory + interface to the ARM9 modem processor which runs the baseband stack + and controls some vital subsystems (clock and power control, etc). config ARCH_RPC bool "RiscPC" @@ -587,6 +596,7 @@ config ARCH_DAVINCI select ZONE_DMA select HAVE_IDE select COMMON_CLKDEV + select GENERIC_ALLOCATOR help Support for TI's DaVinci platform. @@ -600,24 +610,6 @@ config ARCH_OMAP help Support for TI's OMAP platform (OMAP1 and OMAP2). -config ARCH_MSM - bool "Qualcomm MSM" - select CPU_V6 - select GENERIC_TIME - select GENERIC_CLOCKEVENTS - help - Support for Qualcomm MSM7K based systems. This runs on the ARM11 - apps processor of the MSM7K and depends on a shared memory - interface to the ARM9 modem processor which runs the baseband stack - and controls some vital subsystems (clock and power control, etc). - -config ARCH_W90X900 - bool "Nuvoton W90X900 CPU" - select CPU_ARM926T - help - Support for Nuvoton (Winbond logic dept.) ARM9 processor,You - can login www.mcuos.com or www.nuvoton.com to know more. - endchoice source "arch/arm/mach-clps711x/Kconfig" @@ -683,8 +675,6 @@ endif source "arch/arm/mach-lh7a40x/Kconfig" -source "arch/arm/mach-imx/Kconfig" - source "arch/arm/mach-h720x/Kconfig" source "arch/arm/mach-versatile/Kconfig" @@ -1022,7 +1012,7 @@ source "mm/Kconfig" config LEDS bool "Timer and CPU usage LEDs" depends on ARCH_CDB89712 || ARCH_EBSA110 || \ - ARCH_EBSA285 || ARCH_IMX || ARCH_INTEGRATOR || \ + ARCH_EBSA285 || ARCH_INTEGRATOR || \ ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ @@ -1188,7 +1178,7 @@ endmenu menu "CPU Power Management" -if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA) +if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA) source "drivers/cpufreq/Kconfig" @@ -1213,14 +1203,11 @@ config CPU_FREQ_INTEGRATOR If in doubt, say Y. -config CPU_FREQ_IMX - tristate "CPUfreq driver for i.MX CPUs" - depends on ARCH_IMX && CPU_FREQ - default n - help - This enables the CPUfreq driver for i.MX CPUs. - - If in doubt, say N. +config CPU_FREQ_PXA + bool + depends on CPU_FREQ && ARCH_PXA && PXA25x + default y + select CPU_FREQ_DEFAULT_GOV_USERSPACE endif diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 676d10d028b..e8ab87750e9 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -99,65 +99,69 @@ CHECKFLAGS += -D__arm__ #Default value head-y := arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o textofs-y := 0x00008000 - - machine-$(CONFIG_ARCH_RPC) := rpc - machine-$(CONFIG_ARCH_EBSA110) := ebsa110 - machine-$(CONFIG_FOOTBRIDGE) := footbridge - machine-$(CONFIG_ARCH_SHARK) := shark - machine-$(CONFIG_ARCH_SA1100) := sa1100 -ifeq ($(CONFIG_ARCH_SA1100),y) +textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 # SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory - textofs-$(CONFIG_SA1111) := 0x00208000 +ifeq ($(CONFIG_ARCH_SA1100),y) +textofs-$(CONFIG_SA1111) := 0x00208000 endif - machine-$(CONFIG_ARCH_PXA) := pxa - machine-$(CONFIG_ARCH_MMP) := mmp - plat-$(CONFIG_PLAT_PXA) := pxa - machine-$(CONFIG_ARCH_L7200) := l7200 - machine-$(CONFIG_ARCH_INTEGRATOR) := integrator - machine-$(CONFIG_ARCH_GEMINI) := gemini - textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 - machine-$(CONFIG_ARCH_CLPS711X) := clps711x - machine-$(CONFIG_ARCH_IOP32X) := iop32x - machine-$(CONFIG_ARCH_IOP33X) := iop33x - machine-$(CONFIG_ARCH_IOP13XX) := iop13xx - plat-$(CONFIG_PLAT_IOP) := iop - machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx - machine-$(CONFIG_ARCH_IXP2000) := ixp2000 - machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx - machine-$(CONFIG_ARCH_OMAP1) := omap1 - machine-$(CONFIG_ARCH_OMAP2) := omap2 - machine-$(CONFIG_ARCH_OMAP3) := omap2 - machine-$(CONFIG_ARCH_OMAP4) := omap2 - plat-$(CONFIG_ARCH_OMAP) := omap - machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 - machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 - plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c - machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 - plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c - machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x - machine-$(CONFIG_ARCH_VERSATILE) := versatile - machine-$(CONFIG_ARCH_IMX) := imx - machine-$(CONFIG_ARCH_H720X) := h720x - machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 - machine-$(CONFIG_ARCH_REALVIEW) := realview - machine-$(CONFIG_ARCH_AT91) := at91 - machine-$(CONFIG_ARCH_EP93XX) := ep93xx - machine-$(CONFIG_ARCH_PNX4008) := pnx4008 - machine-$(CONFIG_ARCH_NETX) := netx - machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx - machine-$(CONFIG_ARCH_DAVINCI) := davinci - machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood - machine-$(CONFIG_ARCH_KS8695) := ks8695 - plat-$(CONFIG_ARCH_MXC) := mxc - machine-$(CONFIG_ARCH_MX2) := mx2 - machine-$(CONFIG_ARCH_MX3) := mx3 - machine-$(CONFIG_ARCH_MX1) := mx1 - machine-$(CONFIG_ARCH_ORION5X) := orion5x - plat-$(CONFIG_PLAT_ORION) := orion - machine-$(CONFIG_ARCH_MSM) := msm - machine-$(CONFIG_ARCH_LOKI) := loki - machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 - machine-$(CONFIG_ARCH_W90X900) := w90x900 + +# Machine directory name. This list is sorted alphanumerically +# by CONFIG_* macro name. +machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 +machine-$(CONFIG_ARCH_AT91) := at91 +machine-$(CONFIG_ARCH_CLPS711X) := clps711x +machine-$(CONFIG_ARCH_DAVINCI) := davinci +machine-$(CONFIG_ARCH_EBSA110) := ebsa110 +machine-$(CONFIG_ARCH_EP93XX) := ep93xx +machine-$(CONFIG_ARCH_GEMINI) := gemini +machine-$(CONFIG_ARCH_H720X) := h720x +machine-$(CONFIG_ARCH_INTEGRATOR) := integrator +machine-$(CONFIG_ARCH_IOP13XX) := iop13xx +machine-$(CONFIG_ARCH_IOP32X) := iop32x +machine-$(CONFIG_ARCH_IOP33X) := iop33x +machine-$(CONFIG_ARCH_IXP2000) := ixp2000 +machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx +machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx +machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood +machine-$(CONFIG_ARCH_KS8695) := ks8695 +machine-$(CONFIG_ARCH_L7200) := l7200 +machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x +machine-$(CONFIG_ARCH_LOKI) := loki +machine-$(CONFIG_ARCH_MMP) := mmp +machine-$(CONFIG_ARCH_MSM) := msm +machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 +machine-$(CONFIG_ARCH_MX1) := mx1 +machine-$(CONFIG_ARCH_MX2) := mx2 +machine-$(CONFIG_ARCH_MX3) := mx3 +machine-$(CONFIG_ARCH_NETX) := netx +machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx +machine-$(CONFIG_ARCH_OMAP1) := omap1 +machine-$(CONFIG_ARCH_OMAP2) := omap2 +machine-$(CONFIG_ARCH_OMAP3) := omap2 +machine-$(CONFIG_ARCH_OMAP4) := omap2 +machine-$(CONFIG_ARCH_ORION5X) := orion5x +machine-$(CONFIG_ARCH_PNX4008) := pnx4008 +machine-$(CONFIG_ARCH_PXA) := pxa +machine-$(CONFIG_ARCH_REALVIEW) := realview +machine-$(CONFIG_ARCH_RPC) := rpc +machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 +machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 +machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 +machine-$(CONFIG_ARCH_SA1100) := sa1100 +machine-$(CONFIG_ARCH_SHARK) := shark +machine-$(CONFIG_ARCH_VERSATILE) := versatile +machine-$(CONFIG_ARCH_W90X900) := w90x900 +machine-$(CONFIG_FOOTBRIDGE) := footbridge + +# Platform directory name. This list is sorted alphanumerically +# by CONFIG_* macro name. +plat-$(CONFIG_ARCH_MXC) := mxc +plat-$(CONFIG_ARCH_OMAP) := omap +plat-$(CONFIG_PLAT_IOP) := iop +plat-$(CONFIG_PLAT_ORION) := orion +plat-$(CONFIG_PLAT_PXA) := pxa +plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c +plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c ifeq ($(CONFIG_ARCH_EBSA110),y) # This is what happens if you forget the IOCS16 line. diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig index eb2738b5be5..ac18662f38c 100644 --- a/arch/arm/configs/davinci_all_defconfig +++ b/arch/arm/configs/davinci_all_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30-rc2 -# Wed Apr 15 08:16:53 2009 +# Linux kernel version: 2.6.30-rc7 +# Tue May 26 07:24:28 2009 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -179,6 +179,7 @@ CONFIG_ARCH_DAVINCI=y # CONFIG_ARCH_OMAP is not set # CONFIG_ARCH_MSM is not set # CONFIG_ARCH_W90X900 is not set +CONFIG_AINTC=y # # TI DaVinci Implementations @@ -188,11 +189,17 @@ CONFIG_ARCH_DAVINCI=y # DaVinci Core Type # CONFIG_ARCH_DAVINCI_DM644x=y +CONFIG_ARCH_DAVINCI_DM355=y +CONFIG_ARCH_DAVINCI_DM646x=y # # DaVinci Board Type # CONFIG_MACH_DAVINCI_EVM=y +CONFIG_MACH_SFFSDR=y +CONFIG_MACH_DAVINCI_DM355_EVM=y +CONFIG_MACH_DM355_LEOPARD=y +CONFIG_MACH_DAVINCI_DM6467_EVM=y CONFIG_DAVINCI_MUX=y CONFIG_DAVINCI_MUX_DEBUG=y CONFIG_DAVINCI_MUX_WARNINGS=y @@ -245,7 +252,7 @@ CONFIG_PREEMPT=y CONFIG_HZ=100 CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set -CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set # CONFIG_HIGHMEM is not set @@ -661,7 +668,10 @@ CONFIG_NET_ETHERNET=y CONFIG_MII=y # CONFIG_AX88796 is not set # CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set +CONFIG_TI_DAVINCI_EMAC=y +CONFIG_DM9000=y +CONFIG_DM9000_DEBUGLEVEL=4 +# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set # CONFIG_ETHOC is not set # CONFIG_SMC911X is not set # CONFIG_SMSC911X is not set @@ -963,6 +973,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_ASIC3 is not set +# CONFIG_MFD_DM355EVM_MSP is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_TPS65010 is not set @@ -1317,6 +1328,7 @@ CONFIG_MMC_BLOCK=m # MMC/SD/SDIO Host Controller Drivers # # CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_DAVINCI is not set # CONFIG_MEMSTICK is not set # CONFIG_ACCESSIBILITY is not set CONFIG_NEW_LEDS=y @@ -1778,6 +1790,7 @@ CONFIG_CRC32=y CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mx21_defconfig b/arch/arm/configs/mx21_defconfig new file mode 100644 index 00000000000..4b04290d8e8 --- /dev/null +++ b/arch/arm/configs/mx21_defconfig @@ -0,0 +1,1170 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.30-rc1 +# Tue Apr 14 16:58:09 2009 +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_FREEZER is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +CONFIG_ARCH_MXC=y +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_W90X900 is not set + +# +# Freescale MXC Implementations +# +# CONFIG_ARCH_MX1 is not set +CONFIG_ARCH_MX2=y +# CONFIG_ARCH_MX3 is not set +CONFIG_MACH_MX21=y +# CONFIG_MACH_MX27 is not set + +# +# MX2 platforms: +# +CONFIG_MACH_MX21ADS=y +# CONFIG_MXC_IRQ_PRIOR is not set +CONFIG_MXC_PWM=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +# CONFIG_UNIX is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_OLD_REGULATORY is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_LIB80211 is not set +# CONFIG_MAC80211 is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +CONFIG_MTD_DEBUG=y +CONFIG_MTD_DEBUG_VERBOSE=3 +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_XIP is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +CONFIG_MTD_NAND_MXC=y +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ISL29003 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_COMPAT_NET_DEV_OPS=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +CONFIG_CS89x0=y +CONFIG_CS89x0_NONISA_IRQ=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +# CONFIG_CONSOLE_TRANSLATIONS is not set +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_IMX=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_IMX=y +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +# CONFIG_FONT_8x16 is not set +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_MXC=y +# CONFIG_MMC_SPI is not set +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +# CONFIG_VFAT_FS is not set +CONFIG_FAT_DEFAULT_CODEPAGE=437 +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_EVENT_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h index 58cf91f38e6..742c2aaeb02 100644 --- a/arch/arm/include/asm/mach/map.h +++ b/arch/arm/include/asm/mach/map.h @@ -30,6 +30,14 @@ struct map_desc { #ifdef CONFIG_MMU extern void iotable_init(struct map_desc *, int); + +struct mem_type; +extern const struct mem_type *get_mem_type(unsigned int type); +/* + * external interface to remap single page with appropriate type + */ +extern int ioremap_page(unsigned long virt, unsigned long phys, + const struct mem_type *mtype); #else #define iotable_init(map,num) do { } while (0) #endif diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index 110295c5461..1cd2d6416bd 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -342,7 +342,7 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd) return __va(ptr); } -#define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd))) +#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd))) /* * Conversion functions: convert a page and protection to a page entry, diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index e4345106ee5..bac578fe0d3 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -43,6 +43,25 @@ #define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM) +/* + * Chips have some kind of clocks : group them by functionality + */ +#define cpu_has_utmi() ( cpu_is_at91cap9() \ + || cpu_is_at91sam9rl()) + +#define cpu_has_800M_plla() (cpu_is_at91sam9g20()) + +#define cpu_has_pllb() (!cpu_is_at91sam9rl()) + +#define cpu_has_upll() (0) + +/* USB host HS & FS */ +#define cpu_has_uhp() (!cpu_is_at91sam9rl()) + +/* USB device FS only */ +#define cpu_has_udpfs() (!cpu_is_at91sam9rl()) + + static LIST_HEAD(clocks); static DEFINE_SPINLOCK(clk_lock); @@ -140,7 +159,7 @@ static struct clk utmi_clk = { }; static struct clk uhpck = { .name = "uhpck", - .parent = &pllb, + /*.parent = ... we choose parent at runtime */ .mode = pmc_sys_mode, }; @@ -173,7 +192,11 @@ static struct clk __init *at91_css_to_clk(unsigned long css) case AT91_PMC_CSS_PLLA: return &plla; case AT91_PMC_CSS_PLLB: - return &pllb; + if (cpu_has_upll()) + /* CSS_PLLB == CSS_UPLL */ + return &utmi_clk; + else if (cpu_has_pllb()) + return &pllb; } return NULL; @@ -322,7 +345,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate) u32 pckr; pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); - pckr &= AT91_PMC_CSS_PLLB; /* clock selection */ + pckr &= AT91_PMC_CSS; /* clock selection */ pckr |= prescale << 2; at91_sys_write(AT91_PMC_PCKR(clk->id), pckr); clk->rate_hz = actual; @@ -361,7 +384,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent) } EXPORT_SYMBOL(clk_set_parent); -/* establish PCK0..PCK3 parentage and rate */ +/* establish PCK0..PCKN parentage and rate */ static void __init init_programmable_clock(struct clk *clk) { struct clk *parent; @@ -389,11 +412,13 @@ static int at91_clk_show(struct seq_file *s, void *unused) seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR)); seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); - if (!cpu_is_at91sam9rl()) + if (cpu_has_pllb()) seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); - if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) + if (cpu_has_utmi()) seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR)); seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); + if (cpu_has_upll()) + seq_printf(s, "USB = %8x\n", at91_sys_read(AT91_PMC_USB)); seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); seq_printf(s, "\n"); @@ -554,16 +579,60 @@ static struct clk *const standard_pmc_clocks[] __initdata = { &clk32k, &main_clk, &plla, - &pllb, - - /* PLLB children (USB) */ - &udpck, - &uhpck, /* MCK */ &mck }; +/* PLLB generated USB full speed clock init */ +static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock) +{ + /* + * USB clock init: choose 48 MHz PLLB value, + * disable 48MHz clock during usb peripheral suspend. + * + * REVISIT: assumes MCK doesn't derive from PLLB! + */ + uhpck.parent = &pllb; + + at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; + pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); + if (cpu_is_at91rm9200()) { + uhpck.pmc_mask = AT91RM9200_PMC_UHP; + udpck.pmc_mask = AT91RM9200_PMC_UDP; + at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); + } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { + uhpck.pmc_mask = AT91SAM926x_PMC_UHP; + udpck.pmc_mask = AT91SAM926x_PMC_UDP; + } else if (cpu_is_at91cap9()) { + uhpck.pmc_mask = AT91CAP9_PMC_UHP; + } + at91_sys_write(AT91_CKGR_PLLBR, 0); + + udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); +} + +/* UPLL generated USB full speed clock init */ +static void __init at91_upll_usbfs_clock_init(unsigned long main_clock) +{ + /* + * USB clock init: choose 480 MHz from UPLL, + */ + unsigned int usbr = AT91_PMC_USBS_UPLL; + + /* Setup divider by 10 to reach 48 MHz */ + usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV; + + at91_sys_write(AT91_PMC_USB, usbr); + + /* Now set uhpck values */ + uhpck.parent = &utmi_clk; + uhpck.pmc_mask = AT91SAM926x_PMC_UHP; + uhpck.rate_hz = utmi_clk.parent->rate_hz; + uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8); +} + int __init at91_clock_init(unsigned long main_clock) { unsigned tmp, freq, mckr; @@ -585,43 +654,37 @@ int __init at91_clock_init(unsigned long main_clock) /* report if PLLA is more than mildly overclocked */ plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); - if ((!cpu_is_at91sam9g20() && plla.rate_hz > 209000000) - || (cpu_is_at91sam9g20() && plla.rate_hz > 800000000)) + if ((!cpu_has_800M_plla() && plla.rate_hz > 209000000) + || (cpu_has_800M_plla() && plla.rate_hz > 800000000)) pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); - /* - * USB clock init: choose 48 MHz PLLB value, - * disable 48MHz clock during usb peripheral suspend. - * - * REVISIT: assumes MCK doesn't derive from PLLB! - */ - at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; - pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); - if (cpu_is_at91rm9200()) { - uhpck.pmc_mask = AT91RM9200_PMC_UHP; - udpck.pmc_mask = AT91RM9200_PMC_UDP; - at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); - } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { - uhpck.pmc_mask = AT91SAM926x_PMC_UHP; - udpck.pmc_mask = AT91SAM926x_PMC_UDP; - } else if (cpu_is_at91cap9()) { - uhpck.pmc_mask = AT91CAP9_PMC_UHP; + + if (cpu_has_upll() && !cpu_has_pllb()) { + /* setup UTMI clock as the fourth primary clock + * (instead of pllb) */ + utmi_clk.type |= CLK_TYPE_PRIMARY; + utmi_clk.id = 3; } - at91_sys_write(AT91_CKGR_PLLBR, 0); - udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); - uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); /* * USB HS clock init */ - if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) { + if (cpu_has_utmi()) /* * multiplier is hard-wired to 40 * (obtain the USB High Speed 480 MHz when input is 12 MHz) */ utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; - } + + /* + * USB FS clock init + */ + if (cpu_has_pllb()) + at91_pllb_usbfs_clock_init(main_clock); + if (cpu_has_upll()) + /* assumes that we choose UPLL for USB and not PLLA */ + at91_upll_usbfs_clock_init(main_clock); /* * MCK and CPU derive from one of those primary clocks. @@ -631,21 +694,31 @@ int __init at91_clock_init(unsigned long main_clock) mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); freq = mck.parent->rate_hz; freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ - if (cpu_is_at91rm9200()) + if (cpu_is_at91rm9200()) { mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ - else if (cpu_is_at91sam9g20()) { + } else if (cpu_is_at91sam9g20()) { mck.rate_hz = (mckr & AT91_PMC_MDIV) ? freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ if (mckr & AT91_PMC_PDIV) freq /= 2; /* processor clock division */ - } else + } else { mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + } /* Register the PMC's standard clocks */ for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) list_add_tail(&standard_pmc_clocks[i]->node, &clocks); - if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) + if (cpu_has_pllb()) + list_add_tail(&pllb.node, &clocks); + + if (cpu_has_uhp()) + list_add_tail(&uhpck.node, &clocks); + + if (cpu_has_udpfs()) + list_add_tail(&udpck.node, &clocks); + + if (cpu_has_utmi()) list_add_tail(&utmi_clk.node, &clocks); /* MCK and CPU clock are "always on" */ diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 9561e33b8a9..64589eaaaee 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -23,7 +23,7 @@ #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ -#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */ +#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */ #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ #define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ @@ -39,11 +39,11 @@ #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ -#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ +#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */ #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ -#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ +#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ @@ -72,6 +72,7 @@ #define AT91_PMC_CSS_MAIN (1 << 0) #define AT91_PMC_CSS_PLLA (2 << 0) #define AT91_PMC_CSS_PLLB (3 << 0) +#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ #define AT91_PMC_PRES_1 (0 << 2) #define AT91_PMC_PRES_2 (1 << 2) @@ -88,12 +89,25 @@ #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ #define AT91SAM9_PMC_MDIV_2 (1 << 8) #define AT91SAM9_PMC_MDIV_4 (2 << 8) -#define AT91SAM9_PMC_MDIV_6 (3 << 8) +#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ +#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ #define AT91_PMC_PDIV_1 (0 << 12) #define AT91_PMC_PDIV_2 (1 << 12) +#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ +#define AT91_PMC_PLLADIV2_OFF (0 << 12) +#define AT91_PMC_PLLADIV2_ON (1 << 12) -#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ +#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */ +#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ +#define AT91_PMC_USBS_PLLA (0 << 0) +#define AT91_PMC_USBS_UPLL (1 << 0) +#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ + +#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ +#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ +#define AT91_PMC_CSSMCK_CSS (0 << 8) +#define AT91_PMC_CSSMCK_MCK (1 << 8) #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ @@ -102,7 +116,7 @@ #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ -#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ +#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */ #define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index a9c78bc72b8..76408670554 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -1,11 +1,26 @@ if ARCH_DAVINCI +config AINTC + bool + +config CP_INTC + bool + menu "TI DaVinci Implementations" comment "DaVinci Core Type" config ARCH_DAVINCI_DM644x bool "DaVinci 644x based system" + select AINTC + +config ARCH_DAVINCI_DM355 + bool "DaVinci 355 based system" + select AINTC + +config ARCH_DAVINCI_DM646x + bool "DaVinci 646x based system" + select AINTC comment "DaVinci Board Type" @@ -17,6 +32,38 @@ config MACH_DAVINCI_EVM Configure this option to specify the whether the board used for development is a DM644x EVM +config MACH_SFFSDR + bool "Lyrtech SFFSDR" + default n + depends on ARCH_DAVINCI_DM644x + help + Say Y here to select the Lyrtech Small Form Factor + Software Defined Radio (SFFSDR) board. + +config MACH_DAVINCI_DM355_EVM + bool "TI DM355 EVM" + default n + depends on ARCH_DAVINCI_DM355 + help + Configure this option to specify the whether the board used + for development is a DM355 EVM + +config MACH_DM355_LEOPARD + bool "DM355 Leopard board" + default n + depends on ARCH_DAVINCI_DM355 + help + Configure this option to specify the whether the board used + for development is a DM355 Leopard board. + +config MACH_DAVINCI_DM6467_EVM + bool "TI DM6467 EVM" + default n + depends on ARCH_DAVINCI_DM646x + help + Configure this option to specify the whether the board used + for development is a DM6467 EVM + config DAVINCI_MUX bool "DAVINCI multiplexing support" diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 1674661942f..059ab78084b 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -4,13 +4,22 @@ # # Common objects -obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \ - gpio.o devices.o dma.o usb.o +obj-y := time.o clock.o serial.o io.o psc.o \ + gpio.o devices.o dma.o usb.o common.o sram.o obj-$(CONFIG_DAVINCI_MUX) += mux.o # Chip specific obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o +obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o +obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o + +obj-$(CONFIG_AINTC) += irq.o +obj-$(CONFIG_CP_INTC) += cp_intc.o # Board specific obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o +obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o +obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o +obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o +obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c new file mode 100644 index 00000000000..5ac2f565d86 --- /dev/null +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -0,0 +1,298 @@ +/* + * TI DaVinci EVM board support + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/nand.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/clk.h> +#include <linux/spi/spi.h> +#include <linux/spi/eeprom.h> + +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/flash.h> + +#include <mach/hardware.h> +#include <mach/dm355.h> +#include <mach/psc.h> +#include <mach/common.h> +#include <mach/i2c.h> +#include <mach/serial.h> +#include <mach/nand.h> +#include <mach/mmc.h> +#include <mach/common.h> + +#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000 +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 + +/* NOTE: this is geared for the standard config, with a socketed + * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you + * swap chips, maybe with a different block size, partitioning may + * need to be changed. + */ +#define NAND_BLOCK_SIZE SZ_128K + +static struct mtd_partition davinci_nand_partitions[] = { + { + /* UBL (a few copies) plus U-Boot */ + .name = "bootloader", + .offset = 0, + .size = 15 * NAND_BLOCK_SIZE, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + /* U-Boot environment */ + .name = "params", + .offset = MTDPART_OFS_APPEND, + .size = 1 * NAND_BLOCK_SIZE, + .mask_flags = 0, + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, { + .name = "filesystem1", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512M, + .mask_flags = 0, + }, { + .name = "filesystem2", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* two blocks with bad block table (and mirror) at the end */ +}; + +static struct davinci_nand_pdata davinci_nand_data = { + .mask_chipsel = BIT(14), + .parts = davinci_nand_partitions, + .nr_parts = ARRAY_SIZE(davinci_nand_partitions), + .ecc_mode = NAND_ECC_HW_SYNDROME, + .options = NAND_USE_FLASH_BBT, +}; + +static struct resource davinci_nand_resources[] = { + { + .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, + .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, + .flags = IORESOURCE_MEM, + }, { + .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, + .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device davinci_nand_device = { + .name = "davinci_nand", + .id = 0, + + .num_resources = ARRAY_SIZE(davinci_nand_resources), + .resource = davinci_nand_resources, + + .dev = { + .platform_data = &davinci_nand_data, + }, +}; + +static struct davinci_i2c_platform_data i2c_pdata = { + .bus_freq = 400 /* kHz */, + .bus_delay = 0 /* usec */, +}; + +static int dm355evm_mmc_gpios = -EINVAL; + +static void dm355evm_mmcsd_gpios(unsigned gpio) +{ + gpio_request(gpio + 0, "mmc0_ro"); + gpio_request(gpio + 1, "mmc0_cd"); + gpio_request(gpio + 2, "mmc1_ro"); + gpio_request(gpio + 3, "mmc1_cd"); + + /* we "know" these are input-only so we don't + * need to call gpio_direction_input() + */ + + dm355evm_mmc_gpios = gpio; +} + +static struct i2c_board_info dm355evm_i2c_info[] = { + { I2C_BOARD_INFO("dm355evm_msp", 0x25), + .platform_data = dm355evm_mmcsd_gpios, + /* plus irq */ }, + /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */ + /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */ +}; + +static void __init evm_init_i2c(void) +{ + davinci_init_i2c(&i2c_pdata); + + gpio_request(5, "dm355evm_msp"); + gpio_direction_input(5); + dm355evm_i2c_info[0].irq = gpio_to_irq(5); + + i2c_register_board_info(1, dm355evm_i2c_info, + ARRAY_SIZE(dm355evm_i2c_info)); +} + +static struct resource dm355evm_dm9000_rsrc[] = { + { + /* addr */ + .start = 0x04014000, + .end = 0x04014001, + .flags = IORESOURCE_MEM, + }, { + /* data */ + .start = 0x04014002, + .end = 0x04014003, + .flags = IORESOURCE_MEM, + }, { + .flags = IORESOURCE_IRQ + | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */, + }, +}; + +static struct platform_device dm355evm_dm9000 = { + .name = "dm9000", + .id = -1, + .resource = dm355evm_dm9000_rsrc, + .num_resources = ARRAY_SIZE(dm355evm_dm9000_rsrc), +}; + +static struct platform_device *davinci_evm_devices[] __initdata = { + &dm355evm_dm9000, + &davinci_nand_device, +}; + +static struct davinci_uart_config uart_config __initdata = { + .enabled_uarts = (1 << 0), +}; + +static void __init dm355_evm_map_io(void) +{ + dm355_init(); +} + +static int dm355evm_mmc_get_cd(int module) +{ + if (!gpio_is_valid(dm355evm_mmc_gpios)) + return -ENXIO; + /* low == card present */ + return !gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 1); +} + +static int dm355evm_mmc_get_ro(int module) +{ + if (!gpio_is_valid(dm355evm_mmc_gpios)) + return -ENXIO; + /* high == card's write protect switch active */ + return gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 0); +} + +static struct davinci_mmc_config dm355evm_mmc_config = { + .get_cd = dm355evm_mmc_get_cd, + .get_ro = dm355evm_mmc_get_ro, + .wires = 4, + .max_freq = 50000000, + .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, + .version = MMC_CTLR_VERSION_1, +}; + +/* Don't connect anything to J10 unless you're only using USB host + * mode *and* have to do so with some kind of gender-bender. If + * you have proper Mini-B or Mini-A cables (or Mini-A adapters) + * the ID pin won't need any help. + */ +#ifdef CONFIG_USB_MUSB_PERIPHERAL +#define USB_ID_VALUE 0 /* ID pulled high; *should* float */ +#else +#define USB_ID_VALUE 1 /* ID pulled low */ +#endif + +static struct spi_eeprom at25640a = { + .byte_len = SZ_64K / 8, + .name = "at25640a", + .page_size = 32, + .flags = EE_ADDR2, +}; + +static struct spi_board_info dm355_evm_spi_info[] __initconst = { + { + .modalias = "at25", + .platform_data = &at25640a, + .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ + .bus_num = 0, + .chip_select = 0, + .mode = SPI_MODE_0, + }, +}; + +static __init void dm355_evm_init(void) +{ + struct clk *aemif; + + gpio_request(1, "dm9000"); + gpio_direction_input(1); + dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1); + + aemif = clk_get(&dm355evm_dm9000.dev, "aemif"); + if (IS_ERR(aemif)) + WARN("%s: unable to get AEMIF clock\n", __func__); + else + clk_enable(aemif); + + platform_add_devices(davinci_evm_devices, + ARRAY_SIZE(davinci_evm_devices)); + evm_init_i2c(); + davinci_serial_init(&uart_config); + + /* NOTE: NAND flash timings set by the UBL are slower than + * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 + * but could be 0x0400008c for about 25% faster page reads. + */ + + gpio_request(2, "usb_id_toggle"); + gpio_direction_output(2, USB_ID_VALUE); + /* irlml6401 switches over 1A in under 8 msec */ + setup_usb(500, 8); + + davinci_setup_mmc(0, &dm355evm_mmc_config); + davinci_setup_mmc(1, &dm355evm_mmc_config); + + dm355_init_spi0(BIT(0), dm355_evm_spi_info, + ARRAY_SIZE(dm355_evm_spi_info)); +} + +static __init void dm355_evm_irq_init(void) +{ + davinci_irq_init(); +} + +MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM") + .phys_io = IO_PHYS, + .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, + .boot_params = (0x80000100), + .map_io = dm355_evm_map_io, + .init_irq = dm355_evm_irq_init, + .timer = &davinci_timer, + .init_machine = dm355_evm_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c new file mode 100644 index 00000000000..28c9008df4f --- /dev/null +++ b/arch/arm/mach-davinci/board-dm355-leopard.c @@ -0,0 +1,296 @@ +/* + * DM355 leopard board support + * + * Based on board-dm355-evm.c + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/nand.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/clk.h> +#include <linux/spi/spi.h> +#include <linux/spi/eeprom.h> + +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/flash.h> + +#include <mach/hardware.h> +#include <mach/dm355.h> +#include <mach/psc.h> +#include <mach/common.h> +#include <mach/i2c.h> +#include <mach/serial.h> +#include <mach/nand.h> +#include <mach/mmc.h> +#include <mach/common.h> + +#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000 +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 + +/* NOTE: this is geared for the standard config, with a socketed + * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you + * swap chips, maybe with a different block size, partitioning may + * need to be changed. + */ +#define NAND_BLOCK_SIZE SZ_128K + +static struct mtd_partition davinci_nand_partitions[] = { + { + /* UBL (a few copies) plus U-Boot */ + .name = "bootloader", + .offset = 0, + .size = 15 * NAND_BLOCK_SIZE, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + /* U-Boot environment */ + .name = "params", + .offset = MTDPART_OFS_APPEND, + .size = 1 * NAND_BLOCK_SIZE, + .mask_flags = 0, + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, { + .name = "filesystem1", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512M, + .mask_flags = 0, + }, { + .name = "filesystem2", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* two blocks with bad block table (and mirror) at the end */ +}; + +static struct davinci_nand_pdata davinci_nand_data = { + .mask_chipsel = BIT(14), + .parts = davinci_nand_partitions, + .nr_parts = ARRAY_SIZE(davinci_nand_partitions), + .ecc_mode = NAND_ECC_HW_SYNDROME, + .options = NAND_USE_FLASH_BBT, +}; + +static struct resource davinci_nand_resources[] = { + { + .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, + .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, + .flags = IORESOURCE_MEM, + }, { + .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, + .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device davinci_nand_device = { + .name = "davinci_nand", + .id = 0, + + .num_resources = ARRAY_SIZE(davinci_nand_resources), + .resource = davinci_nand_resources, + + .dev = { + .platform_data = &davinci_nand_data, + }, +}; + +static struct davinci_i2c_platform_data i2c_pdata = { + .bus_freq = 400 /* kHz */, + .bus_delay = 0 /* usec */, +}; + +static int leopard_mmc_gpio = -EINVAL; + +static void dm355leopard_mmcsd_gpios(unsigned gpio) +{ + gpio_request(gpio + 0, "mmc0_ro"); + gpio_request(gpio + 1, "mmc0_cd"); + gpio_request(gpio + 2, "mmc1_ro"); + gpio_request(gpio + 3, "mmc1_cd"); + + /* we "know" these are input-only so we don't + * need to call gpio_direction_input() + */ + + leopard_mmc_gpio = gpio; +} + +static struct i2c_board_info dm355leopard_i2c_info[] = { + { I2C_BOARD_INFO("dm355leopard_msp", 0x25), + .platform_data = dm355leopard_mmcsd_gpios, + /* plus irq */ }, + /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */ + /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */ +}; + +static void __init leopard_init_i2c(void) +{ + davinci_init_i2c(&i2c_pdata); + + gpio_request(5, "dm355leopard_msp"); + gpio_direction_input(5); + dm355leopard_i2c_info[0].irq = gpio_to_irq(5); + + i2c_register_board_info(1, dm355leopard_i2c_info, + ARRAY_SIZE(dm355leopard_i2c_info)); +} + +static struct resource dm355leopard_dm9000_rsrc[] = { + { + /* addr */ + .start = 0x04000000, + .end = 0x04000001, + .flags = IORESOURCE_MEM, + }, { + /* data */ + .start = 0x04000016, + .end = 0x04000017, + .flags = IORESOURCE_MEM, + }, { + .flags = IORESOURCE_IRQ + | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */, + }, +}; + +static struct platform_device dm355leopard_dm9000 = { + .name = "dm9000", + .id = -1, + .resource = dm355leopard_dm9000_rsrc, + .num_resources = ARRAY_SIZE(dm355leopard_dm9000_rsrc), +}; + +static struct platform_device *davinci_leopard_devices[] __initdata = { + &dm355leopard_dm9000, + &davinci_nand_device, +}; + +static struct davinci_uart_config uart_config __initdata = { + .enabled_uarts = (1 << 0), +}; + +static void __init dm355_leopard_map_io(void) +{ + dm355_init(); +} + +static int dm355leopard_mmc_get_cd(int module) +{ + if (!gpio_is_valid(leopard_mmc_gpio)) + return -ENXIO; + /* low == card present */ + return !gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 1); +} + +static int dm355leopard_mmc_get_ro(int module) +{ + if (!gpio_is_valid(leopard_mmc_gpio)) + return -ENXIO; + /* high == card's write protect switch active */ + return gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 0); +} + +static struct davinci_mmc_config dm355leopard_mmc_config = { + .get_cd = dm355leopard_mmc_get_cd, + .get_ro = dm355leopard_mmc_get_ro, + .wires = 4, + .max_freq = 50000000, + .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, +}; + +/* Don't connect anything to J10 unless you're only using USB host + * mode *and* have to do so with some kind of gender-bender. If + * you have proper Mini-B or Mini-A cables (or Mini-A adapters) + * the ID pin won't need any help. + */ +#ifdef CONFIG_USB_MUSB_PERIPHERAL +#define USB_ID_VALUE 0 /* ID pulled high; *should* float */ +#else +#define USB_ID_VALUE 1 /* ID pulled low */ +#endif + +static struct spi_eeprom at25640a = { + .byte_len = SZ_64K / 8, + .name = "at25640a", + .page_size = 32, + .flags = EE_ADDR2, +}; + +static struct spi_board_info dm355_leopard_spi_info[] __initconst = { + { + .modalias = "at25", + .platform_data = &at25640a, + .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ + .bus_num = 0, + .chip_select = 0, + .mode = SPI_MODE_0, + }, +}; + +static __init void dm355_leopard_init(void) +{ + struct clk *aemif; + + gpio_request(9, "dm9000"); + gpio_direction_input(9); + dm355leopard_dm9000_rsrc[2].start = gpio_to_irq(9); + + aemif = clk_get(&dm355leopard_dm9000.dev, "aemif"); + if (IS_ERR(aemif)) + WARN("%s: unable to get AEMIF clock\n", __func__); + else + clk_enable(aemif); + + platform_add_devices(davinci_leopard_devices, + ARRAY_SIZE(davinci_leopard_devices)); + leopard_init_i2c(); + davinci_serial_init(&uart_config); + + /* NOTE: NAND flash timings set by the UBL are slower than + * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 + * but could be 0x0400008c for about 25% faster page reads. + */ + + gpio_request(2, "usb_id_toggle"); + gpio_direction_output(2, USB_ID_VALUE); + /* irlml6401 switches over 1A in under 8 msec */ + setup_usb(500, 8); + + davinci_setup_mmc(0, &dm355leopard_mmc_config); + davinci_setup_mmc(1, &dm355leopard_mmc_config); + + dm355_init_spi0(BIT(0), dm355_leopard_spi_info, + ARRAY_SIZE(dm355_leopard_spi_info)); +} + +static __init void dm355_leopard_irq_init(void) +{ + davinci_irq_init(); +} + +MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard") + .phys_io = IO_PHYS, + .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, + .boot_params = (0x80000100), + .map_io = dm355_leopard_map_io, + .init_irq = dm355_leopard_irq_init, + .timer = &davinci_timer, + .init_machine = dm355_leopard_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index b2e7f9c63bc..d9d40450bdc 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -16,12 +16,11 @@ #include <linux/gpio.h> #include <linux/leds.h> #include <linux/memory.h> -#include <linux/etherdevice.h> #include <linux/i2c.h> #include <linux/i2c/pcf857x.h> #include <linux/i2c/at24.h> - +#include <linux/etherdevice.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> @@ -44,6 +43,9 @@ #include <mach/mux.h> #include <mach/psc.h> #include <mach/nand.h> +#include <mach/mmc.h> +#include <mach/emac.h> +#include <mach/common.h> #define DM644X_EVM_PHY_MASK (0x2) #define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ @@ -436,45 +438,15 @@ static struct pcf857x_platform_data pcf_data_u35 = { * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL) * - ... newer boards may have more */ -static struct memory_accessor *at24_mem_acc; - -static void at24_setup(struct memory_accessor *mem_acc, void *context) -{ - DECLARE_MAC_BUF(mac_str); - char mac_addr[6]; - - at24_mem_acc = mem_acc; - - /* Read MAC addr from EEPROM */ - if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x7f00, 6) == 6) { - printk(KERN_INFO "Read MAC addr from EEPROM: %s\n", - print_mac(mac_str, mac_addr)); - } -} static struct at24_platform_data eeprom_info = { .byte_len = (256*1024) / 8, .page_size = 64, .flags = AT24_FLAG_ADDR16, - .setup = at24_setup, + .setup = davinci_get_mac_addr, + .context = (void *)0x7f00, }; -int dm6446evm_eeprom_read(void *buf, off_t off, size_t count) -{ - if (at24_mem_acc) - return at24_mem_acc->read(at24_mem_acc, buf, off, count); - return -ENODEV; -} -EXPORT_SYMBOL(dm6446evm_eeprom_read); - -int dm6446evm_eeprom_write(void *buf, off_t off, size_t count) -{ - if (at24_mem_acc) - return at24_mem_acc->write(at24_mem_acc, buf, off, count); - return -ENODEV; -} -EXPORT_SYMBOL(dm6446evm_eeprom_write); - /* * MSP430 supports RTC, card detection, input from IR remote, and * a bit more. It triggers interrupts on GPIO(7) from pressing @@ -545,6 +517,27 @@ static int dm6444evm_msp430_get_pins(void) return (buf[3] << 8) | buf[2]; } +static int dm6444evm_mmc_get_cd(int module) +{ + int status = dm6444evm_msp430_get_pins(); + + return (status < 0) ? status : !(status & BIT(1)); +} + +static int dm6444evm_mmc_get_ro(int module) +{ + int status = dm6444evm_msp430_get_pins(); + + return (status < 0) ? status : status & BIT(6 + 8); +} + +static struct davinci_mmc_config dm6446evm_mmc_config = { + .get_cd = dm6444evm_mmc_get_cd, + .get_ro = dm6444evm_mmc_get_ro, + .wires = 4, + .version = MMC_CTLR_VERSION_1 +}; + static struct i2c_board_info __initdata i2c_info[] = { { I2C_BOARD_INFO("dm6446evm_msp", 0x23), @@ -598,7 +591,6 @@ static struct davinci_uart_config uart_config __initdata = { static void __init davinci_evm_map_io(void) { - davinci_map_common_io(); dm644x_init(); } @@ -639,6 +631,7 @@ static int davinci_phy_fixup(struct phy_device *phydev) static __init void davinci_evm_init(void) { struct clk *aemif_clk; + struct davinci_soc_info *soc_info = &davinci_soc_info; aemif_clk = clk_get(NULL, "aemif"); clk_enable(aemif_clk); @@ -671,8 +664,13 @@ static __init void davinci_evm_init(void) ARRAY_SIZE(davinci_evm_devices)); evm_init_i2c(); + davinci_setup_mmc(0, &dm6446evm_mmc_config); + davinci_serial_init(&uart_config); + soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK; + soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY; + /* Register the fixup for PHY on DaVinci */ phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK, davinci_phy_fixup); diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c new file mode 100644 index 00000000000..e17de635262 --- /dev/null +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -0,0 +1,262 @@ +/* + * TI DaVinci DM646X EVM board + * + * Derived from: arch/arm/mach-davinci/board-evm.c + * Copyright (C) 2006 Texas Instruments. + * + * (C) 2007-2008, MontaVista Software, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + * + */ + +/************************************************************************** + * Included Files + **************************************************************************/ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/fs.h> +#include <linux/major.h> +#include <linux/root_dev.h> +#include <linux/dma-mapping.h> +#include <linux/serial.h> +#include <linux/serial_8250.h> +#include <linux/leds.h> +#include <linux/gpio.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/i2c.h> +#include <linux/i2c/at24.h> +#include <linux/i2c/pcf857x.h> +#include <linux/etherdevice.h> + +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/flash.h> + +#include <mach/dm646x.h> +#include <mach/common.h> +#include <mach/psc.h> +#include <mach/serial.h> +#include <mach/i2c.h> +#include <mach/mmc.h> +#include <mach/emac.h> +#include <mach/common.h> + +#define DM646X_EVM_PHY_MASK (0x2) +#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ + +static struct davinci_uart_config uart_config __initdata = { + .enabled_uarts = (1 << 0), +}; + +/* LEDS */ + +static struct gpio_led evm_leds[] = { + { .name = "DS1", .active_low = 1, }, + { .name = "DS2", .active_low = 1, }, + { .name = "DS3", .active_low = 1, }, + { .name = "DS4", .active_low = 1, }, +}; + +static __initconst struct gpio_led_platform_data evm_led_data = { + .num_leds = ARRAY_SIZE(evm_leds), + .leds = evm_leds, +}; + +static struct platform_device *evm_led_dev; + +static int evm_led_setup(struct i2c_client *client, int gpio, + unsigned int ngpio, void *c) +{ + struct gpio_led *leds = evm_leds; + int status; + + while (ngpio--) { + leds->gpio = gpio++; + leds++; + }; + + evm_led_dev = platform_device_alloc("leds-gpio", 0); + platform_device_add_data(evm_led_dev, &evm_led_data, + sizeof(evm_led_data)); + + evm_led_dev->dev.parent = &client->dev; + status = platform_device_add(evm_led_dev); + if (status < 0) { + platform_device_put(evm_led_dev); + evm_led_dev = NULL; + } + return status; +} + +static int evm_led_teardown(struct i2c_client *client, int gpio, + unsigned ngpio, void *c) +{ + if (evm_led_dev) { + platform_device_unregister(evm_led_dev); + evm_led_dev = NULL; + } + return 0; +} + +static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL }; + +static int evm_sw_setup(struct i2c_client *client, int gpio, + unsigned ngpio, void *c) +{ + int status; + int i; + char label[10]; + + for (i = 0; i < 4; ++i) { + snprintf(label, 10, "user_sw%d", i); + status = gpio_request(gpio, label); + if (status) + goto out_free; + evm_sw_gpio[i] = gpio++; + + status = gpio_direction_input(evm_sw_gpio[i]); + if (status) { + gpio_free(evm_sw_gpio[i]); + evm_sw_gpio[i] = -EINVAL; + goto out_free; + } + + status = gpio_export(evm_sw_gpio[i], 0); + if (status) { + gpio_free(evm_sw_gpio[i]); + evm_sw_gpio[i] = -EINVAL; + goto out_free; + } + } + return status; +out_free: + for (i = 0; i < 4; ++i) { + if (evm_sw_gpio[i] != -EINVAL) { + gpio_free(evm_sw_gpio[i]); + evm_sw_gpio[i] = -EINVAL; + } + } + return status; +} + +static int evm_sw_teardown(struct i2c_client *client, int gpio, + unsigned ngpio, void *c) +{ + int i; + + for (i = 0; i < 4; ++i) { + if (evm_sw_gpio[i] != -EINVAL) { + gpio_unexport(evm_sw_gpio[i]); + gpio_free(evm_sw_gpio[i]); + evm_sw_gpio[i] = -EINVAL; + } + } + return 0; +} + +static int evm_pcf_setup(struct i2c_client *client, int gpio, + unsigned int ngpio, void *c) +{ + int status; + + if (ngpio < 8) + return -EINVAL; + + status = evm_sw_setup(client, gpio, 4, c); + if (status) + return status; + + return evm_led_setup(client, gpio+4, 4, c); +} + +static int evm_pcf_teardown(struct i2c_client *client, int gpio, + unsigned int ngpio, void *c) +{ + BUG_ON(ngpio < 8); + + evm_sw_teardown(client, gpio, 4, c); + evm_led_teardown(client, gpio+4, 4, c); + + return 0; +} + +static struct pcf857x_platform_data pcf_data = { + .gpio_base = DAVINCI_N_GPIO+1, + .setup = evm_pcf_setup, + .teardown = evm_pcf_teardown, +}; + +/* Most of this EEPROM is unused, but U-Boot uses some data: + * - 0x7f00, 6 bytes Ethernet Address + * - ... newer boards may have more + */ + +static struct at24_platform_data eeprom_info = { + .byte_len = (256*1024) / 8, + .page_size = 64, + .flags = AT24_FLAG_ADDR16, + .setup = davinci_get_mac_addr, + .context = (void *)0x7f00, +}; + +static struct i2c_board_info __initdata i2c_info[] = { + { + I2C_BOARD_INFO("24c256", 0x50), + .platform_data = &eeprom_info, + }, + { + I2C_BOARD_INFO("pcf8574a", 0x38), + .platform_data = &pcf_data, + }, +}; + +static struct davinci_i2c_platform_data i2c_pdata = { + .bus_freq = 100 /* kHz */, + .bus_delay = 0 /* usec */, +}; + +static void __init evm_init_i2c(void) +{ + davinci_init_i2c(&i2c_pdata); + i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); +} + +static void __init davinci_map_io(void) +{ + dm646x_init(); +} + +static __init void evm_init(void) +{ + struct davinci_soc_info *soc_info = &davinci_soc_info; + + evm_init_i2c(); + davinci_serial_init(&uart_config); + + soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK; + soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY; +} + +static __init void davinci_dm646x_evm_irq_init(void) +{ + davinci_irq_init(); +} + +MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") + .phys_io = IO_PHYS, + .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, + .boot_params = (0x80000100), + .map_io = davinci_map_io, + .init_irq = davinci_dm646x_evm_irq_init, + .timer = &davinci_timer, + .init_machine = evm_init, +MACHINE_END + diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c new file mode 100644 index 00000000000..748a8e48541 --- /dev/null +++ b/arch/arm/mach-davinci/board-sffsdr.c @@ -0,0 +1,189 @@ +/* + * Lyrtech SFFSDR board support. + * + * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com> + * Copyright (C) 2008 Lyrtech <www.lyrtech.com> + * + * Based on DV-EVM platform, original copyright follows: + * + * Copyright (C) 2007 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/dma-mapping.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> + +#include <linux/i2c.h> +#include <linux/i2c/at24.h> +#include <linux/etherdevice.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/physmap.h> +#include <linux/io.h> + +#include <asm/setup.h> +#include <asm/mach-types.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/flash.h> + +#include <mach/dm644x.h> +#include <mach/common.h> +#include <mach/i2c.h> +#include <mach/serial.h> +#include <mach/psc.h> +#include <mach/mux.h> +#include <mach/common.h> + +#define SFFSDR_PHY_MASK (0x2) +#define SFFSDR_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ + +#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000 +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 + +struct mtd_partition davinci_sffsdr_nandflash_partition[] = { + /* U-Boot Environment: Block 0 + * UBL: Block 1 + * U-Boot: Blocks 6-7 (256 kb) + * Integrity Kernel: Blocks 8-31 (3 Mb) + * Integrity Data: Blocks 100-END + */ + { + .name = "Linux Kernel", + .offset = 32 * SZ_128K, + .size = 16 * SZ_128K, /* 2 Mb */ + .mask_flags = MTD_WRITEABLE, /* Force read-only */ + }, + { + .name = "Linux ROOT", + .offset = MTDPART_OFS_APPEND, + .size = 256 * SZ_128K, /* 32 Mb */ + .mask_flags = 0, /* R/W */ + }, +}; + +static struct flash_platform_data davinci_sffsdr_nandflash_data = { + .parts = davinci_sffsdr_nandflash_partition, + .nr_parts = ARRAY_SIZE(davinci_sffsdr_nandflash_partition), +}; + +static struct resource davinci_sffsdr_nandflash_resource[] = { + { + .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, + .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, + }, { + .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, + .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device davinci_sffsdr_nandflash_device = { + .name = "davinci_nand", /* Name of driver */ + .id = 0, + .dev = { + .platform_data = &davinci_sffsdr_nandflash_data, + }, + .num_resources = ARRAY_SIZE(davinci_sffsdr_nandflash_resource), + .resource = davinci_sffsdr_nandflash_resource, +}; + +static struct emac_platform_data sffsdr_emac_pdata = { + .phy_mask = SFFSDR_PHY_MASK, + .mdio_max_freq = SFFSDR_MDIO_FREQUENCY, +}; + +static struct at24_platform_data eeprom_info = { + .byte_len = (64*1024) / 8, + .page_size = 32, + .flags = AT24_FLAG_ADDR16, +}; + +static struct i2c_board_info __initdata i2c_info[] = { + { + I2C_BOARD_INFO("24lc64", 0x50), + .platform_data = &eeprom_info, + }, + /* Other I2C devices: + * MSP430, addr 0x23 (not used) + * PCA9543, addr 0x70 (setup done by U-Boot) + * ADS7828, addr 0x48 (ADC for voltage monitoring.) + */ +}; + +static struct davinci_i2c_platform_data i2c_pdata = { + .bus_freq = 20 /* kHz */, + .bus_delay = 100 /* usec */, +}; + +static void __init sffsdr_init_i2c(void) +{ + davinci_init_i2c(&i2c_pdata); + i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); +} + +static struct platform_device *davinci_sffsdr_devices[] __initdata = { + &davinci_sffsdr_nandflash_device, +}; + +static struct davinci_uart_config uart_config __initdata = { + .enabled_uarts = (1 << 0), +}; + +static void __init davinci_sffsdr_map_io(void) +{ + dm644x_init(); +} + +static __init void davinci_sffsdr_init(void) +{ + struct davinci_soc_info *soc_info = &davinci_soc_info; + + platform_add_devices(davinci_sffsdr_devices, + ARRAY_SIZE(davinci_sffsdr_devices)); + sffsdr_init_i2c(); + davinci_serial_init(&uart_config); + soc_info->emac_pdata->phy_mask = SFFSDR_PHY_MASK; + soc_info->emac_pdata->mdio_max_freq = SFFSDR_MDIO_FREQUENCY; + setup_usb(0, 0); /* We support only peripheral mode. */ + + /* mux VLYNQ pins */ + davinci_cfg_reg(DM644X_VLYNQEN); + davinci_cfg_reg(DM644X_VLYNQWD); +} + +static __init void davinci_sffsdr_irq_init(void) +{ + davinci_irq_init(); +} + +MACHINE_START(SFFSDR, "Lyrtech SFFSDR") + /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */ + .phys_io = IO_PHYS, + .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, + .boot_params = (DAVINCI_DDR_BASE + 0x100), + .map_io = davinci_sffsdr_map_io, + .init_irq = davinci_sffsdr_irq_init, + .timer = &davinci_timer, + .init_machine = davinci_sffsdr_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index f0baaa15a57..39bf321d70a 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -42,7 +42,8 @@ static void __clk_enable(struct clk *clk) if (clk->parent) __clk_enable(clk->parent); if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) - davinci_psc_config(psc_domain(clk), clk->lpsc, 1); + davinci_psc_config(psc_domain(clk), clk->psc_ctlr, + clk->lpsc, 1); } static void __clk_disable(struct clk *clk) @@ -50,7 +51,8 @@ static void __clk_disable(struct clk *clk) if (WARN_ON(clk->usecount == 0)) return; if (--clk->usecount == 0 && !(clk->flags & CLK_PLL)) - davinci_psc_config(psc_domain(clk), clk->lpsc, 0); + davinci_psc_config(psc_domain(clk), clk->psc_ctlr, + clk->lpsc, 0); if (clk->parent) __clk_disable(clk->parent); } @@ -164,11 +166,11 @@ static int __init clk_disable_unused(void) continue; /* ignore if in Disabled or SwRstDisable states */ - if (!davinci_psc_is_clk_active(ck->lpsc)) + if (!davinci_psc_is_clk_active(ck->psc_ctlr, ck->lpsc)) continue; pr_info("Clocks: disable unused %s\n", ck->name); - davinci_psc_config(psc_domain(ck), ck->lpsc, 0); + davinci_psc_config(psc_domain(ck), ck->psc_ctlr, ck->lpsc, 0); } spin_unlock_irq(&clockfw_lock); diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 35736ec202f..27233cb4a2f 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -67,6 +67,7 @@ struct clk { u8 usecount; u8 flags; u8 lpsc; + u8 psc_ctlr; struct clk *parent; struct pll_data *pll_data; u32 div_reg; @@ -93,4 +94,7 @@ struct davinci_clk { } int davinci_clk_init(struct davinci_clk *clocks); + +extern struct platform_device davinci_wdt_device; + #endif diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c new file mode 100644 index 00000000000..61ede19c6b5 --- /dev/null +++ b/arch/arm/mach-davinci/common.c @@ -0,0 +1,108 @@ +/* + * Code commons to all DaVinci SoCs. + * + * Author: Mark A. Greer <mgreer@mvista.com> + * + * 2009 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/module.h> +#include <linux/io.h> +#include <linux/etherdevice.h> + +#include <asm/tlb.h> +#include <asm/mach/map.h> + +#include <mach/common.h> +#include <mach/cputype.h> +#include <mach/emac.h> + +#include "clock.h" + +struct davinci_soc_info davinci_soc_info; +EXPORT_SYMBOL(davinci_soc_info); + +void __iomem *davinci_intc_base; +int davinci_intc_type; + +void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context) +{ + char *mac_addr = davinci_soc_info.emac_pdata->mac_addr; + off_t offset = (off_t)context; + + /* Read MAC addr from EEPROM */ + if (mem_acc->read(mem_acc, mac_addr, offset, ETH_ALEN) == ETH_ALEN) + pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr); +} + +static struct davinci_id * __init davinci_get_id(u32 jtag_id) +{ + int i; + struct davinci_id *dip; + u8 variant = (jtag_id & 0xf0000000) >> 28; + u16 part_no = (jtag_id & 0x0ffff000) >> 12; + + for (i = 0, dip = davinci_soc_info.ids; i < davinci_soc_info.ids_num; + i++, dip++) + /* Don't care about the manufacturer right now */ + if ((dip->part_no == part_no) && (dip->variant == variant)) + return dip; + + return NULL; +} + +void __init davinci_common_init(struct davinci_soc_info *soc_info) +{ + int ret; + struct davinci_id *dip; + + if (!soc_info) { + ret = -EINVAL; + goto err; + } + + memcpy(&davinci_soc_info, soc_info, sizeof(struct davinci_soc_info)); + + if (davinci_soc_info.io_desc && (davinci_soc_info.io_desc_num > 0)) + iotable_init(davinci_soc_info.io_desc, + davinci_soc_info.io_desc_num); + + /* + * Normally devicemaps_init() would flush caches and tlb after + * mdesc->map_io(), but we must also do it here because of the CPU + * revision check below. + */ + local_flush_tlb_all(); + flush_cache_all(); + + /* + * We want to check CPU revision early for cpu_is_xxxx() macros. + * IO space mapping must be initialized before we can do that. + */ + davinci_soc_info.jtag_id = __raw_readl(davinci_soc_info.jtag_id_base); + + dip = davinci_get_id(davinci_soc_info.jtag_id); + if (!dip) { + ret = -EINVAL; + goto err; + } + + davinci_soc_info.cpu_id = dip->cpu_id; + pr_info("DaVinci %s variant 0x%x\n", dip->name, dip->variant); + + if (davinci_soc_info.cpu_clks) { + ret = davinci_clk_init(davinci_soc_info.cpu_clks); + + if (ret != 0) + goto err; + } + + davinci_intc_base = davinci_soc_info.intc_base; + davinci_intc_type = davinci_soc_info.intc_type; + return; + +err: + pr_err("davinci_common_init: SoC Initialization failed\n"); +} diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c new file mode 100644 index 00000000000..96c8e97a7de --- /dev/null +++ b/arch/arm/mach-davinci/cp_intc.c @@ -0,0 +1,161 @@ +/* + * TI Common Platform Interrupt Controller (cp_intc) driver + * + * Author: Steve Chen <schen@mvista.com> + * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com> + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <mach/cp_intc.h> + +static void __iomem *cp_intc_base; + +static inline unsigned int cp_intc_read(unsigned offset) +{ + return __raw_readl(cp_intc_base + offset); +} + +static inline void cp_intc_write(unsigned long value, unsigned offset) +{ + __raw_writel(value, cp_intc_base + offset); +} + +static void cp_intc_ack_irq(unsigned int irq) +{ + cp_intc_write(irq, CP_INTC_SYS_STAT_IDX_CLR); +} + +/* Disable interrupt */ +static void cp_intc_mask_irq(unsigned int irq) +{ + /* XXX don't know why we need to disable nIRQ here... */ + cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR); + cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_CLR); + cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET); +} + +/* Enable interrupt */ +static void cp_intc_unmask_irq(unsigned int irq) +{ + cp_intc_write(irq, CP_INTC_SYS_ENABLE_IDX_SET); +} + +static int cp_intc_set_irq_type(unsigned int irq, unsigned int flow_type) +{ + unsigned reg = BIT_WORD(irq); + unsigned mask = BIT_MASK(irq); + unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg)); + unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg)); + + switch (flow_type) { + case IRQ_TYPE_EDGE_RISING: + polarity |= mask; + type |= mask; + break; + case IRQ_TYPE_EDGE_FALLING: + polarity &= ~mask; + type |= mask; + break; + case IRQ_TYPE_LEVEL_HIGH: + polarity |= mask; + type &= ~mask; + break; + case IRQ_TYPE_LEVEL_LOW: + polarity &= ~mask; + type &= ~mask; + break; + default: + return -EINVAL; + } + + cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg)); + cp_intc_write(type, CP_INTC_SYS_TYPE(reg)); + + return 0; +} + +static struct irq_chip cp_intc_irq_chip = { + .name = "cp_intc", + .ack = cp_intc_ack_irq, + .mask = cp_intc_mask_irq, + .unmask = cp_intc_unmask_irq, + .set_type = cp_intc_set_irq_type, +}; + +void __init cp_intc_init(void __iomem *base, unsigned short num_irq, + u8 *irq_prio) +{ + unsigned num_reg = BITS_TO_LONGS(num_irq); + int i; + + cp_intc_base = base; + + cp_intc_write(0, CP_INTC_GLOBAL_ENABLE); + + /* Disable all host interrupts */ + cp_intc_write(0, CP_INTC_HOST_ENABLE(0)); + + /* Disable system interrupts */ + for (i = 0; i < num_reg; i++) + cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i)); + + /* Set to normal mode, no nesting, no priority hold */ + cp_intc_write(0, CP_INTC_CTRL); + cp_intc_write(0, CP_INTC_HOST_CTRL); + + /* Clear system interrupt status */ + for (i = 0; i < num_reg; i++) + cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i)); + + /* Enable nIRQ (what about nFIQ?) */ + cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET); + + /* + * Priority is determined by host channel: lower channel number has + * higher priority i.e. channel 0 has highest priority and channel 31 + * had the lowest priority. + */ + num_reg = (num_irq + 3) >> 2; /* 4 channels per register */ + if (irq_prio) { + unsigned j, k; + u32 val; + + for (k = i = 0; i < num_reg; i++) { + for (val = j = 0; j < 4; j++, k++) { + val >>= 8; + if (k < num_irq) + val |= irq_prio[k] << 24; + } + + cp_intc_write(val, CP_INTC_CHAN_MAP(i)); + } + } else { + /* + * Default everything to channel 15 if priority not specified. + * Note that channel 0-1 are mapped to nFIQ and channels 2-31 + * are mapped to nIRQ. + */ + for (i = 0; i < num_reg; i++) + cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i)); + } + + /* Set up genirq dispatching for cp_intc */ + for (i = 0; i < num_irq; i++) { + set_irq_chip(i, &cp_intc_irq_chip); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + set_irq_handler(i, handle_edge_irq); + } + + /* Enable global interrupt */ + cp_intc_write(1, CP_INTC_GLOBAL_ENABLE); +} diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index a31370b93dd..de16f347566 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -23,8 +23,14 @@ #include <mach/irqs.h> #include <mach/cputype.h> #include <mach/mux.h> +#include <mach/edma.h> +#include <mach/mmc.h> +#include <mach/time.h> #define DAVINCI_I2C_BASE 0x01C21000 +#define DAVINCI_MMCSD0_BASE 0x01E10000 +#define DM355_MMCSD0_BASE 0x01E11000 +#define DM355_MMCSD1_BASE 0x01E00000 static struct resource i2c_resources[] = { { @@ -54,3 +60,208 @@ void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata) (void) platform_device_register(&davinci_i2c_device); } +#if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE) + +static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32); + +static struct resource mmcsd0_resources[] = { + { + /* different on dm355 */ + .start = DAVINCI_MMCSD0_BASE, + .end = DAVINCI_MMCSD0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + /* IRQs: MMC/SD, then SDIO */ + { + .start = IRQ_MMCINT, + .flags = IORESOURCE_IRQ, + }, { + /* different on dm355 */ + .start = IRQ_SDIOINT, + .flags = IORESOURCE_IRQ, + }, + /* DMA channels: RX, then TX */ + { + .start = DAVINCI_DMA_MMCRXEVT, + .flags = IORESOURCE_DMA, + }, { + .start = DAVINCI_DMA_MMCTXEVT, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device davinci_mmcsd0_device = { + .name = "davinci_mmc", + .id = 0, + .dev = { + .dma_mask = &mmcsd0_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(mmcsd0_resources), + .resource = mmcsd0_resources, +}; + +static u64 mmcsd1_dma_mask = DMA_BIT_MASK(32); + +static struct resource mmcsd1_resources[] = { + { + .start = DM355_MMCSD1_BASE, + .end = DM355_MMCSD1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + /* IRQs: MMC/SD, then SDIO */ + { + .start = IRQ_DM355_MMCINT1, + .flags = IORESOURCE_IRQ, + }, { + .start = IRQ_DM355_SDIOINT1, + .flags = IORESOURCE_IRQ, + }, + /* DMA channels: RX, then TX */ + { + .start = 30, /* rx */ + .flags = IORESOURCE_DMA, + }, { + .start = 31, /* tx */ + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device davinci_mmcsd1_device = { + .name = "davinci_mmc", + .id = 1, + .dev = { + .dma_mask = &mmcsd1_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(mmcsd1_resources), + .resource = mmcsd1_resources, +}; + + +void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) +{ + struct platform_device *pdev = NULL; + + if (WARN_ON(cpu_is_davinci_dm646x())) + return; + + /* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too; + * for example if MMCSD1 is used for SDIO, maybe DAT2 is unused. + * + * FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are + * not handled right here ... + */ + switch (module) { + case 1: + if (!cpu_is_davinci_dm355()) + break; + + /* REVISIT we may not need all these pins if e.g. this + * is a hard-wired SDIO device... + */ + davinci_cfg_reg(DM355_SD1_CMD); + davinci_cfg_reg(DM355_SD1_CLK); + davinci_cfg_reg(DM355_SD1_DATA0); + davinci_cfg_reg(DM355_SD1_DATA1); + davinci_cfg_reg(DM355_SD1_DATA2); + davinci_cfg_reg(DM355_SD1_DATA3); + + pdev = &davinci_mmcsd1_device; + break; + case 0: + if (cpu_is_davinci_dm355()) { + mmcsd0_resources[0].start = DM355_MMCSD0_BASE; + mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1; + mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0; + + /* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */ + davinci_cfg_reg(DM355_MMCSD0); + + /* enable RX EDMA */ + davinci_cfg_reg(DM355_EVT26_MMC0_RX); + } + + else if (cpu_is_davinci_dm644x()) { + /* REVISIT: should this be in board-init code? */ + void __iomem *base = + IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); + + /* Power-on 3.3V IO cells */ + __raw_writel(0, base + DM64XX_VDD3P3V_PWDN); + /*Set up the pull regiter for MMC */ + davinci_cfg_reg(DM644X_MSTK); + } + + pdev = &davinci_mmcsd0_device; + break; + } + + if (WARN_ON(!pdev)) + return; + + pdev->dev.platform_data = config; + platform_device_register(pdev); +} + +#else + +void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) +{ +} + +#endif + +/*-------------------------------------------------------------------------*/ + +static struct resource wdt_resources[] = { + { + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device davinci_wdt_device = { + .name = "watchdog", + .id = -1, + .num_resources = ARRAY_SIZE(wdt_resources), + .resource = wdt_resources, +}; + +static void davinci_init_wdt(void) +{ + struct davinci_soc_info *soc_info = &davinci_soc_info; + + wdt_resources[0].start = (resource_size_t)soc_info->wdt_base; + wdt_resources[0].end = (resource_size_t)soc_info->wdt_base + SZ_1K - 1; + + platform_device_register(&davinci_wdt_device); +} + +/*-------------------------------------------------------------------------*/ + +struct davinci_timer_instance davinci_timer_instance[2] = { + { + .base = IO_ADDRESS(DAVINCI_TIMER0_BASE), + .bottom_irq = IRQ_TINT0_TINT12, + .top_irq = IRQ_TINT0_TINT34, + }, + { + .base = IO_ADDRESS(DAVINCI_TIMER1_BASE), + .bottom_irq = IRQ_TINT1_TINT12, + .top_irq = IRQ_TINT1_TINT34, + }, +}; + +/*-------------------------------------------------------------------------*/ + +static int __init davinci_init_devices(void) +{ + /* please keep these calls, and their implementations above, + * in alphabetical order so they're easier to sort through. + */ + davinci_init_wdt(); + + return 0; +} +arch_initcall(davinci_init_devices); + diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c new file mode 100644 index 00000000000..baaaf328de2 --- /dev/null +++ b/arch/arm/mach-davinci/dm355.c @@ -0,0 +1,730 @@ +/* + * TI DaVinci DM355 chip specific setup + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * 2007 (c) Deep Root Systems, LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/serial_8250.h> +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <linux/gpio.h> + +#include <linux/spi/spi.h> + +#include <asm/mach/map.h> + +#include <mach/dm355.h> +#include <mach/clock.h> +#include <mach/cputype.h> +#include <mach/edma.h> +#include <mach/psc.h> +#include <mach/mux.h> +#include <mach/irqs.h> +#include <mach/time.h> +#include <mach/serial.h> +#include <mach/common.h> + +#include "clock.h" +#include "mux.h" + +#define DM355_UART2_BASE (IO_PHYS + 0x206000) + +/* + * Device specific clocks + */ +#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */ + +static struct pll_data pll1_data = { + .num = 1, + .phys_base = DAVINCI_PLL1_BASE, + .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, +}; + +static struct pll_data pll2_data = { + .num = 2, + .phys_base = DAVINCI_PLL2_BASE, + .flags = PLL_HAS_PREDIV, +}; + +static struct clk ref_clk = { + .name = "ref_clk", + /* FIXME -- crystal rate is board-specific */ + .rate = DM355_REF_FREQ, +}; + +static struct clk pll1_clk = { + .name = "pll1", + .parent = &ref_clk, + .flags = CLK_PLL, + .pll_data = &pll1_data, +}; + +static struct clk pll1_aux_clk = { + .name = "pll1_aux_clk", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll1_sysclk1 = { + .name = "pll1_sysclk1", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + +static struct clk pll1_sysclk2 = { + .name = "pll1_sysclk2", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll1_sysclk3 = { + .name = "pll1_sysclk3", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk pll1_sysclk4 = { + .name = "pll1_sysclk4", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV4, +}; + +static struct clk pll1_sysclkbp = { + .name = "pll1_sysclkbp", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, + .div_reg = BPDIV +}; + +static struct clk vpss_dac_clk = { + .name = "vpss_dac", + .parent = &pll1_sysclk3, + .lpsc = DM355_LPSC_VPSS_DAC, +}; + +static struct clk vpss_master_clk = { + .name = "vpss_master", + .parent = &pll1_sysclk4, + .lpsc = DAVINCI_LPSC_VPSSMSTR, + .flags = CLK_PSC, +}; + +static struct clk vpss_slave_clk = { + .name = "vpss_slave", + .parent = &pll1_sysclk4, + .lpsc = DAVINCI_LPSC_VPSSSLV, +}; + + +static struct clk clkout1_clk = { + .name = "clkout1", + .parent = &pll1_aux_clk, + /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */ +}; + +static struct clk clkout2_clk = { + .name = "clkout2", + .parent = &pll1_sysclkbp, +}; + +static struct clk pll2_clk = { + .name = "pll2", + .parent = &ref_clk, + .flags = CLK_PLL, + .pll_data = &pll2_data, +}; + +static struct clk pll2_sysclk1 = { + .name = "pll2_sysclk1", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + +static struct clk pll2_sysclkbp = { + .name = "pll2_sysclkbp", + .parent = &pll2_clk, + .flags = CLK_PLL | PRE_PLL, + .div_reg = BPDIV +}; + +static struct clk clkout3_clk = { + .name = "clkout3", + .parent = &pll2_sysclkbp, + /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */ +}; + +static struct clk arm_clk = { + .name = "arm_clk", + .parent = &pll1_sysclk1, + .lpsc = DAVINCI_LPSC_ARM, + .flags = ALWAYS_ENABLED, +}; + +/* + * NOT LISTED below, and not touched by Linux + * - in SyncReset state by default + * .lpsc = DAVINCI_LPSC_TPCC, + * .lpsc = DAVINCI_LPSC_TPTC0, + * .lpsc = DAVINCI_LPSC_TPTC1, + * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk, + * .lpsc = DAVINCI_LPSC_MEMSTICK, + * - in Enabled state by default + * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS, + * .lpsc = DAVINCI_LPSC_SCR2, // "bus" + * .lpsc = DAVINCI_LPSC_SCR3, // "bus" + * .lpsc = DAVINCI_LPSC_SCR4, // "bus" + * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation" + * .lpsc = DAVINCI_LPSC_CFG27, // "test" + * .lpsc = DAVINCI_LPSC_CFG3, // "test" + * .lpsc = DAVINCI_LPSC_CFG5, // "test" + */ + +static struct clk mjcp_clk = { + .name = "mjcp", + .parent = &pll1_sysclk1, + .lpsc = DAVINCI_LPSC_IMCOP, +}; + +static struct clk uart0_clk = { + .name = "uart0", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_UART0, +}; + +static struct clk uart1_clk = { + .name = "uart1", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_UART1, +}; + +static struct clk uart2_clk = { + .name = "uart2", + .parent = &pll1_sysclk2, + .lpsc = DAVINCI_LPSC_UART2, +}; + +static struct clk i2c_clk = { + .name = "i2c", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_I2C, +}; + +static struct clk asp0_clk = { + .name = "asp0", + .parent = &pll1_sysclk2, + .lpsc = DAVINCI_LPSC_McBSP, +}; + +static struct clk asp1_clk = { + .name = "asp1", + .parent = &pll1_sysclk2, + .lpsc = DM355_LPSC_McBSP1, +}; + +static struct clk mmcsd0_clk = { + .name = "mmcsd0", + .parent = &pll1_sysclk2, + .lpsc = DAVINCI_LPSC_MMC_SD, +}; + +static struct clk mmcsd1_clk = { + .name = "mmcsd1", + .parent = &pll1_sysclk2, + .lpsc = DM355_LPSC_MMC_SD1, +}; + +static struct clk spi0_clk = { + .name = "spi0", + .parent = &pll1_sysclk2, + .lpsc = DAVINCI_LPSC_SPI, +}; + +static struct clk spi1_clk = { + .name = "spi1", + .parent = &pll1_sysclk2, + .lpsc = DM355_LPSC_SPI1, +}; + +static struct clk spi2_clk = { + .name = "spi2", + .parent = &pll1_sysclk2, + .lpsc = DM355_LPSC_SPI2, +}; + +static struct clk gpio_clk = { + .name = "gpio", + .parent = &pll1_sysclk2, + .lpsc = DAVINCI_LPSC_GPIO, +}; + +static struct clk aemif_clk = { + .name = "aemif", + .parent = &pll1_sysclk2, + .lpsc = DAVINCI_LPSC_AEMIF, +}; + +static struct clk pwm0_clk = { + .name = "pwm0", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM0, +}; + +static struct clk pwm1_clk = { + .name = "pwm1", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM1, +}; + +static struct clk pwm2_clk = { + .name = "pwm2", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_PWM2, +}; + +static struct clk pwm3_clk = { + .name = "pwm3", + .parent = &pll1_aux_clk, + .lpsc = DM355_LPSC_PWM3, +}; + +static struct clk timer0_clk = { + .name = "timer0", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_TIMER0, +}; + +static struct clk timer1_clk = { + .name = "timer1", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_TIMER1, +}; + +static struct clk timer2_clk = { + .name = "timer2", + .parent = &pll1_aux_clk, + .lpsc = DAVINCI_LPSC_TIMER2, + .usecount = 1, /* REVISIT: why cant' this be disabled? */ +}; + +static struct clk timer3_clk = { + .name = "timer3", + .parent = &pll1_aux_clk, + .lpsc = DM355_LPSC_TIMER3, +}; + +static struct clk rto_clk = { + .name = "rto", + .parent = &pll1_aux_clk, + .lpsc = DM355_LPSC_RTO, +}; + +static struct clk usb_clk = { + .name = "usb", + .parent = &pll1_sysclk2, + .lpsc = DAVINCI_LPSC_USB, +}; + +static struct davinci_clk dm355_clks[] = { + CLK(NULL, "ref", &ref_clk), + CLK(NULL, "pll1", &pll1_clk), + CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), + CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), + CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), + CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), + CLK(NULL, "pll1_aux", &pll1_aux_clk), + CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp), + CLK(NULL, "vpss_dac", &vpss_dac_clk), + CLK(NULL, "vpss_master", &vpss_master_clk), + CLK(NULL, "vpss_slave", &vpss_slave_clk), + CLK(NULL, "clkout1", &clkout1_clk), + CLK(NULL, "clkout2", &clkout2_clk), + CLK(NULL, "pll2", &pll2_clk), + CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), + CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp), + CLK(NULL, "clkout3", &clkout3_clk), + CLK(NULL, "arm", &arm_clk), + CLK(NULL, "mjcp", &mjcp_clk), + CLK(NULL, "uart0", &uart0_clk), + CLK(NULL, "uart1", &uart1_clk), + CLK(NULL, "uart2", &uart2_clk), + CLK("i2c_davinci.1", NULL, &i2c_clk), + CLK("soc-audio.0", NULL, &asp0_clk), + CLK("soc-audio.1", NULL, &asp1_clk), + CLK("davinci_mmc.0", NULL, &mmcsd0_clk), + CLK("davinci_mmc.1", NULL, &mmcsd1_clk), + CLK(NULL, "spi0", &spi0_clk), + CLK(NULL, "spi1", &spi1_clk), + CLK(NULL, "spi2", &spi2_clk), + CLK(NULL, "gpio", &gpio_clk), + CLK(NULL, "aemif", &aemif_clk), + CLK(NULL, "pwm0", &pwm0_clk), + CLK(NULL, "pwm1", &pwm1_clk), + CLK(NULL, "pwm2", &pwm2_clk), + CLK(NULL, "pwm3", &pwm3_clk), + CLK(NULL, "timer0", &timer0_clk), + CLK(NULL, "timer1", &timer1_clk), + CLK("watchdog", NULL, &timer2_clk), + CLK(NULL, "timer3", &timer3_clk), + CLK(NULL, "rto", &rto_clk), + CLK(NULL, "usb", &usb_clk), + CLK(NULL, NULL, NULL), +}; + +/*----------------------------------------------------------------------*/ + +static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32); + +static struct resource dm355_spi0_resources[] = { + { + .start = 0x01c66000, + .end = 0x01c667ff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DM355_SPINT0_1, + .flags = IORESOURCE_IRQ, + }, + /* Not yet used, so not included: + * IORESOURCE_IRQ: + * - IRQ_DM355_SPINT0_0 + * IORESOURCE_DMA: + * - DAVINCI_DMA_SPI_SPIX + * - DAVINCI_DMA_SPI_SPIR + */ +}; + +static struct platform_device dm355_spi0_device = { + .name = "spi_davinci", + .id = 0, + .dev = { + .dma_mask = &dm355_spi0_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(dm355_spi0_resources), + .resource = dm355_spi0_resources, +}; + +void __init dm355_init_spi0(unsigned chipselect_mask, + struct spi_board_info *info, unsigned len) +{ + /* for now, assume we need MISO */ + davinci_cfg_reg(DM355_SPI0_SDI); + + /* not all slaves will be wired up */ + if (chipselect_mask & BIT(0)) + davinci_cfg_reg(DM355_SPI0_SDENA0); + if (chipselect_mask & BIT(1)) + davinci_cfg_reg(DM355_SPI0_SDENA1); + + spi_register_board_info(info, len); + + platform_device_register(&dm355_spi0_device); +} + +/*----------------------------------------------------------------------*/ + +#define PINMUX0 0x00 +#define PINMUX1 0x04 +#define PINMUX2 0x08 +#define PINMUX3 0x0c +#define PINMUX4 0x10 +#define INTMUX 0x18 +#define EVTMUX 0x1c + +/* + * Device specific mux setup + * + * soc description mux mode mode mux dbg + * reg offset mask mode + */ +static const struct mux_config dm355_pins[] = { +#ifdef CONFIG_DAVINCI_MUX +MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false) + +MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false) +MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false) +MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false) +MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false) +MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false) +MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false) + +MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false) +MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false) + +MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false) +MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false) +MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false) +MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false) +MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false) +MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false) + +MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false) +MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false) +MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false) + +INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false) +INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false) +INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false) + +EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false) +EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false) +EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false) +#endif +}; + +static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = { + [IRQ_DM355_CCDC_VDINT0] = 2, + [IRQ_DM355_CCDC_VDINT1] = 6, + [IRQ_DM355_CCDC_VDINT2] = 6, + [IRQ_DM355_IPIPE_HST] = 6, + [IRQ_DM355_H3AINT] = 6, + [IRQ_DM355_IPIPE_SDR] = 6, + [IRQ_DM355_IPIPEIFINT] = 6, + [IRQ_DM355_OSDINT] = 7, + [IRQ_DM355_VENCINT] = 6, + [IRQ_ASQINT] = 6, + [IRQ_IMXINT] = 6, + [IRQ_USBINT] = 4, + [IRQ_DM355_RTOINT] = 4, + [IRQ_DM355_UARTINT2] = 7, + [IRQ_DM355_TINT6] = 7, + [IRQ_CCINT0] = 5, /* dma */ + [IRQ_CCERRINT] = 5, /* dma */ + [IRQ_TCERRINT0] = 5, /* dma */ + [IRQ_TCERRINT] = 5, /* dma */ + [IRQ_DM355_SPINT2_1] = 7, + [IRQ_DM355_TINT7] = 4, + [IRQ_DM355_SDIOINT0] = 7, + [IRQ_MBXINT] = 7, + [IRQ_MBRINT] = 7, + [IRQ_MMCINT] = 7, + [IRQ_DM355_MMCINT1] = 7, + [IRQ_DM355_PWMINT3] = 7, + [IRQ_DDRINT] = 7, + [IRQ_AEMIFINT] = 7, + [IRQ_DM355_SDIOINT1] = 4, + [IRQ_TINT0_TINT12] = 2, /* clockevent */ + [IRQ_TINT0_TINT34] = 2, /* clocksource */ + [IRQ_TINT1_TINT12] = 7, /* DSP timer */ + [IRQ_TINT1_TINT34] = 7, /* system tick */ + [IRQ_PWMINT0] = 7, + [IRQ_PWMINT1] = 7, + [IRQ_PWMINT2] = 7, + [IRQ_I2C] = 3, + [IRQ_UARTINT0] = 3, + [IRQ_UARTINT1] = 3, + [IRQ_DM355_SPINT0_0] = 3, + [IRQ_DM355_SPINT0_1] = 3, + [IRQ_DM355_GPIO0] = 3, + [IRQ_DM355_GPIO1] = 7, + [IRQ_DM355_GPIO2] = 4, + [IRQ_DM355_GPIO3] = 4, + [IRQ_DM355_GPIO4] = 7, + [IRQ_DM355_GPIO5] = 7, + [IRQ_DM355_GPIO6] = 7, + [IRQ_DM355_GPIO7] = 7, + [IRQ_DM355_GPIO8] = 7, + [IRQ_DM355_GPIO9] = 7, + [IRQ_DM355_GPIOBNK0] = 7, + [IRQ_DM355_GPIOBNK1] = 7, + [IRQ_DM355_GPIOBNK2] = 7, + [IRQ_DM355_GPIOBNK3] = 7, + [IRQ_DM355_GPIOBNK4] = 7, + [IRQ_DM355_GPIOBNK5] = 7, + [IRQ_DM355_GPIOBNK6] = 7, + [IRQ_COMMTX] = 7, + [IRQ_COMMRX] = 7, + [IRQ_EMUINT] = 7, +}; + +/*----------------------------------------------------------------------*/ + +static const s8 dma_chan_dm355_no_event[] = { + 12, 13, 24, 56, 57, + 58, 59, 60, 61, 62, + 63, + -1 +}; + +static struct edma_soc_info dm355_edma_info = { + .n_channel = 64, + .n_region = 4, + .n_slot = 128, + .n_tc = 2, + .noevent = dma_chan_dm355_no_event, +}; + +static struct resource edma_resources[] = { + { + .name = "edma_cc", + .start = 0x01c00000, + .end = 0x01c00000 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc0", + .start = 0x01c10000, + .end = 0x01c10000 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc1", + .start = 0x01c10400, + .end = 0x01c10400 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_CCINT0, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_CCERRINT, + .flags = IORESOURCE_IRQ, + }, + /* not using (or muxing) TC*_ERR */ +}; + +static struct platform_device dm355_edma_device = { + .name = "edma", + .id = -1, + .dev.platform_data = &dm355_edma_info, + .num_resources = ARRAY_SIZE(edma_resources), + .resource = edma_resources, +}; + +/*----------------------------------------------------------------------*/ + +static struct map_desc dm355_io_desc[] = { + { + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(IO_PHYS), + .length = IO_SIZE, + .type = MT_DEVICE + }, + { + .virtual = SRAM_VIRT, + .pfn = __phys_to_pfn(0x00010000), + .length = SZ_32K, + /* MT_MEMORY_NONCACHED requires supersection alignment */ + .type = MT_DEVICE, + }, +}; + +/* Contents of JTAG ID register used to identify exact cpu type */ +static struct davinci_id dm355_ids[] = { + { + .variant = 0x0, + .part_no = 0xb73b, + .manufacturer = 0x00f, + .cpu_id = DAVINCI_CPU_ID_DM355, + .name = "dm355", + }, +}; + +static void __iomem *dm355_psc_bases[] = { + IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), +}; + +/* + * T0_BOT: Timer 0, bottom: clockevent source for hrtimers + * T0_TOP: Timer 0, top : clocksource for generic timekeeping + * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) + * T1_TOP: Timer 1, top : <unused> + */ +struct davinci_timer_info dm355_timer_info = { + .timers = davinci_timer_instance, + .clockevent_id = T0_BOT, + .clocksource_id = T0_TOP, +}; + +static struct plat_serial8250_port dm355_serial_platform_data[] = { + { + .mapbase = DAVINCI_UART0_BASE, + .irq = IRQ_UARTINT0, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DAVINCI_UART1_BASE, + .irq = IRQ_UARTINT1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DM355_UART2_BASE, + .irq = IRQ_DM355_UARTINT2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .flags = 0 + }, +}; + +static struct platform_device dm355_serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = dm355_serial_platform_data, + }, +}; + +static struct davinci_soc_info davinci_soc_info_dm355 = { + .io_desc = dm355_io_desc, + .io_desc_num = ARRAY_SIZE(dm355_io_desc), + .jtag_id_base = IO_ADDRESS(0x01c40028), + .ids = dm355_ids, + .ids_num = ARRAY_SIZE(dm355_ids), + .cpu_clks = dm355_clks, + .psc_bases = dm355_psc_bases, + .psc_bases_num = ARRAY_SIZE(dm355_psc_bases), + .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), + .pinmux_pins = dm355_pins, + .pinmux_pins_num = ARRAY_SIZE(dm355_pins), + .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), + .intc_type = DAVINCI_INTC_TYPE_AINTC, + .intc_irq_prios = dm355_default_priorities, + .intc_irq_num = DAVINCI_N_AINTC_IRQ, + .timer_info = &dm355_timer_info, + .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE), + .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), + .gpio_num = 104, + .gpio_irq = IRQ_DM355_GPIOBNK0, + .serial_dev = &dm355_serial_device, + .sram_dma = 0x00010000, + .sram_len = SZ_32K, +}; + +void __init dm355_init(void) +{ + davinci_common_init(&davinci_soc_info_dm355); +} + +static int __init dm355_init_devices(void) +{ + if (!cpu_is_davinci_dm355()) + return 0; + + davinci_cfg_reg(DM355_INT_EDMA_CC); + platform_device_register(&dm355_edma_device); + return 0; +} +postcore_initcall(dm355_init_devices); diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index d428ef192ea..fb5449b3c97 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -11,7 +11,11 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/clk.h> +#include <linux/serial_8250.h> #include <linux/platform_device.h> +#include <linux/gpio.h> + +#include <asm/mach/map.h> #include <mach/dm644x.h> #include <mach/clock.h> @@ -20,6 +24,9 @@ #include <mach/irqs.h> #include <mach/psc.h> #include <mach/mux.h> +#include <mach/time.h> +#include <mach/serial.h> +#include <mach/common.h> #include "clock.h" #include "mux.h" @@ -312,7 +319,14 @@ struct davinci_clk dm644x_clks[] = { CLK(NULL, NULL, NULL), }; -#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE) +static struct emac_platform_data dm644x_emac_pdata = { + .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET, + .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET, + .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET, + .mdio_reg_offset = DM644X_EMAC_MDIO_OFFSET, + .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE, + .version = EMAC_VERSION_1, +}; static struct resource dm644x_emac_resources[] = { { @@ -330,11 +344,15 @@ static struct resource dm644x_emac_resources[] = { static struct platform_device dm644x_emac_device = { .name = "davinci_emac", .id = 1, + .dev = { + .platform_data = &dm644x_emac_pdata, + }, .num_resources = ARRAY_SIZE(dm644x_emac_resources), .resource = dm644x_emac_resources, }; -#endif +#define PINMUX0 0x00 +#define PINMUX1 0x04 /* * Device specific mux setup @@ -343,6 +361,7 @@ static struct platform_device dm644x_emac_device = { * reg offset mask mode */ static const struct mux_config dm644x_pins[] = { +#ifdef CONFIG_DAVINCI_MUX MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true) MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true) MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true) @@ -383,8 +402,76 @@ MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true) MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true) MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false) +#endif }; +/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ +static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = { + [IRQ_VDINT0] = 2, + [IRQ_VDINT1] = 6, + [IRQ_VDINT2] = 6, + [IRQ_HISTINT] = 6, + [IRQ_H3AINT] = 6, + [IRQ_PRVUINT] = 6, + [IRQ_RSZINT] = 6, + [7] = 7, + [IRQ_VENCINT] = 6, + [IRQ_ASQINT] = 6, + [IRQ_IMXINT] = 6, + [IRQ_VLCDINT] = 6, + [IRQ_USBINT] = 4, + [IRQ_EMACINT] = 4, + [14] = 7, + [15] = 7, + [IRQ_CCINT0] = 5, /* dma */ + [IRQ_CCERRINT] = 5, /* dma */ + [IRQ_TCERRINT0] = 5, /* dma */ + [IRQ_TCERRINT] = 5, /* dma */ + [IRQ_PSCIN] = 7, + [21] = 7, + [IRQ_IDE] = 4, + [23] = 7, + [IRQ_MBXINT] = 7, + [IRQ_MBRINT] = 7, + [IRQ_MMCINT] = 7, + [IRQ_SDIOINT] = 7, + [28] = 7, + [IRQ_DDRINT] = 7, + [IRQ_AEMIFINT] = 7, + [IRQ_VLQINT] = 4, + [IRQ_TINT0_TINT12] = 2, /* clockevent */ + [IRQ_TINT0_TINT34] = 2, /* clocksource */ + [IRQ_TINT1_TINT12] = 7, /* DSP timer */ + [IRQ_TINT1_TINT34] = 7, /* system tick */ + [IRQ_PWMINT0] = 7, + [IRQ_PWMINT1] = 7, + [IRQ_PWMINT2] = 7, + [IRQ_I2C] = 3, + [IRQ_UARTINT0] = 3, + [IRQ_UARTINT1] = 3, + [IRQ_UARTINT2] = 3, + [IRQ_SPINT0] = 3, + [IRQ_SPINT1] = 3, + [45] = 7, + [IRQ_DSP2ARM0] = 4, + [IRQ_DSP2ARM1] = 4, + [IRQ_GPIO0] = 7, + [IRQ_GPIO1] = 7, + [IRQ_GPIO2] = 7, + [IRQ_GPIO3] = 7, + [IRQ_GPIO4] = 7, + [IRQ_GPIO5] = 7, + [IRQ_GPIO6] = 7, + [IRQ_GPIO7] = 7, + [IRQ_GPIOBNK0] = 7, + [IRQ_GPIOBNK1] = 7, + [IRQ_GPIOBNK2] = 7, + [IRQ_GPIOBNK3] = 7, + [IRQ_GPIOBNK4] = 7, + [IRQ_COMMTX] = 7, + [IRQ_COMMRX] = 7, + [IRQ_EMUINT] = 7, +}; /*----------------------------------------------------------------------*/ @@ -444,10 +531,118 @@ static struct platform_device dm644x_edma_device = { }; /*----------------------------------------------------------------------*/ + +static struct map_desc dm644x_io_desc[] = { + { + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(IO_PHYS), + .length = IO_SIZE, + .type = MT_DEVICE + }, + { + .virtual = SRAM_VIRT, + .pfn = __phys_to_pfn(0x00008000), + .length = SZ_16K, + /* MT_MEMORY_NONCACHED requires supersection alignment */ + .type = MT_DEVICE, + }, +}; + +/* Contents of JTAG ID register used to identify exact cpu type */ +static struct davinci_id dm644x_ids[] = { + { + .variant = 0x0, + .part_no = 0xb700, + .manufacturer = 0x017, + .cpu_id = DAVINCI_CPU_ID_DM6446, + .name = "dm6446", + }, +}; + +static void __iomem *dm644x_psc_bases[] = { + IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), +}; + +/* + * T0_BOT: Timer 0, bottom: clockevent source for hrtimers + * T0_TOP: Timer 0, top : clocksource for generic timekeeping + * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) + * T1_TOP: Timer 1, top : <unused> + */ +struct davinci_timer_info dm644x_timer_info = { + .timers = davinci_timer_instance, + .clockevent_id = T0_BOT, + .clocksource_id = T0_TOP, +}; + +static struct plat_serial8250_port dm644x_serial_platform_data[] = { + { + .mapbase = DAVINCI_UART0_BASE, + .irq = IRQ_UARTINT0, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DAVINCI_UART1_BASE, + .irq = IRQ_UARTINT1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .mapbase = DAVINCI_UART2_BASE, + .irq = IRQ_UARTINT2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM, + .regshift = 2, + }, + { + .flags = 0 + }, +}; + +static struct platform_device dm644x_serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = dm644x_serial_platform_data, + }, +}; + +static struct davinci_soc_info davinci_soc_info_dm644x = { + .io_desc = dm644x_io_desc, + .io_desc_num = ARRAY_SIZE(dm644x_io_desc), + .jtag_id_base = IO_ADDRESS(0x01c40028), + .ids = dm644x_ids, + .ids_num = ARRAY_SIZE(dm644x_ids), + .cpu_clks = dm644x_clks, + .psc_bases = dm644x_psc_bases, + .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases), + .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), + .pinmux_pins = dm644x_pins, + .pinmux_pins_num = ARRAY_SIZE(dm644x_pins), + .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), + .intc_type = DAVINCI_INTC_TYPE_AINTC, + .intc_irq_prios = dm644x_default_priorities, + .intc_irq_num = DAVINCI_N_AINTC_IRQ, + .timer_info = &dm644x_timer_info, + .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE), + .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), + .gpio_num = 71, + .gpio_irq = IRQ_GPIOBNK0, + .serial_dev = &dm644x_serial_device, + .emac_pdata = &dm644x_emac_pdata, + .sram_dma = 0x00008000, + .sram_len = SZ_16K, +}; + void __init dm644x_init(void) { - davinci_clk_init(dm644x_clks); - davinci_mux_register(dm644x_pins, ARRAY_SIZE(dm644x_pins)); + davinci_common_init(&davinci_soc_info_dm644x); } static int __init dm644x_init_devices(void) @@ -456,6 +651,7 @@ static int __init dm644x_init_devices(void) return 0; platform_device_register(&dm644x_edma_device); + platform_device_register(&dm644x_emac_device); return 0; } postcore_initcall(dm644x_init_devices); diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c new file mode 100644 index 00000000000..334f0711e0f --- /dev/null +++ b/arch/arm/mach-davinci/dm646x.c @@ -0,0 +1,636 @@ +/* + * TI DaVinci DM644x chip specific setup + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * 2007 (c) Deep Root Systems, LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/serial_8250.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> + +#include <asm/mach/map.h> + +#include <mach/dm646x.h> +#include <mach/clock.h> +#include <mach/cputype.h> +#include <mach/edma.h> +#include <mach/irqs.h> +#include <mach/psc.h> +#include <mach/mux.h> +#include <mach/time.h> +#include <mach/serial.h> +#include <mach/common.h> + +#include "clock.h" +#include "mux.h" + +/* + * Device specific clocks + */ +#define DM646X_REF_FREQ 27000000 +#define DM646X_AUX_FREQ 24000000 + +static struct pll_data pll1_data = { + .num = 1, + .phys_base = DAVINCI_PLL1_BASE, +}; + +static struct pll_data pll2_data = { + .num = 2, + .phys_base = DAVINCI_PLL2_BASE, +}; + +static struct clk ref_clk = { + .name = "ref_clk", + .rate = DM646X_REF_FREQ, +}; + +static struct clk aux_clkin = { + .name = "aux_clkin", + .rate = DM646X_AUX_FREQ, +}; + +static struct clk pll1_clk = { + .name = "pll1", + .parent = &ref_clk, + .pll_data = &pll1_data, + .flags = CLK_PLL, +}; + +static struct clk pll1_sysclk1 = { + .name = "pll1_sysclk1", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + +static struct clk pll1_sysclk2 = { + .name = "pll1_sysclk2", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV2, +}; + +static struct clk pll1_sysclk3 = { + .name = "pll1_sysclk3", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV3, +}; + +static struct clk pll1_sysclk4 = { + .name = "pll1_sysclk4", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV4, +}; + +static struct clk pll1_sysclk5 = { + .name = "pll1_sysclk5", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV5, +}; + +static struct clk pll1_sysclk6 = { + .name = "pll1_sysclk6", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV6, +}; + +static struct clk pll1_sysclk8 = { + .name = "pll1_sysclk8", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV8, +}; + +static struct clk pll1_sysclk9 = { + .name = "pll1_sysclk9", + .parent = &pll1_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV9, +}; + +static struct clk pll1_sysclkbp = { + .name = "pll1_sysclkbp", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, + .div_reg = BPDIV, +}; + +static struct clk pll1_aux_clk = { + .name = "pll1_aux_clk", + .parent = &pll1_clk, + .flags = CLK_PLL | PRE_PLL, +}; + +static struct clk pll2_clk = { + .name = "pll2_clk", + .parent = &ref_clk, + .pll_data = &pll2_data, + .flags = CLK_PLL, +}; + +static struct clk pll2_sysclk1 = { + .name = "pll2_sysclk1", + .parent = &pll2_clk, + .flags = CLK_PLL, + .div_reg = PLLDIV1, +}; + +static struct clk dsp_clk = { + .name = "dsp", + .parent = &pll1_sysclk1, + .lpsc = DM646X_LPSC_C64X_CPU, + .flags = PSC_DSP, + .usecount = 1, /* REVISIT how to disable? */ +}; + +static struct clk arm_clk = { + .name = "arm", + .parent = &pll1_sysclk2, + .lpsc = DM646X_LPSC_ARM, + .flags = ALWAYS_ENABLED, +}; + +static struct clk uart0_clk = { + .name = "uart0", + .parent = &aux_clkin, + .lpsc = DM646X_LPSC_UART0, +}; + +static struct clk uart1_clk = { + .name = "uart1", + .parent = &aux_clkin, + .lpsc = DM646X_LPSC_UART1, +}; + +static struct clk uart2_clk = { + .name = "uart2", + .parent = &aux_clkin, + .lpsc = DM646X_LPSC_UART2, +}; + +static struct clk i2c_clk = { + .name = "I2CCLK", + .parent = &pll1_sysclk3, + .lpsc = DM646X_LPSC_I2C, +}; + +static struct clk gpio_clk = { + .name = "gpio", + .parent = &pll1_sysclk3, + .lpsc = DM646X_LPSC_GPIO, +}; + +static struct clk aemif_clk = { + .name = "aemif", + .parent = &pll1_sysclk3, + .lpsc = DM646X_LPSC_AEMIF, + .flags = ALWAYS_ENABLED, +}; + +static struct clk emac_clk = { + .name = "emac", + .parent = &pll1_sysclk3, + .lpsc = DM646X_LPSC_EMAC, +}; + +static struct clk pwm0_clk = { + .name = "pwm0", + .parent = &pll1_sysclk3, + .lpsc = DM646X_LPSC_PWM0, + .usecount = 1, /* REVIST: disabling hangs system */ +}; + +static struct clk pwm1_clk = { + .name = "pwm1", + .parent = &pll1_sysclk3, + .lpsc = DM646X_LPSC_PWM1, + .usecount = 1, /* REVIST: disabling hangs system */ +}; + +static struct clk timer0_clk = { + .name = "timer0", + .parent = &pll1_sysclk3, + .lpsc = DM646X_LPSC_TIMER0, +}; + +static struct clk timer1_clk = { + .name = "timer1", + .parent = &pll1_sysclk3, + .lpsc = DM646X_LPSC_TIMER1, +}; + +static struct clk timer2_clk = { + .name = "timer2", + .parent = &pll1_sysclk3, + .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */ +}; + +static struct clk vpif0_clk = { + .name = "vpif0", + .parent = &ref_clk, + .lpsc = DM646X_LPSC_VPSSMSTR, + .flags = ALWAYS_ENABLED, +}; + +static struct clk vpif1_clk = { + .name = "vpif1", + .parent = &ref_clk, + .lpsc = DM646X_LPSC_VPSSSLV, + .flags = ALWAYS_ENABLED, +}; + +struct davinci_clk dm646x_clks[] = { + CLK(NULL, "ref", &ref_clk), + CLK(NULL, "aux", &aux_clkin), + CLK(NULL, "pll1", &pll1_clk), + CLK(NULL, "pll1_sysclk", &pll1_sysclk1), + CLK(NULL, "pll1_sysclk", &pll1_sysclk2), + CLK(NULL, "pll1_sysclk", &pll1_sysclk3), + CLK(NULL, "pll1_sysclk", &pll1_sysclk4), + CLK(NULL, "pll1_sysclk", &pll1_sysclk5), + CLK(NULL, "pll1_sysclk", &pll1_sysclk6), + CLK(NULL, "pll1_sysclk", &pll1_sysclk8), + CLK(NULL, "pll1_sysclk", &pll1_sysclk9), + CLK(NULL, "pll1_sysclk", &pll1_sysclkbp), + CLK(NULL, "pll1_aux", &pll1_aux_clk), + CLK(NULL, "pll2", &pll2_clk), + CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), + CLK(NULL, "dsp", &dsp_clk), + CLK(NULL, "arm", &arm_clk), + CLK(NULL, "uart0", &uart0_clk), + CLK(NULL, "uart1", &uart1_clk), + CLK(NULL, "uart2", &uart2_clk), + CLK("i2c_davinci.1", NULL, &i2c_clk), + CLK(NULL, "gpio", &gpio_clk), + CLK(NULL, "aemif", &aemif_clk), + CLK("davinci_emac.1", NULL, &emac_clk), + CLK(NULL, "pwm0", &pwm0_clk), + CLK(NULL, "pwm1", &pwm1_clk), + CLK(NULL, "timer0", &timer0_clk), + CLK(NULL, "timer1", &timer1_clk), + CLK("watchdog", NULL, &timer2_clk), + CLK(NULL, "vpif0", &vpif0_clk), + CLK(NULL, "vpif1", &vpif1_clk), + CLK(NULL, NULL, NULL), +}; + +static struct emac_platform_data dm646x_emac_pdata = { + .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET, + .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET, + .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET, + .mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET, + .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE, + .version = EMAC_VERSION_2, +}; + +static struct resource dm646x_emac_resources[] = { + { + .start = DM646X_EMAC_BASE, + .end = DM646X_EMAC_BASE + 0x47ff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_DM646X_EMACRXTHINT, + .end = IRQ_DM646X_EMACRXTHINT, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DM646X_EMACRXINT, + .end = IRQ_DM646X_EMACRXINT, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DM646X_EMACTXINT, + .end = IRQ_DM646X_EMACTXINT, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_DM646X_EMACMISCINT, + .end = IRQ_DM646X_EMACMISCINT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dm646x_emac_device = { + .name = "davinci_emac", + .id = 1, + .dev = { + .platform_data = &dm646x_emac_pdata, + }, + .num_resources = ARRAY_SIZE(dm646x_emac_resources), + .resource = dm646x_emac_resources, +}; + +#define PINMUX0 0x00 +#define PINMUX1 0x04 + +/* + * Device specific mux setup + * + * soc description mux mode mode mux dbg + * reg offset mask mode + */ +static const struct mux_config dm646x_pins[] = { +#ifdef CONFIG_DAVINCI_MUX +MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true) + +MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false) + +MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false) + +MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true) + +MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true) + +MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true) + +MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true) + +MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true) + +MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true) + +MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true) + +MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true) + +MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true) + +MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true) + +MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true) +#endif +}; + +static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { + [IRQ_DM646X_VP_VERTINT0] = 7, + [IRQ_DM646X_VP_VERTINT1] = 7, + [IRQ_DM646X_VP_VERTINT2] = 7, + [IRQ_DM646X_VP_VERTINT3] = 7, + [IRQ_DM646X_VP_ERRINT] = 7, + [IRQ_DM646X_RESERVED_1] = 7, + [IRQ_DM646X_RESERVED_2] = 7, + [IRQ_DM646X_WDINT] = 7, + [IRQ_DM646X_CRGENINT0] = 7, + [IRQ_DM646X_CRGENINT1] = 7, + [IRQ_DM646X_TSIFINT0] = 7, + [IRQ_DM646X_TSIFINT1] = 7, + [IRQ_DM646X_VDCEINT] = 7, + [IRQ_DM646X_USBINT] = 7, + [IRQ_DM646X_USBDMAINT] = 7, + [IRQ_DM646X_PCIINT] = 7, + [IRQ_CCINT0] = 7, /* dma */ + [IRQ_CCERRINT] = 7, /* dma */ + [IRQ_TCERRINT0] = 7, /* dma */ + [IRQ_TCERRINT] = 7, /* dma */ + [IRQ_DM646X_TCERRINT2] = 7, + [IRQ_DM646X_TCERRINT3] = 7, + [IRQ_DM646X_IDE] = 7, + [IRQ_DM646X_HPIINT] = 7, + [IRQ_DM646X_EMACRXTHINT] = 7, + [IRQ_DM646X_EMACRXINT] = 7, + [IRQ_DM646X_EMACTXINT] = 7, + [IRQ_DM646X_EMACMISCINT] = 7, + [IRQ_DM646X_MCASP0TXINT] = 7, + [IRQ_DM646X_MCASP0RXINT] = 7, + [IRQ_AEMIFINT] = 7, + [IRQ_DM646X_RESERVED_3] = 7, + [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */ + [IRQ_TINT0_TINT34] = 7, /* clocksource */ + [IRQ_TINT1_TINT12] = 7, /* DSP timer */ + [IRQ_TINT1_TINT34] = 7, /* system tick */ + [IRQ_PWMINT0] = 7, + [IRQ_PWMINT1] = 7, + [IRQ_DM646X_VLQINT] = 7, + [IRQ_I2C] = 7, + [IRQ_UARTINT0] = 7, + [IRQ_UARTINT1] = 7, + [IRQ_DM646X_UARTINT2] = 7, + [IRQ_DM646X_SPINT0] = 7, + [IRQ_DM646X_SPINT1] = 7, + [IRQ_DM646X_DSP2ARMINT] = 7, + [IRQ_DM646X_RESERVED_4] = 7, + [IRQ_DM646X_PSCINT] = 7, + [IRQ_DM646X_GPIO0] = 7, + [IRQ_DM646X_GPIO1] = 7, + [IRQ_DM646X_GPIO2] = 7, + [IRQ_DM646X_GPIO3] = 7, + [IRQ_DM646X_GPIO4] = 7, + [IRQ_DM646X_GPIO5] = 7, + [IRQ_DM646X_GPIO6] = 7, + [IRQ_DM646X_GPIO7] = 7, + [IRQ_DM646X_GPIOBNK0] = 7, + [IRQ_DM646X_GPIOBNK1] = 7, + [IRQ_DM646X_GPIOBNK2] = 7, + [IRQ_DM646X_DDRINT] = 7, + [IRQ_DM646X_AEMIFINT] = 7, + [IRQ_COMMTX] = 7, + [IRQ_COMMRX] = 7, + [IRQ_EMUINT] = 7, +}; + +/*----------------------------------------------------------------------*/ + +static const s8 dma_chan_dm646x_no_event[] = { + 0, 1, 2, 3, 13, + 14, 15, 24, 25, 26, + 27, 30, 31, 54, 55, + 56, + -1 +}; + +static struct edma_soc_info dm646x_edma_info = { + .n_channel = 64, + .n_region = 6, /* 0-1, 4-7 */ + .n_slot = 512, + .n_tc = 4, + .noevent = dma_chan_dm646x_no_event, +}; + +static struct resource edma_resources[] = { + { + .name = "edma_cc", + .start = 0x01c00000, + .end = 0x01c00000 + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc0", + .start = 0x01c10000, + .end = 0x01c10000 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc1", + .start = 0x01c10400, + .end = 0x01c10400 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc2", + .start = 0x01c10800, + .end = 0x01c10800 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc3", + .start = 0x01c10c00, + .end = 0x01c10c00 + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_CCINT0, + .flags = IORESOURCE_IRQ, + }, + { + .start = IRQ_CCERRINT, + .flags = IORESOURCE_IRQ, + }, + /* not using TC*_ERR */ +}; + +static struct platform_device dm646x_edma_device = { + .name = "edma", + .id = -1, + .dev.platform_data = &dm646x_edma_info, + .num_resources = ARRAY_SIZE(edma_resources), + .resource = edma_resources, +}; + +/*----------------------------------------------------------------------*/ + +static struct map_desc dm646x_io_desc[] = { + { + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(IO_PHYS), + .length = IO_SIZE, + .type = MT_DEVICE + }, + { + .virtual = SRAM_VIRT, + .pfn = __phys_to_pfn(0x00010000), + .length = SZ_32K, + /* MT_MEMORY_NONCACHED requires supersection alignment */ + .type = MT_DEVICE, + }, +}; + +/* Contents of JTAG ID register used to identify exact cpu type */ +static struct davinci_id dm646x_ids[] = { + { + .variant = 0x0, + .part_no = 0xb770, + .manufacturer = 0x017, + .cpu_id = DAVINCI_CPU_ID_DM6467, + .name = "dm6467", + }, +}; + +static void __iomem *dm646x_psc_bases[] = { + IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), +}; + +/* + * T0_BOT: Timer 0, bottom: clockevent source for hrtimers + * T0_TOP: Timer 0, top : clocksource for generic timekeeping + * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) + * T1_TOP: Timer 1, top : <unused> + */ +struct davinci_timer_info dm646x_timer_info = { + .timers = davinci_timer_instance, + .clockevent_id = T0_BOT, + .clocksource_id = T0_TOP, +}; + +static struct plat_serial8250_port dm646x_serial_platform_data[] = { + { + .mapbase = DAVINCI_UART0_BASE, + .irq = IRQ_UARTINT0, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM32, + .regshift = 2, + }, + { + .mapbase = DAVINCI_UART1_BASE, + .irq = IRQ_UARTINT1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM32, + .regshift = 2, + }, + { + .mapbase = DAVINCI_UART2_BASE, + .irq = IRQ_DM646X_UARTINT2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_IOREMAP, + .iotype = UPIO_MEM32, + .regshift = 2, + }, + { + .flags = 0 + }, +}; + +static struct platform_device dm646x_serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = dm646x_serial_platform_data, + }, +}; + +static struct davinci_soc_info davinci_soc_info_dm646x = { + .io_desc = dm646x_io_desc, + .io_desc_num = ARRAY_SIZE(dm646x_io_desc), + .jtag_id_base = IO_ADDRESS(0x01c40028), + .ids = dm646x_ids, + .ids_num = ARRAY_SIZE(dm646x_ids), + .cpu_clks = dm646x_clks, + .psc_bases = dm646x_psc_bases, + .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases), + .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), + .pinmux_pins = dm646x_pins, + .pinmux_pins_num = ARRAY_SIZE(dm646x_pins), + .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), + .intc_type = DAVINCI_INTC_TYPE_AINTC, + .intc_irq_prios = dm646x_default_priorities, + .intc_irq_num = DAVINCI_N_AINTC_IRQ, + .timer_info = &dm646x_timer_info, + .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE), + .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), + .gpio_num = 43, /* Only 33 usable */ + .gpio_irq = IRQ_DM646X_GPIOBNK0, + .serial_dev = &dm646x_serial_device, + .emac_pdata = &dm646x_emac_pdata, + .sram_dma = 0x10010000, + .sram_len = SZ_32K, +}; + +void __init dm646x_init(void) +{ + davinci_common_init(&davinci_soc_info_dm646x); +} + +static int __init dm646x_init_devices(void) +{ + if (!cpu_is_davinci_dm646x()) + return 0; + + platform_device_register(&dm646x_edma_device); + platform_device_register(&dm646x_emac_device); + return 0; +} +postcore_initcall(dm646x_init_devices); diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index 1aba41c6351..1b6532159c5 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c @@ -23,6 +23,7 @@ #include <mach/cputype.h> #include <mach/irqs.h> #include <mach/hardware.h> +#include <mach/common.h> #include <mach/gpio.h> #include <asm/mach/irq.h> @@ -37,14 +38,13 @@ struct davinci_gpio { static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; -static unsigned __initdata ngpio; - /* create a non-inlined version */ static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio) { return __gpio_to_controller(gpio); } +static int __init davinci_gpio_irq_setup(void); /*--------------------------------------------------------------------------*/ @@ -115,23 +115,16 @@ davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) static int __init davinci_gpio_setup(void) { int i, base; + unsigned ngpio; + struct davinci_soc_info *soc_info = &davinci_soc_info; - /* The gpio banks conceptually expose a segmented bitmap, + /* + * The gpio banks conceptually expose a segmented bitmap, * and "ngpio" is one more than the largest zero-based * bit index that's valid. */ - if (cpu_is_davinci_dm355()) { /* or dm335() */ - ngpio = 104; - } else if (cpu_is_davinci_dm644x()) { /* or dm337() */ - ngpio = 71; - } else if (cpu_is_davinci_dm646x()) { - /* NOTE: each bank has several "reserved" bits, - * unusable as GPIOs. Only 33 of the GPIO numbers - * are usable, and we're not rejecting the others. - */ - ngpio = 43; - } else { - /* if cpu_is_davinci_dm643x() ngpio = 111 */ + ngpio = soc_info->gpio_num; + if (ngpio == 0) { pr_err("GPIO setup: how many GPIOs?\n"); return -EINVAL; } @@ -157,6 +150,7 @@ static int __init davinci_gpio_setup(void) gpiochip_add(&chips[i].chip); } + davinci_gpio_irq_setup(); return 0; } pure_initcall(davinci_gpio_setup); @@ -187,10 +181,15 @@ static void gpio_irq_enable(unsigned irq) { struct gpio_controller *__iomem g = get_irq_chip_data(irq); u32 mask = __gpio_mask(irq_to_gpio(irq)); + unsigned status = irq_desc[irq].status; + + status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; + if (!status) + status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; - if (irq_desc[irq].status & IRQ_TYPE_EDGE_FALLING) + if (status & IRQ_TYPE_EDGE_FALLING) __raw_writel(mask, &g->set_falling); - if (irq_desc[irq].status & IRQ_TYPE_EDGE_RISING) + if (status & IRQ_TYPE_EDGE_RISING) __raw_writel(mask, &g->set_rising); } @@ -205,10 +204,13 @@ static int gpio_irq_type(unsigned irq, unsigned trigger) irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; irq_desc[irq].status |= trigger; - __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) - ? &g->set_falling : &g->clr_falling); - __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) - ? &g->set_rising : &g->clr_rising); + /* don't enable the IRQ if it's currently disabled */ + if (irq_desc[irq].depth == 0) { + __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) + ? &g->set_falling : &g->clr_falling); + __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) + ? &g->set_rising : &g->clr_rising); + } return 0; } @@ -230,6 +232,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) mask <<= 16; /* temporarily mask (level sensitive) parent IRQ */ + desc->chip->mask(irq); desc->chip->ack(irq); while (1) { u32 status; @@ -268,17 +271,15 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) static int __init davinci_gpio_irq_setup(void) { unsigned gpio, irq, bank; - unsigned bank_irq; struct clk *clk; u32 binten = 0; + unsigned ngpio, bank_irq; + struct davinci_soc_info *soc_info = &davinci_soc_info; + + ngpio = soc_info->gpio_num; - if (cpu_is_davinci_dm355()) { /* or dm335() */ - bank_irq = IRQ_DM355_GPIOBNK0; - } else if (cpu_is_davinci_dm644x()) { - bank_irq = IRQ_GPIOBNK0; - } else if (cpu_is_davinci_dm646x()) { - bank_irq = IRQ_DM646X_GPIOBNK0; - } else { + bank_irq = soc_info->gpio_irq; + if (bank_irq == 0) { printk(KERN_ERR "Don't know first GPIO bank IRQ.\n"); return -EINVAL; } @@ -318,11 +319,9 @@ static int __init davinci_gpio_irq_setup(void) /* BINTEN -- per-bank interrupt enable. genirq would also let these * bits be set/cleared dynamically. */ - __raw_writel(binten, (void *__iomem) - IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08)); + __raw_writel(binten, soc_info->gpio_base + 0x08); printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); return 0; } -arch_initcall(davinci_gpio_irq_setup); diff --git a/arch/arm/mach-davinci/id.c b/arch/arm/mach-davinci/id.c deleted file mode 100644 index 018b994cd79..00000000000 --- a/arch/arm/mach-davinci/id.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Davinci CPU identification code - * - * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com> - * - * Derived from OMAP1 CPU identification code. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> - -#define JTAG_ID_BASE IO_ADDRESS(0x01c40028) - -static unsigned int davinci_revision; - -struct davinci_id { - u8 variant; /* JTAG ID bits 31:28 */ - u16 part_no; /* JTAG ID bits 27:12 */ - u32 manufacturer; /* JTAG ID bits 11:1 */ - u32 type; /* Cpu id bits [31:8], cpu class bits [7:0] */ -}; - -/* Register values to detect the DaVinci version */ -static struct davinci_id davinci_ids[] __initdata = { - { - /* DM6446 */ - .part_no = 0xb700, - .variant = 0x0, - .manufacturer = 0x017, - .type = 0x64460000, - }, - { - /* DM646X */ - .part_no = 0xb770, - .variant = 0x0, - .manufacturer = 0x017, - .type = 0x64670000, - }, - { - /* DM355 */ - .part_no = 0xb73b, - .variant = 0x0, - .manufacturer = 0x00f, - .type = 0x03550000, - }, -}; - -/* - * Get Device Part No. from JTAG ID register - */ -static u16 __init davinci_get_part_no(void) -{ - u32 dev_id, part_no; - - dev_id = __raw_readl(JTAG_ID_BASE); - - part_no = ((dev_id >> 12) & 0xffff); - - return part_no; -} - -/* - * Get Device Revision from JTAG ID register - */ -static u8 __init davinci_get_variant(void) -{ - u32 variant; - - variant = __raw_readl(JTAG_ID_BASE); - - variant = (variant >> 28) & 0xf; - - return variant; -} - -unsigned int davinci_rev(void) -{ - return davinci_revision >> 16; -} -EXPORT_SYMBOL(davinci_rev); - -void __init davinci_check_revision(void) -{ - int i; - u16 part_no; - u8 variant; - - part_no = davinci_get_part_no(); - variant = davinci_get_variant(); - - /* First check only the major version in a safe way */ - for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { - if (part_no == (davinci_ids[i].part_no)) { - davinci_revision = davinci_ids[i].type; - break; - } - } - - /* Check if we can find the dev revision */ - for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) { - if (part_no == davinci_ids[i].part_no && - variant == davinci_ids[i].variant) { - davinci_revision = davinci_ids[i].type; - break; - } - } - - printk(KERN_INFO "DaVinci DM%04x variant 0x%x\n", - davinci_rev(), variant); -} diff --git a/arch/arm/mach-davinci/include/mach/board-dm6446evm.h b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h deleted file mode 100644 index 3216f21c123..00000000000 --- a/arch/arm/mach-davinci/include/mach/board-dm6446evm.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * DaVinci DM6446 EVM board specific headers - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * 2007 (c) Deep Root Systems, LLC. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or ifndef. - */ - -#ifndef _MACH_DAVINCI_DM6446EVM_H -#define _MACH_DAVINCI_DM6446EVM_H - -#include <linux/types.h> - -int dm6446evm_eeprom_read(char *buf, off_t off, size_t count); -int dm6446evm_eeprom_write(char *buf, off_t off, size_t count); - -#endif diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h index 19177097625..a1f03b606d8 100644 --- a/arch/arm/mach-davinci/include/mach/common.h +++ b/arch/arm/mach-davinci/include/mach/common.h @@ -17,7 +17,8 @@ struct sys_timer; extern struct sys_timer davinci_timer; extern void davinci_irq_init(void); -extern void davinci_map_common_io(void); +extern void __iomem *davinci_intc_base; +extern int davinci_intc_type; /* parameters describe VBUS sourcing for host mode */ extern void setup_usb(unsigned mA, unsigned potpgt_msec); @@ -25,4 +26,56 @@ extern void setup_usb(unsigned mA, unsigned potpgt_msec); /* parameters describe VBUS sourcing for host mode */ extern void setup_usb(unsigned mA, unsigned potpgt_msec); +struct davinci_timer_instance { + void __iomem *base; + u32 bottom_irq; + u32 top_irq; + unsigned long cmp_off; + unsigned int cmp_irq; +}; + +struct davinci_timer_info { + struct davinci_timer_instance *timers; + unsigned int clockevent_id; + unsigned int clocksource_id; +}; + +/* SoC specific init support */ +struct davinci_soc_info { + struct map_desc *io_desc; + unsigned long io_desc_num; + u32 cpu_id; + u32 jtag_id; + void __iomem *jtag_id_base; + struct davinci_id *ids; + unsigned long ids_num; + struct davinci_clk *cpu_clks; + void __iomem **psc_bases; + unsigned long psc_bases_num; + void __iomem *pinmux_base; + const struct mux_config *pinmux_pins; + unsigned long pinmux_pins_num; + void __iomem *intc_base; + int intc_type; + u8 *intc_irq_prios; + unsigned long intc_irq_num; + struct davinci_timer_info *timer_info; + void __iomem *wdt_base; + void __iomem *gpio_base; + unsigned gpio_num; + unsigned gpio_irq; + struct platform_device *serial_dev; + struct emac_platform_data *emac_pdata; + dma_addr_t sram_dma; + unsigned sram_len; +}; + +extern struct davinci_soc_info davinci_soc_info; + +extern void davinci_common_init(struct davinci_soc_info *soc_info); + +/* standard place to map on-chip SRAMs; they *may* support DMA */ +#define SRAM_VIRT 0xfffe0000 +#define SRAM_SIZE SZ_128K + #endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */ diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h new file mode 100644 index 00000000000..c4d27eec806 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/cp_intc.h @@ -0,0 +1,57 @@ +/* + * TI Common Platform Interrupt Controller (cp_intc) definitions + * + * Author: Steve Chen <schen@mvista.com> + * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com> + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ +#ifndef __ASM_HARDWARE_CP_INTC_H +#define __ASM_HARDWARE_CP_INTC_H + +#define CP_INTC_REV 0x00 +#define CP_INTC_CTRL 0x04 +#define CP_INTC_HOST_CTRL 0x0C +#define CP_INTC_GLOBAL_ENABLE 0x10 +#define CP_INTC_GLOBAL_NESTING_LEVEL 0x1C +#define CP_INTC_SYS_STAT_IDX_SET 0x20 +#define CP_INTC_SYS_STAT_IDX_CLR 0x24 +#define CP_INTC_SYS_ENABLE_IDX_SET 0x28 +#define CP_INTC_SYS_ENABLE_IDX_CLR 0x2C +#define CP_INTC_GLOBAL_WAKEUP_ENABLE 0x30 +#define CP_INTC_HOST_ENABLE_IDX_SET 0x34 +#define CP_INTC_HOST_ENABLE_IDX_CLR 0x38 +#define CP_INTC_PACING_PRESCALE 0x40 +#define CP_INTC_VECTOR_BASE 0x50 +#define CP_INTC_VECTOR_SIZE 0x54 +#define CP_INTC_VECTOR_NULL 0x58 +#define CP_INTC_PRIO_IDX 0x80 +#define CP_INTC_PRIO_VECTOR 0x84 +#define CP_INTC_SECURE_ENABLE 0x90 +#define CP_INTC_SECURE_PRIO_IDX 0x94 +#define CP_INTC_PACING_PARAM(n) (0x0100 + (n << 4)) +#define CP_INTC_PACING_DEC(n) (0x0104 + (n << 4)) +#define CP_INTC_PACING_MAP(n) (0x0108 + (n << 4)) +#define CP_INTC_SYS_RAW_STAT(n) (0x0200 + (n << 2)) +#define CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2)) +#define CP_INTC_SYS_ENABLE_SET(n) (0x0300 + (n << 2)) +#define CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2)) +#define CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2)) +#define CP_INTC_HOST_MAP(n) (0x0800 + (n << 2)) +#define CP_INTC_HOST_PRIO_IDX(n) (0x0900 + (n << 2)) +#define CP_INTC_SYS_POLARITY(n) (0x0D00 + (n << 2)) +#define CP_INTC_SYS_TYPE(n) (0x0D80 + (n << 2)) +#define CP_INTC_WAKEUP_ENABLE(n) (0x0E00 + (n << 2)) +#define CP_INTC_DEBUG_SELECT(n) (0x0F00 + (n << 2)) +#define CP_INTC_SYS_SECURE_ENABLE(n) (0x1000 + (n << 2)) +#define CP_INTC_HOST_NESTING_LEVEL(n) (0x1100 + (n << 2)) +#define CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2)) +#define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2)) +#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2)) + +void __init cp_intc_init(void __iomem *base, unsigned short num_irq, + u8 *irq_prio); + +#endif /* __ASM_HARDWARE_CP_INTC_H */ diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h index 27cfb1b3a66..d12a5ed2959 100644 --- a/arch/arm/mach-davinci/include/mach/cputype.h +++ b/arch/arm/mach-davinci/include/mach/cputype.h @@ -16,17 +16,30 @@ #ifndef _ASM_ARCH_CPU_H #define _ASM_ARCH_CPU_H -extern unsigned int davinci_rev(void); +#include <mach/common.h> -#define IS_DAVINCI_CPU(type, id) \ -static inline int is_davinci_dm ##type(void) \ -{ \ - return (davinci_rev() == (id)) ? 1 : 0; \ +struct davinci_id { + u8 variant; /* JTAG ID bits 31:28 */ + u16 part_no; /* JTAG ID bits 27:12 */ + u16 manufacturer; /* JTAG ID bits 11:1 */ + u32 cpu_id; + char *name; +}; + +/* Can use lower 16 bits of cpu id for a variant when required */ +#define DAVINCI_CPU_ID_DM6446 0x64460000 +#define DAVINCI_CPU_ID_DM6467 0x64670000 +#define DAVINCI_CPU_ID_DM355 0x03550000 + +#define IS_DAVINCI_CPU(type, id) \ +static inline int is_davinci_ ##type(void) \ +{ \ + return (davinci_soc_info.cpu_id == (id)); \ } -IS_DAVINCI_CPU(644x, 0x6446) -IS_DAVINCI_CPU(646x, 0x6467) -IS_DAVINCI_CPU(355, 0x355) +IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446) +IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467) +IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) #ifdef CONFIG_ARCH_DAVINCI_DM644x #define cpu_is_davinci_dm644x() is_davinci_dm644x() diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S index e6c0f0d5d06..de3fc2182b4 100644 --- a/arch/arm/mach-davinci/include/mach/debug-macro.S +++ b/arch/arm/mach-davinci/include/mach/debug-macro.S @@ -9,6 +9,16 @@ * or implied. */ +/* Modifications + * Jan 2009 Chaithrika U S Added senduart, busyuart, waituart + * macros, based on debug-8250.S file + * but using 32-bit accesses required for + * some davinci devices. + */ + +#include <linux/serial_reg.h> +#define UART_SHIFT 2 + .macro addruart, rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? @@ -17,5 +27,22 @@ orr \rx, \rx, #0x00c20000 @ UART 0 .endm -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> + .macro senduart,rd,rx + str \rd, [\rx, #UART_TX << UART_SHIFT] + .endm + + .macro busyuart,rd,rx +1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT] + and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE + teq \rd, #UART_LSR_TEMT | UART_LSR_THRE + bne 1002b + .endm + + .macro waituart,rd,rx +#ifdef FLOW_CONTROL +1001: ldr \rd, [\rx, #UART_MSR << UART_SHIFT] + tst \rd, #UART_MSR_CTS + beq 1001b +#endif + .endm + diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h new file mode 100644 index 00000000000..54903b72438 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/dm355.h @@ -0,0 +1,22 @@ +/* + * Chip specific defines for DM355 SoC + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * 2007 (c) Deep Root Systems, LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_DM355_H +#define __ASM_ARCH_DM355_H + +#include <mach/hardware.h> + +struct spi_board_info; + +void __init dm355_init(void); +void dm355_init_spi0(unsigned chipselect_mask, + struct spi_board_info *info, unsigned len); + +#endif /* __ASM_ARCH_DM355_H */ diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h index 3dcb9f4e58b..15d42b92a8c 100644 --- a/arch/arm/mach-davinci/include/mach/dm644x.h +++ b/arch/arm/mach-davinci/include/mach/dm644x.h @@ -24,6 +24,7 @@ #include <linux/platform_device.h> #include <mach/hardware.h> +#include <mach/emac.h> #define DM644X_EMAC_BASE (0x01C80000) #define DM644X_EMAC_CNTRL_OFFSET (0x0000) diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h new file mode 100644 index 00000000000..1fc764c8646 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/dm646x.h @@ -0,0 +1,26 @@ +/* + * Chip specific defines for DM646x SoC + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * 2007 (c) Deep Root Systems, LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_DM646X_H +#define __ASM_ARCH_DM646X_H + +#include <mach/hardware.h> +#include <mach/emac.h> + +#define DM646X_EMAC_BASE (0x01C80000) +#define DM646X_EMAC_CNTRL_OFFSET (0x0000) +#define DM646X_EMAC_CNTRL_MOD_OFFSET (0x1000) +#define DM646X_EMAC_CNTRL_RAM_OFFSET (0x2000) +#define DM646X_EMAC_MDIO_OFFSET (0x4000) +#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000) + +void __init dm646x_init(void); + +#endif /* __ASM_ARCH_DM646X_H */ diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h index f6fc5396daf..24a379239d7 100644 --- a/arch/arm/mach-davinci/include/mach/edma.h +++ b/arch/arm/mach-davinci/include/mach/edma.h @@ -208,10 +208,6 @@ void edma_clear_event(unsigned channel); void edma_pause(unsigned channel); void edma_resume(unsigned channel); -/* UNRELATED TO DMA */ -int davinci_alloc_iram(unsigned size); -void davinci_free_iram(unsigned addr, unsigned size); - /* platform_data for EDMA driver */ struct edma_soc_info { diff --git a/arch/arm/mach-davinci/include/mach/emac.h b/arch/arm/mach-davinci/include/mach/emac.h new file mode 100644 index 00000000000..beff4fb7c84 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/emac.h @@ -0,0 +1,36 @@ +/* + * TI DaVinci EMAC platform support + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * 2007 (c) Deep Root Systems, LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef _MACH_DAVINCI_EMAC_H +#define _MACH_DAVINCI_EMAC_H + +#include <linux/if_ether.h> +#include <linux/memory.h> + +struct emac_platform_data { + char mac_addr[ETH_ALEN]; + u32 ctrl_reg_offset; + u32 ctrl_mod_reg_offset; + u32 ctrl_ram_offset; + u32 mdio_reg_offset; + u32 ctrl_ram_size; + u32 phy_mask; + u32 mdio_max_freq; + u8 rmii_en; + u8 version; +}; + +enum { + EMAC_VERSION_1, /* DM644x */ + EMAC_VERSION_2, /* DM646x */ +}; + +void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context); +#endif diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S index 039b84f933b..fbdebc7cb40 100644 --- a/arch/arm/mach-davinci/include/mach/entry-macro.S +++ b/arch/arm/mach-davinci/include/mach/entry-macro.S @@ -15,17 +15,36 @@ .endm .macro get_irqnr_preamble, base, tmp - ldr \base, =IO_ADDRESS(DAVINCI_ARM_INTC_BASE) + ldr \base, =davinci_intc_base + ldr \base, [\base] .endm .macro arch_ret_to_user, tmp1, tmp2 .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp +#if defined(CONFIG_AINTC) && defined(CONFIG_CP_INTC) + ldr \tmp, =davinci_intc_type + ldr \tmp, [\tmp] + cmp \tmp, #DAVINCI_INTC_TYPE_CP_INTC + beq 1001f +#endif +#if defined(CONFIG_AINTC) ldr \tmp, [\base, #0x14] - mov \tmp, \tmp, lsr #2 + movs \tmp, \tmp, lsr #2 sub \irqnr, \tmp, #1 - cmp \tmp, #0 + b 1002f +#endif +#if defined(CONFIG_CP_INTC) +1001: ldr \irqnr, [\base, #0x80] /* get irq number */ + and \irqnr, \irqnr, #0xff /* irq is in bits 0-9 */ + mov \tmp, \irqnr, lsr #3 + and \tmp, \tmp, #0xfc + add \tmp, \tmp, #0x280 /* get the register offset */ + ldr \irqstat, [\base, \tmp] /* get the intc status */ + cmp \irqstat, #0x0 +#endif +1002: .endm .macro irq_prio_table diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index efe3281364e..ae074556831 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -17,6 +17,7 @@ #include <asm-generic/gpio.h> #include <mach/irqs.h> +#include <mach/common.h> #define DAVINCI_GPIO_BASE 0x01C67000 @@ -67,15 +68,16 @@ static inline struct gpio_controller *__iomem __gpio_to_controller(unsigned gpio) { void *__iomem ptr; + void __iomem *base = davinci_soc_info.gpio_base; if (gpio < 32 * 1) - ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10); + ptr = base + 0x10; else if (gpio < 32 * 2) - ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38); + ptr = base + 0x38; else if (gpio < 32 * 3) - ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60); + ptr = base + 0x60; else if (gpio < 32 * 4) - ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x88); + ptr = base + 0x88; else ptr = NULL; return ptr; @@ -142,13 +144,13 @@ static inline int gpio_to_irq(unsigned gpio) { if (gpio >= DAVINCI_N_GPIO) return -EINVAL; - return DAVINCI_N_AINTC_IRQ + gpio; + return davinci_soc_info.intc_irq_num + gpio; } static inline int irq_to_gpio(unsigned irq) { /* caller guarantees gpio_to_irq() succeeded */ - return irq - DAVINCI_N_AINTC_IRQ; + return irq - davinci_soc_info.intc_irq_num; } #endif /* __DAVINCI_GPIO_H */ diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h index 18066074c99..bc5d6aaa69a 100644 --- a/arch/arm/mach-davinci/include/mach/irqs.h +++ b/arch/arm/mach-davinci/include/mach/irqs.h @@ -30,6 +30,9 @@ /* Base address */ #define DAVINCI_ARM_INTC_BASE 0x01C48000 +#define DAVINCI_INTC_TYPE_AINTC 0 +#define DAVINCI_INTC_TYPE_CP_INTC 1 + /* Interrupt lines */ #define IRQ_VDINT0 0 #define IRQ_VDINT1 1 diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h index 86c25c7f3ce..c712c7cdf38 100644 --- a/arch/arm/mach-davinci/include/mach/memory.h +++ b/arch/arm/mach-davinci/include/mach/memory.h @@ -21,7 +21,6 @@ * Definitions **************************************************************************/ #define DAVINCI_DDR_BASE 0x80000000 -#define DAVINCI_IRAM_BASE 0x00008000 /* ARM Internal RAM */ #define PHYS_OFFSET DAVINCI_DDR_BASE diff --git a/arch/arm/mach-davinci/include/mach/mmc.h b/arch/arm/mach-davinci/include/mach/mmc.h new file mode 100644 index 00000000000..5a85e24f367 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/mmc.h @@ -0,0 +1,33 @@ +/* + * Board-specific MMC configuration + */ + +#ifndef _DAVINCI_MMC_H +#define _DAVINCI_MMC_H + +#include <linux/types.h> +#include <linux/mmc/host.h> + +struct davinci_mmc_config { + /* get_cd()/get_wp() may sleep */ + int (*get_cd)(int module); + int (*get_ro)(int module); + /* wires == 0 is equivalent to wires == 4 (4-bit parallel) */ + u8 wires; + + u32 max_freq; + + /* any additional host capabilities: OR'd in to mmc->f_caps */ + u32 caps; + + /* Version of the MMC/SD controller */ + u8 version; +}; +void davinci_setup_mmc(int module, struct davinci_mmc_config *config); + +enum { + MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */ + MMC_CTLR_VERSION_2, /* DA830 */ +}; + +#endif diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index bae22cb3e27..27378458542 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h @@ -19,16 +19,6 @@ #ifndef __INC_MACH_MUX_H #define __INC_MACH_MUX_H -/* System module registers */ -#define PINMUX0 0x00 -#define PINMUX1 0x04 -/* dm355 only */ -#define PINMUX2 0x08 -#define PINMUX3 0x0c -#define PINMUX4 0x10 -#define INTMUX 0x18 -#define EVTMUX 0x1c - struct mux_config { const char *name; const char *mux_reg_name; @@ -168,15 +158,9 @@ enum davinci_dm355_index { #ifdef CONFIG_DAVINCI_MUX /* setup pin muxing */ -extern void davinci_mux_init(void); -extern int davinci_mux_register(const struct mux_config *pins, - unsigned long size); extern int davinci_cfg_reg(unsigned long reg_cfg); #else /* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */ -static inline void davinci_mux_init(void) {} -static inline int davinci_mux_register(const struct mux_config *pins, - unsigned long size) { return 0; } static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } #endif diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index 55a90d419fa..ab8a2586d1c 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -27,6 +27,8 @@ #ifndef __ASM_ARCH_PSC_H #define __ASM_ARCH_PSC_H +#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000 + /* Power and Sleep Controller (PSC) Domains */ #define DAVINCI_GPSC_ARMDOMAIN 0 #define DAVINCI_GPSC_DSPDOMAIN 1 @@ -116,8 +118,8 @@ #define DM646X_LPSC_TIMER1 35 #define DM646X_LPSC_ARM_INTC 45 -extern int davinci_psc_is_clk_active(unsigned int id); -extern void davinci_psc_config(unsigned int domain, unsigned int id, - char enable); +extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); +extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, + unsigned int id, char enable); #endif /* __ASM_ARCH_PSC_H */ diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h index 632847d74a1..794fa5cf93c 100644 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ b/arch/arm/mach-davinci/include/mach/serial.h @@ -18,8 +18,6 @@ #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) -#define DM355_UART2_BASE (IO_PHYS + 0x206000) - /* DaVinci UART register offsets */ #define UART_DAVINCI_PWREMU 0x0c #define UART_DM646X_SCR 0x10 @@ -30,6 +28,6 @@ struct davinci_uart_config { unsigned int enabled_uarts; }; -extern void davinci_serial_init(struct davinci_uart_config *); +extern int davinci_serial_init(struct davinci_uart_config *); #endif /* __ASM_ARCH_SERIAL_H */ diff --git a/arch/arm/mach-davinci/include/mach/sram.h b/arch/arm/mach-davinci/include/mach/sram.h new file mode 100644 index 00000000000..111f7cc71e0 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/sram.h @@ -0,0 +1,27 @@ +/* + * mach/sram.h - DaVinci simple SRAM allocator + * + * Copyright (C) 2009 David Brownell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __MACH_SRAM_H +#define __MACH_SRAM_H + +/* ARBITRARY: SRAM allocations are multiples of this 2^N size */ +#define SRAM_GRANULARITY 512 + +/* + * SRAM allocations return a CPU virtual address, or NULL on error. + * If a DMA address is requested and the SRAM supports DMA, its + * mapped address is also returned. + * + * Errors include SRAM memory not being available, and requesting + * DMA mapped SRAM on systems which don't allow that. + */ +extern void *sram_alloc(size_t len, dma_addr_t *dma); +extern void sram_free(void *addr, size_t len); + +#endif /* __MACH_SRAM_H */ diff --git a/arch/arm/mach-davinci/include/mach/time.h b/arch/arm/mach-davinci/include/mach/time.h new file mode 100644 index 00000000000..1c971d8d8ba --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/time.h @@ -0,0 +1,35 @@ +/* + * Local header file for DaVinci time code. + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H +#define __ARCH_ARM_MACH_DAVINCI_TIME_H + +#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400) +#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800) +#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00) + +enum { + T0_BOT, + T0_TOP, + T1_BOT, + T1_TOP, + NUM_TIMERS +}; + +#define IS_TIMER1(id) (id & 0x2) +#define IS_TIMER0(id) (!IS_TIMER1(id)) +#define IS_TIMER_TOP(id) ((id & 0x1)) +#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id)) + +#define ID_TO_TIMER(id) (IS_TIMER1(id) != 0) + +extern struct davinci_timer_instance davinci_timer_instance[]; + +#endif /* __ARCH_ARM_MACH_DAVINCI_TIME_H */ diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 8c165def37b..1e27475f9a2 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -13,11 +13,24 @@ #include <linux/serial_reg.h> #include <mach/serial.h> +#include <asm/mach-types.h> + +extern unsigned int __machine_arch_type; + +static u32 *uart; + +static u32 *get_uart_base(void) +{ + /* Add logic here for new platforms, using __macine_arch_type */ + return (u32 *)DAVINCI_UART0_BASE; +} + /* PORT_16C550A, in polled non-fifo mode */ static void putc(char c) { - volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; + if (!uart) + uart = get_uart_base(); while (!(uart[UART_LSR] & UART_LSR_THRE)) barrier(); @@ -26,7 +39,9 @@ static void putc(char c) static inline void flush(void) { - volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; + if (!uart) + uart = get_uart_base(); + while (!(uart[UART_LSR] & UART_LSR_THRE)) barrier(); } diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c index a548abb513e..49912b48b1b 100644 --- a/arch/arm/mach-davinci/io.c +++ b/arch/arm/mach-davinci/io.c @@ -9,47 +9,9 @@ */ #include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> #include <linux/io.h> #include <asm/tlb.h> -#include <asm/memory.h> - -#include <asm/mach/map.h> -#include <mach/clock.h> - -extern void davinci_check_revision(void); - -/* - * The machine specific code may provide the extra mapping besides the - * default mapping provided here. - */ -static struct map_desc davinci_io_desc[] __initdata = { - { - .virtual = IO_VIRT, - .pfn = __phys_to_pfn(IO_PHYS), - .length = IO_SIZE, - .type = MT_DEVICE - }, -}; - -void __init davinci_map_common_io(void) -{ - iotable_init(davinci_io_desc, ARRAY_SIZE(davinci_io_desc)); - - /* Normally devicemaps_init() would flush caches and tlb after - * mdesc->map_io(), but we must also do it here because of the CPU - * revision check below. - */ - local_flush_tlb_all(); - flush_cache_all(); - - /* We want to check CPU revision early for cpu_is_xxxx() macros. - * IO space mapping must be initialized before we can do that. - */ - davinci_check_revision(); -} #define BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) #define XLATE(p, pst, vst) ((void __iomem *)((p) - (pst) + (vst))) diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index 5a324c90e29..af92ffee847 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c @@ -26,6 +26,7 @@ #include <mach/hardware.h> #include <mach/cputype.h> +#include <mach/common.h> #include <asm/mach/irq.h> #define IRQ_BIT(irq) ((irq) & 0x1f) @@ -41,18 +42,14 @@ #define IRQ_INTPRI0_REG_OFFSET 0x0030 #define IRQ_INTPRI7_REG_OFFSET 0x004C -const u8 *davinci_def_priorities; - -#define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE) - static inline unsigned int davinci_irq_readl(int offset) { - return __raw_readl(INTC_BASE + offset); + return __raw_readl(davinci_intc_base + offset); } static inline void davinci_irq_writel(unsigned long value, int offset) { - __raw_writel(value, INTC_BASE + offset); + __raw_writel(value, davinci_intc_base + offset); } /* Disable interrupt */ @@ -113,217 +110,11 @@ static struct irq_chip davinci_irq_chip_0 = { .unmask = davinci_unmask_irq, }; -/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ -static const u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = { - [IRQ_VDINT0] = 2, - [IRQ_VDINT1] = 6, - [IRQ_VDINT2] = 6, - [IRQ_HISTINT] = 6, - [IRQ_H3AINT] = 6, - [IRQ_PRVUINT] = 6, - [IRQ_RSZINT] = 6, - [7] = 7, - [IRQ_VENCINT] = 6, - [IRQ_ASQINT] = 6, - [IRQ_IMXINT] = 6, - [IRQ_VLCDINT] = 6, - [IRQ_USBINT] = 4, - [IRQ_EMACINT] = 4, - [14] = 7, - [15] = 7, - [IRQ_CCINT0] = 5, /* dma */ - [IRQ_CCERRINT] = 5, /* dma */ - [IRQ_TCERRINT0] = 5, /* dma */ - [IRQ_TCERRINT] = 5, /* dma */ - [IRQ_PSCIN] = 7, - [21] = 7, - [IRQ_IDE] = 4, - [23] = 7, - [IRQ_MBXINT] = 7, - [IRQ_MBRINT] = 7, - [IRQ_MMCINT] = 7, - [IRQ_SDIOINT] = 7, - [28] = 7, - [IRQ_DDRINT] = 7, - [IRQ_AEMIFINT] = 7, - [IRQ_VLQINT] = 4, - [IRQ_TINT0_TINT12] = 2, /* clockevent */ - [IRQ_TINT0_TINT34] = 2, /* clocksource */ - [IRQ_TINT1_TINT12] = 7, /* DSP timer */ - [IRQ_TINT1_TINT34] = 7, /* system tick */ - [IRQ_PWMINT0] = 7, - [IRQ_PWMINT1] = 7, - [IRQ_PWMINT2] = 7, - [IRQ_I2C] = 3, - [IRQ_UARTINT0] = 3, - [IRQ_UARTINT1] = 3, - [IRQ_UARTINT2] = 3, - [IRQ_SPINT0] = 3, - [IRQ_SPINT1] = 3, - [45] = 7, - [IRQ_DSP2ARM0] = 4, - [IRQ_DSP2ARM1] = 4, - [IRQ_GPIO0] = 7, - [IRQ_GPIO1] = 7, - [IRQ_GPIO2] = 7, - [IRQ_GPIO3] = 7, - [IRQ_GPIO4] = 7, - [IRQ_GPIO5] = 7, - [IRQ_GPIO6] = 7, - [IRQ_GPIO7] = 7, - [IRQ_GPIOBNK0] = 7, - [IRQ_GPIOBNK1] = 7, - [IRQ_GPIOBNK2] = 7, - [IRQ_GPIOBNK3] = 7, - [IRQ_GPIOBNK4] = 7, - [IRQ_COMMTX] = 7, - [IRQ_COMMRX] = 7, - [IRQ_EMUINT] = 7, -}; - -static const u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { - [IRQ_DM646X_VP_VERTINT0] = 7, - [IRQ_DM646X_VP_VERTINT1] = 7, - [IRQ_DM646X_VP_VERTINT2] = 7, - [IRQ_DM646X_VP_VERTINT3] = 7, - [IRQ_DM646X_VP_ERRINT] = 7, - [IRQ_DM646X_RESERVED_1] = 7, - [IRQ_DM646X_RESERVED_2] = 7, - [IRQ_DM646X_WDINT] = 7, - [IRQ_DM646X_CRGENINT0] = 7, - [IRQ_DM646X_CRGENINT1] = 7, - [IRQ_DM646X_TSIFINT0] = 7, - [IRQ_DM646X_TSIFINT1] = 7, - [IRQ_DM646X_VDCEINT] = 7, - [IRQ_DM646X_USBINT] = 7, - [IRQ_DM646X_USBDMAINT] = 7, - [IRQ_DM646X_PCIINT] = 7, - [IRQ_CCINT0] = 7, /* dma */ - [IRQ_CCERRINT] = 7, /* dma */ - [IRQ_TCERRINT0] = 7, /* dma */ - [IRQ_TCERRINT] = 7, /* dma */ - [IRQ_DM646X_TCERRINT2] = 7, - [IRQ_DM646X_TCERRINT3] = 7, - [IRQ_DM646X_IDE] = 7, - [IRQ_DM646X_HPIINT] = 7, - [IRQ_DM646X_EMACRXTHINT] = 7, - [IRQ_DM646X_EMACRXINT] = 7, - [IRQ_DM646X_EMACTXINT] = 7, - [IRQ_DM646X_EMACMISCINT] = 7, - [IRQ_DM646X_MCASP0TXINT] = 7, - [IRQ_DM646X_MCASP0RXINT] = 7, - [IRQ_AEMIFINT] = 7, - [IRQ_DM646X_RESERVED_3] = 7, - [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */ - [IRQ_TINT0_TINT34] = 7, /* clocksource */ - [IRQ_TINT1_TINT12] = 7, /* DSP timer */ - [IRQ_TINT1_TINT34] = 7, /* system tick */ - [IRQ_PWMINT0] = 7, - [IRQ_PWMINT1] = 7, - [IRQ_DM646X_VLQINT] = 7, - [IRQ_I2C] = 7, - [IRQ_UARTINT0] = 7, - [IRQ_UARTINT1] = 7, - [IRQ_DM646X_UARTINT2] = 7, - [IRQ_DM646X_SPINT0] = 7, - [IRQ_DM646X_SPINT1] = 7, - [IRQ_DM646X_DSP2ARMINT] = 7, - [IRQ_DM646X_RESERVED_4] = 7, - [IRQ_DM646X_PSCINT] = 7, - [IRQ_DM646X_GPIO0] = 7, - [IRQ_DM646X_GPIO1] = 7, - [IRQ_DM646X_GPIO2] = 7, - [IRQ_DM646X_GPIO3] = 7, - [IRQ_DM646X_GPIO4] = 7, - [IRQ_DM646X_GPIO5] = 7, - [IRQ_DM646X_GPIO6] = 7, - [IRQ_DM646X_GPIO7] = 7, - [IRQ_DM646X_GPIOBNK0] = 7, - [IRQ_DM646X_GPIOBNK1] = 7, - [IRQ_DM646X_GPIOBNK2] = 7, - [IRQ_DM646X_DDRINT] = 7, - [IRQ_DM646X_AEMIFINT] = 7, - [IRQ_COMMTX] = 7, - [IRQ_COMMRX] = 7, - [IRQ_EMUINT] = 7, -}; - -static const u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = { - [IRQ_DM355_CCDC_VDINT0] = 2, - [IRQ_DM355_CCDC_VDINT1] = 6, - [IRQ_DM355_CCDC_VDINT2] = 6, - [IRQ_DM355_IPIPE_HST] = 6, - [IRQ_DM355_H3AINT] = 6, - [IRQ_DM355_IPIPE_SDR] = 6, - [IRQ_DM355_IPIPEIFINT] = 6, - [IRQ_DM355_OSDINT] = 7, - [IRQ_DM355_VENCINT] = 6, - [IRQ_ASQINT] = 6, - [IRQ_IMXINT] = 6, - [IRQ_USBINT] = 4, - [IRQ_DM355_RTOINT] = 4, - [IRQ_DM355_UARTINT2] = 7, - [IRQ_DM355_TINT6] = 7, - [IRQ_CCINT0] = 5, /* dma */ - [IRQ_CCERRINT] = 5, /* dma */ - [IRQ_TCERRINT0] = 5, /* dma */ - [IRQ_TCERRINT] = 5, /* dma */ - [IRQ_DM355_SPINT2_1] = 7, - [IRQ_DM355_TINT7] = 4, - [IRQ_DM355_SDIOINT0] = 7, - [IRQ_MBXINT] = 7, - [IRQ_MBRINT] = 7, - [IRQ_MMCINT] = 7, - [IRQ_DM355_MMCINT1] = 7, - [IRQ_DM355_PWMINT3] = 7, - [IRQ_DDRINT] = 7, - [IRQ_AEMIFINT] = 7, - [IRQ_DM355_SDIOINT1] = 4, - [IRQ_TINT0_TINT12] = 2, /* clockevent */ - [IRQ_TINT0_TINT34] = 2, /* clocksource */ - [IRQ_TINT1_TINT12] = 7, /* DSP timer */ - [IRQ_TINT1_TINT34] = 7, /* system tick */ - [IRQ_PWMINT0] = 7, - [IRQ_PWMINT1] = 7, - [IRQ_PWMINT2] = 7, - [IRQ_I2C] = 3, - [IRQ_UARTINT0] = 3, - [IRQ_UARTINT1] = 3, - [IRQ_DM355_SPINT0_0] = 3, - [IRQ_DM355_SPINT0_1] = 3, - [IRQ_DM355_GPIO0] = 3, - [IRQ_DM355_GPIO1] = 7, - [IRQ_DM355_GPIO2] = 4, - [IRQ_DM355_GPIO3] = 4, - [IRQ_DM355_GPIO4] = 7, - [IRQ_DM355_GPIO5] = 7, - [IRQ_DM355_GPIO6] = 7, - [IRQ_DM355_GPIO7] = 7, - [IRQ_DM355_GPIO8] = 7, - [IRQ_DM355_GPIO9] = 7, - [IRQ_DM355_GPIOBNK0] = 7, - [IRQ_DM355_GPIOBNK1] = 7, - [IRQ_DM355_GPIOBNK2] = 7, - [IRQ_DM355_GPIOBNK3] = 7, - [IRQ_DM355_GPIOBNK4] = 7, - [IRQ_DM355_GPIOBNK5] = 7, - [IRQ_DM355_GPIOBNK6] = 7, - [IRQ_COMMTX] = 7, - [IRQ_COMMRX] = 7, - [IRQ_EMUINT] = 7, -}; - /* ARM Interrupt Controller Initialization */ void __init davinci_irq_init(void) { unsigned i; - - if (cpu_is_davinci_dm644x()) - davinci_def_priorities = dm644x_default_priorities; - else if (cpu_is_davinci_dm646x()) - davinci_def_priorities = dm646x_default_priorities; - else if (cpu_is_davinci_dm355()) - davinci_def_priorities = dm355_default_priorities; + const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios; /* Clear all interrupt requests */ davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c index bbba0b247a4..d310f579aa8 100644 --- a/arch/arm/mach-davinci/mux.c +++ b/arch/arm/mach-davinci/mux.c @@ -21,18 +21,7 @@ #include <mach/hardware.h> #include <mach/mux.h> - -static const struct mux_config *mux_table; -static unsigned long pin_table_sz; - -int __init davinci_mux_register(const struct mux_config *pins, - unsigned long size) -{ - mux_table = pins; - pin_table_sz = size; - - return 0; -} +#include <mach/common.h> /* * Sets the DAVINCI MUX register based on the table @@ -40,23 +29,24 @@ int __init davinci_mux_register(const struct mux_config *pins, int __init_or_module davinci_cfg_reg(const unsigned long index) { static DEFINE_SPINLOCK(mux_spin_lock); - void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); + struct davinci_soc_info *soc_info = &davinci_soc_info; + void __iomem *base = soc_info->pinmux_base; unsigned long flags; const struct mux_config *cfg; unsigned int reg_orig = 0, reg = 0; unsigned int mask, warn = 0; - if (!mux_table) + if (!soc_info->pinmux_pins) BUG(); - if (index >= pin_table_sz) { + if (index >= soc_info->pinmux_pins_num) { printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", - index, pin_table_sz); + index, soc_info->pinmux_pins_num); dump_stack(); return -ENODEV; } - cfg = &mux_table[index]; + cfg = &soc_info->pinmux_pins[index]; if (cfg->name == NULL) { printk(KERN_ERR "No entry for the specified index\n"); diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index 84171abf5f7..a78b657e916 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c @@ -28,8 +28,6 @@ #include <mach/psc.h> #include <mach/mux.h> -#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000 - /* PSC register offsets */ #define EPCPR 0x070 #define PTCMD 0x120 @@ -42,22 +40,42 @@ #define MDSTAT_STATE_MASK 0x1f /* Return nonzero iff the domain's clock is active */ -int __init davinci_psc_is_clk_active(unsigned int id) +int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) { - void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE); - u32 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); + void __iomem *psc_base; + u32 mdstat; + struct davinci_soc_info *soc_info = &davinci_soc_info; + + if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { + pr_warning("PSC: Bad psc data: 0x%x[%d]\n", + (int)soc_info->psc_bases, ctlr); + return 0; + } + + psc_base = soc_info->psc_bases[ctlr]; + mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); /* if clocked, state can be "Enable" or "SyncReset" */ return mdstat & BIT(12); } /* Enable or disable a PSC domain */ -void davinci_psc_config(unsigned int domain, unsigned int id, char enable) +void davinci_psc_config(unsigned int domain, unsigned int ctlr, + unsigned int id, char enable) { u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl; - void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE); + void __iomem *psc_base; + struct davinci_soc_info *soc_info = &davinci_soc_info; u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */ + if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { + pr_warning("PSC: Bad psc data: 0x%x[%d]\n", + (int)soc_info->psc_bases, ctlr); + return; + } + + psc_base = soc_info->psc_bases[ctlr]; + mdctl = __raw_readl(psc_base + MDCTL + 4 * id); mdctl &= ~MDSTAT_STATE_MASK; mdctl |= next_state; diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c index 69507579652..c530c7333d0 100644 --- a/arch/arm/mach-davinci/serial.c +++ b/arch/arm/mach-davinci/serial.c @@ -33,6 +33,8 @@ #include <mach/serial.h> #include <mach/irqs.h> #include <mach/cputype.h> +#include <mach/common.h> + #include "clock.h" static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, @@ -49,44 +51,6 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, __raw_writel(value, IO_ADDRESS(p->mapbase) + offset); } -static struct plat_serial8250_port serial_platform_data[] = { - { - .mapbase = DAVINCI_UART0_BASE, - .irq = IRQ_UARTINT0, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .mapbase = DAVINCI_UART1_BASE, - .irq = IRQ_UARTINT1, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .mapbase = DAVINCI_UART2_BASE, - .irq = IRQ_UARTINT2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_IOREMAP, - .iotype = UPIO_MEM, - .regshift = 2, - }, - { - .flags = 0 - }, -}; - -static struct platform_device serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = serial_platform_data, - }, -}; - static void __init davinci_serial_reset(struct plat_serial8250_port *p) { unsigned int pwremu = 0; @@ -106,35 +70,22 @@ static void __init davinci_serial_reset(struct plat_serial8250_port *p) UART_DM646X_SCR_TX_WATERMARK); } -void __init davinci_serial_init(struct davinci_uart_config *info) +int __init davinci_serial_init(struct davinci_uart_config *info) { int i; char name[16]; struct clk *uart_clk; - struct device *dev = &serial_device.dev; + struct davinci_soc_info *soc_info = &davinci_soc_info; + struct device *dev = &soc_info->serial_dev->dev; + struct plat_serial8250_port *p = dev->platform_data; /* * Make sure the serial ports are muxed on at this point. - * You have to mux them off in device drivers later on - * if not needed. + * You have to mux them off in device drivers later on if not needed. */ - for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++) { - struct plat_serial8250_port *p = serial_platform_data + i; - - if (!(info->enabled_uarts & (1 << i))) { - p->flags = 0; + for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++, p++) { + if (!(info->enabled_uarts & (1 << i))) continue; - } - - if (cpu_is_davinci_dm646x()) - p->iotype = UPIO_MEM32; - - if (cpu_is_davinci_dm355()) { - if (i == 2) { - p->mapbase = (unsigned long)DM355_UART2_BASE; - p->irq = IRQ_DM355_UARTINT2; - } - } sprintf(name, "uart%d", i); uart_clk = clk_get(dev, name); @@ -147,11 +98,6 @@ void __init davinci_serial_init(struct davinci_uart_config *info) davinci_serial_reset(p); } } -} -static int __init davinci_init(void) -{ - return platform_device_register(&serial_device); + return platform_device_register(soc_info->serial_dev); } - -arch_initcall(davinci_init); diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c new file mode 100644 index 00000000000..db54b2a66b4 --- /dev/null +++ b/arch/arm/mach-davinci/sram.c @@ -0,0 +1,74 @@ +/* + * mach-davinci/sram.c - DaVinci simple SRAM allocator + * + * Copyright (C) 2009 David Brownell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/genalloc.h> + +#include <mach/common.h> +#include <mach/memory.h> +#include <mach/sram.h> + + +static struct gen_pool *sram_pool; + +void *sram_alloc(size_t len, dma_addr_t *dma) +{ + unsigned long vaddr; + dma_addr_t dma_base = davinci_soc_info.sram_dma; + + if (dma) + *dma = 0; + if (!sram_pool || (dma && !dma_base)) + return NULL; + + vaddr = gen_pool_alloc(sram_pool, len); + if (!vaddr) + return NULL; + + if (dma) + *dma = dma_base + (vaddr - SRAM_VIRT); + return (void *)vaddr; + +} +EXPORT_SYMBOL(sram_alloc); + +void sram_free(void *addr, size_t len) +{ + gen_pool_free(sram_pool, (unsigned long) addr, len); +} +EXPORT_SYMBOL(sram_free); + + +/* + * REVISIT This supports CPU and DMA access to/from SRAM, but it + * doesn't (yet?) support some other notable uses of SRAM: as TCM + * for data and/or instructions; and holding code needed to enter + * and exit suspend states (while DRAM can't be used). + */ +static int __init sram_init(void) +{ + unsigned len = davinci_soc_info.sram_len; + int status = 0; + + if (len) { + len = min(len, SRAM_SIZE); + sram_pool = gen_pool_create(ilog2(SRAM_GRANULARITY), -1); + if (!sram_pool) + status = -ENOMEM; + } + if (sram_pool) + status = gen_pool_add(sram_pool, SRAM_VIRT, len, -1); + WARN_ON(status < 0); + return status; +} +core_initcall(sram_init); + diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 494e01bff5c..0884ca57bfb 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c @@ -19,6 +19,7 @@ #include <linux/clk.h> #include <linux/err.h> #include <linux/device.h> +#include <linux/platform_device.h> #include <mach/hardware.h> #include <asm/system.h> @@ -28,52 +29,41 @@ #include <asm/errno.h> #include <mach/io.h> #include <mach/cputype.h> +#include <mach/time.h> #include "clock.h" static struct clock_event_device clockevent_davinci; static unsigned int davinci_clock_tick_rate; -#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400) -#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800) -#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00) - -enum { - T0_BOT = 0, T0_TOP, T1_BOT, T1_TOP, NUM_TIMERS, -}; - -#define IS_TIMER1(id) (id & 0x2) -#define IS_TIMER0(id) (!IS_TIMER1(id)) -#define IS_TIMER_TOP(id) ((id & 0x1)) -#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id)) - -static int timer_irqs[NUM_TIMERS] = { - IRQ_TINT0_TINT12, - IRQ_TINT0_TINT34, - IRQ_TINT1_TINT12, - IRQ_TINT1_TINT34, -}; - /* * This driver configures the 2 64-bit count-up timers as 4 independent * 32-bit count-up timers used as follows: - * - * T0_BOT: Timer 0, bottom: clockevent source for hrtimers - * T0_TOP: Timer 0, top : clocksource for generic timekeeping - * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) - * T1_TOP: Timer 1, top : <unused> */ -#define TID_CLOCKEVENT T0_BOT -#define TID_CLOCKSOURCE T0_TOP + +enum { + TID_CLOCKEVENT, + TID_CLOCKSOURCE, +}; /* Timer register offsets */ -#define PID12 0x0 -#define TIM12 0x10 -#define TIM34 0x14 -#define PRD12 0x18 -#define PRD34 0x1c -#define TCR 0x20 -#define TGCR 0x24 -#define WDTCR 0x28 +#define PID12 0x0 +#define TIM12 0x10 +#define TIM34 0x14 +#define PRD12 0x18 +#define PRD34 0x1c +#define TCR 0x20 +#define TGCR 0x24 +#define WDTCR 0x28 + +/* Offsets of the 8 compare registers */ +#define CMP12_0 0x60 +#define CMP12_1 0x64 +#define CMP12_2 0x68 +#define CMP12_3 0x6c +#define CMP12_4 0x70 +#define CMP12_5 0x74 +#define CMP12_6 0x78 +#define CMP12_7 0x7c /* Timer register bitfields */ #define TCR_ENAMODE_DISABLE 0x0 @@ -105,6 +95,7 @@ struct timer_s { unsigned int id; unsigned long period; unsigned long opts; + unsigned long flags; void __iomem *base; unsigned long tim_off; unsigned long prd_off; @@ -114,30 +105,58 @@ struct timer_s { static struct timer_s timers[]; /* values for 'opts' field of struct timer_s */ -#define TIMER_OPTS_DISABLED 0x00 -#define TIMER_OPTS_ONESHOT 0x01 -#define TIMER_OPTS_PERIODIC 0x02 +#define TIMER_OPTS_DISABLED 0x01 +#define TIMER_OPTS_ONESHOT 0x02 +#define TIMER_OPTS_PERIODIC 0x04 +#define TIMER_OPTS_STATE_MASK 0x07 + +#define TIMER_OPTS_USE_COMPARE 0x80000000 +#define USING_COMPARE(t) ((t)->opts & TIMER_OPTS_USE_COMPARE) + +static char *id_to_name[] = { + [T0_BOT] = "timer0_0", + [T0_TOP] = "timer0_1", + [T1_BOT] = "timer1_0", + [T1_TOP] = "timer1_1", +}; static int timer32_config(struct timer_s *t) { - u32 tcr = __raw_readl(t->base + TCR); - - /* disable timer */ - tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift); - __raw_writel(tcr, t->base + TCR); - - /* reset counter to zero, set new period */ - __raw_writel(0, t->base + t->tim_off); - __raw_writel(t->period, t->base + t->prd_off); - - /* Set enable mode */ - if (t->opts & TIMER_OPTS_ONESHOT) { - tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift; - } else if (t->opts & TIMER_OPTS_PERIODIC) { - tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift; + u32 tcr; + struct davinci_soc_info *soc_info = &davinci_soc_info; + + if (USING_COMPARE(t)) { + struct davinci_timer_instance *dtip = + soc_info->timer_info->timers; + int event_timer = ID_TO_TIMER(timers[TID_CLOCKEVENT].id); + + /* + * Next interrupt should be the current time reg value plus + * the new period (using 32-bit unsigned addition/wrapping + * to 0 on overflow). This assumes that the clocksource + * is setup to count to 2^32-1 before wrapping around to 0. + */ + __raw_writel(__raw_readl(t->base + t->tim_off) + t->period, + t->base + dtip[event_timer].cmp_off); + } else { + tcr = __raw_readl(t->base + TCR); + + /* disable timer */ + tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift); + __raw_writel(tcr, t->base + TCR); + + /* reset counter to zero, set new period */ + __raw_writel(0, t->base + t->tim_off); + __raw_writel(t->period, t->base + t->prd_off); + + /* Set enable mode */ + if (t->opts & TIMER_OPTS_ONESHOT) + tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift; + else if (t->opts & TIMER_OPTS_PERIODIC) + tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift; + + __raw_writel(tcr, t->base + TCR); } - - __raw_writel(tcr, t->base + TCR); return 0; } @@ -182,13 +201,14 @@ static struct timer_s timers[] = { static void __init timer_init(void) { - u32 phys_bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE}; + struct davinci_soc_info *soc_info = &davinci_soc_info; + struct davinci_timer_instance *dtip = soc_info->timer_info->timers; int i; /* Global init of each 64-bit timer as a whole */ for(i=0; i<2; i++) { u32 tgcr; - void __iomem *base = IO_ADDRESS(phys_bases[i]); + void __iomem *base = dtip[i].base; /* Disabled, Internal clock source */ __raw_writel(0, base + TCR); @@ -214,33 +234,33 @@ static void __init timer_init(void) /* Init of each timer as a 32-bit timer */ for (i=0; i< ARRAY_SIZE(timers); i++) { struct timer_s *t = &timers[i]; - u32 phys_base; - - if (t->name) { - t->id = i; - phys_base = (IS_TIMER1(t->id) ? - DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE); - t->base = IO_ADDRESS(phys_base); - - if (IS_TIMER_BOT(t->id)) { - t->enamode_shift = 6; - t->tim_off = TIM12; - t->prd_off = PRD12; - } else { - t->enamode_shift = 22; - t->tim_off = TIM34; - t->prd_off = PRD34; - } - - /* Register interrupt */ - t->irqaction.name = t->name; - t->irqaction.dev_id = (void *)t; - if (t->irqaction.handler != NULL) { - setup_irq(timer_irqs[t->id], &t->irqaction); - } - - timer32_config(&timers[i]); + int timer = ID_TO_TIMER(t->id); + u32 irq; + + t->base = dtip[timer].base; + + if (IS_TIMER_BOT(t->id)) { + t->enamode_shift = 6; + t->tim_off = TIM12; + t->prd_off = PRD12; + irq = dtip[timer].bottom_irq; + } else { + t->enamode_shift = 22; + t->tim_off = TIM34; + t->prd_off = PRD34; + irq = dtip[timer].top_irq; + } + + /* Register interrupt */ + t->irqaction.name = t->name; + t->irqaction.dev_id = (void *)t; + + if (t->irqaction.handler != NULL) { + irq = USING_COMPARE(t) ? dtip[i].cmp_irq : irq; + setup_irq(irq, &t->irqaction); } + + timer32_config(&timers[i]); } } @@ -255,7 +275,6 @@ static cycle_t read_cycles(struct clocksource *cs) } static struct clocksource clocksource_davinci = { - .name = "timer0_1", .rating = 300, .read = read_cycles, .mask = CLOCKSOURCE_MASK(32), @@ -284,15 +303,18 @@ static void davinci_set_mode(enum clock_event_mode mode, switch (mode) { case CLOCK_EVT_MODE_PERIODIC: t->period = davinci_clock_tick_rate / (HZ); - t->opts = TIMER_OPTS_PERIODIC; + t->opts &= ~TIMER_OPTS_STATE_MASK; + t->opts |= TIMER_OPTS_PERIODIC; timer32_config(t); break; case CLOCK_EVT_MODE_ONESHOT: - t->opts = TIMER_OPTS_ONESHOT; + t->opts &= ~TIMER_OPTS_STATE_MASK; + t->opts |= TIMER_OPTS_ONESHOT; break; case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: - t->opts = TIMER_OPTS_DISABLED; + t->opts &= ~TIMER_OPTS_STATE_MASK; + t->opts |= TIMER_OPTS_DISABLED; break; case CLOCK_EVT_MODE_RESUME: break; @@ -300,7 +322,6 @@ static void davinci_set_mode(enum clock_event_mode mode, } static struct clock_event_device clockevent_davinci = { - .name = "timer0_0", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .shift = 32, .set_next_event = davinci_set_next_event, @@ -311,10 +332,42 @@ static struct clock_event_device clockevent_davinci = { static void __init davinci_timer_init(void) { struct clk *timer_clk; - + struct davinci_soc_info *soc_info = &davinci_soc_info; + unsigned int clockevent_id; + unsigned int clocksource_id; static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n"; + clockevent_id = soc_info->timer_info->clockevent_id; + clocksource_id = soc_info->timer_info->clocksource_id; + + timers[TID_CLOCKEVENT].id = clockevent_id; + timers[TID_CLOCKSOURCE].id = clocksource_id; + + /* + * If using same timer for both clock events & clocksource, + * a compare register must be used to generate an event interrupt. + * This is equivalent to a oneshot timer only (not periodic). + */ + if (clockevent_id == clocksource_id) { + struct davinci_timer_instance *dtip = + soc_info->timer_info->timers; + int event_timer = ID_TO_TIMER(clockevent_id); + + /* Only bottom timers can use compare regs */ + if (IS_TIMER_TOP(clockevent_id)) + pr_warning("davinci_timer_init: Invalid use" + " of system timers. Results unpredictable.\n"); + else if ((dtip[event_timer].cmp_off == 0) + || (dtip[event_timer].cmp_irq == 0)) + pr_warning("davinci_timer_init: Invalid timer instance" + " setup. Results unpredictable.\n"); + else { + timers[TID_CLOCKEVENT].opts |= TIMER_OPTS_USE_COMPARE; + clockevent_davinci.features = CLOCK_EVT_FEAT_ONESHOT; + } + } + /* init timer hw */ timer_init(); @@ -325,6 +378,7 @@ static void __init davinci_timer_init(void) davinci_clock_tick_rate = clk_get_rate(timer_clk); /* setup clocksource */ + clocksource_davinci.name = id_to_name[clocksource_id]; clocksource_davinci.mult = clocksource_khz2mult(davinci_clock_tick_rate/1000, clocksource_davinci.shift); @@ -332,12 +386,12 @@ static void __init davinci_timer_init(void) printk(err, clocksource_davinci.name); /* setup clockevent */ + clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id]; clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC, clockevent_davinci.shift); clockevent_davinci.max_delta_ns = clockevent_delta2ns(0xfffffffe, &clockevent_davinci); - clockevent_davinci.min_delta_ns = - clockevent_delta2ns(1, &clockevent_davinci); + clockevent_davinci.min_delta_ns = 50000; /* 50 usec */ clockevent_davinci.cpumask = cpumask_of(0); clockevents_register_device(&clockevent_davinci); @@ -349,15 +403,14 @@ struct sys_timer davinci_timer = { /* reset board using watchdog timer */ -void davinci_watchdog_reset(void) { +void davinci_watchdog_reset(void) +{ u32 tgcr, wdtcr; - void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE); - struct device dev; + struct davinci_soc_info *soc_info = &davinci_soc_info; + void __iomem *base = soc_info->wdt_base; struct clk *wd_clk; - char *name = "watchdog"; - dev_set_name(&dev, name); - wd_clk = clk_get(&dev, NULL); + wd_clk = clk_get(&davinci_wdt_device.dev, NULL); if (WARN_ON(IS_ERR(wd_clk))) return; clk_enable(wd_clk); diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index ae24486f858..c535e8805a3 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -450,10 +450,19 @@ static struct amba_device uart3_device = { }; +static struct resource ep93xx_rtc_resource[] = { + { + .start = EP93XX_RTC_PHYS_BASE, + .end = EP93XX_RTC_PHYS_BASE + 0x10c - 1, + .flags = IORESOURCE_MEM, + }, +}; + static struct platform_device ep93xx_rtc_device = { - .name = "ep93xx-rtc", - .id = -1, - .num_resources = 0, + .name = "ep93xx-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(ep93xx_rtc_resource), + .resource = ep93xx_rtc_resource, }; diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h index 1732de7629a..420f71b8512 100644 --- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h @@ -147,6 +147,7 @@ #define EP93XX_PWM_BASE (EP93XX_APB_VIRT_BASE + 0x00110000) #define EP93XX_RTC_BASE (EP93XX_APB_VIRT_BASE + 0x00120000) +#define EP93XX_RTC_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x00120000) #define EP93XX_SYSCON_BASE (EP93XX_APB_VIRT_BASE + 0x00130000) #define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x)) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig deleted file mode 100644 index cddd194ac6e..00000000000 --- a/arch/arm/mach-imx/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -menu "IMX Implementations" - depends on ARCH_IMX - -config ARCH_MX1ADS - bool "mx1ads" - depends on ARCH_IMX - select ISA - help - Say Y here if you are using the Motorola MX1ADS board - -endmenu diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile deleted file mode 100644 index b047c7e795a..00000000000 --- a/arch/arm/mach-imx/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the linux kernel. -# - -# Object file lists. - -obj-y += irq.o time.o dma.o generic.o clock.o - -obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o - -# Specific board support -obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o - -# Support for blinky lights -led-y := leds.o - -obj-$(CONFIG_LEDS) += $(led-y) -led-$(CONFIG_ARCH_MX1ADS) += leds-mx1ads.o diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot deleted file mode 100644 index fd72ce5b808..00000000000 --- a/arch/arm/mach-imx/Makefile.boot +++ /dev/null @@ -1,2 +0,0 @@ - zreladdr-$(CONFIG_ARCH_MX1ADS) := 0x08008000 - diff --git a/arch/arm/mach-imx/clock.c b/arch/arm/mach-imx/clock.c deleted file mode 100644 index cf332aeb942..00000000000 --- a/arch/arm/mach-imx/clock.c +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <linux/kernel.h> -#include <linux/device.h> -#include <linux/list.h> -#include <linux/math64.h> -#include <linux/err.h> -#include <linux/io.h> - -#include <mach/hardware.h> - -/* - * Very simple approach: We can't disable clocks, so we do - * not need refcounting - */ - -struct clk { - struct list_head node; - const char *name; - unsigned long (*get_rate)(void); -}; - -/* - * get the system pll clock in Hz - * - * mfi + mfn / (mfd +1) - * f = 2 * f_ref * -------------------- - * pd + 1 - */ -static unsigned long imx_decode_pll(unsigned int pll, u32 f_ref) -{ - unsigned long long ll; - unsigned long quot; - - u32 mfi = (pll >> 10) & 0xf; - u32 mfn = pll & 0x3ff; - u32 mfd = (pll >> 16) & 0x3ff; - u32 pd = (pll >> 26) & 0xf; - - mfi = mfi <= 5 ? 5 : mfi; - - ll = 2 * (unsigned long long)f_ref * - ((mfi << 16) + (mfn << 16) / (mfd + 1)); - quot = (pd + 1) * (1 << 16); - ll += quot / 2; - do_div(ll, quot); - return (unsigned long)ll; -} - -static unsigned long imx_get_system_clk(void) -{ - u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512); - - return imx_decode_pll(SPCTL0, f_ref); -} - -static unsigned long imx_get_mcu_clk(void) -{ - return imx_decode_pll(MPCTL0, CLK32 * 512); -} - -/* - * get peripheral clock 1 ( UART[12], Timer[12], PWM ) - */ -static unsigned long imx_get_perclk1(void) -{ - return imx_get_system_clk() / (((PCDR) & 0xf)+1); -} - -/* - * get peripheral clock 2 ( LCD, SD, SPI[12] ) - */ -static unsigned long imx_get_perclk2(void) -{ - return imx_get_system_clk() / (((PCDR>>4) & 0xf)+1); -} - -/* - * get peripheral clock 3 ( SSI ) - */ -static unsigned long imx_get_perclk3(void) -{ - return imx_get_system_clk() / (((PCDR>>16) & 0x7f)+1); -} - -/* - * get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA ) - */ -static unsigned long imx_get_hclk(void) -{ - return imx_get_system_clk() / (((CSCR>>10) & 0xf)+1); -} - -static struct clk clk_system_clk = { - .name = "system_clk", - .get_rate = imx_get_system_clk, -}; - -static struct clk clk_hclk = { - .name = "hclk", - .get_rate = imx_get_hclk, -}; - -static struct clk clk_mcu_clk = { - .name = "mcu_clk", - .get_rate = imx_get_mcu_clk, -}; - -static struct clk clk_perclk1 = { - .name = "perclk1", - .get_rate = imx_get_perclk1, -}; - -static struct clk clk_uart_clk = { - .name = "uart_clk", - .get_rate = imx_get_perclk1, -}; - -static struct clk clk_perclk2 = { - .name = "perclk2", - .get_rate = imx_get_perclk2, -}; - -static struct clk clk_perclk3 = { - .name = "perclk3", - .get_rate = imx_get_perclk3, -}; - -static struct clk *clks[] = { - &clk_perclk1, - &clk_perclk2, - &clk_perclk3, - &clk_system_clk, - &clk_hclk, - &clk_mcu_clk, - &clk_uart_clk, -}; - -static LIST_HEAD(clocks); -static DEFINE_MUTEX(clocks_mutex); - -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *p, *clk = ERR_PTR(-ENOENT); - - mutex_lock(&clocks_mutex); - list_for_each_entry(p, &clocks, node) { - if (!strcmp(p->name, id)) { - clk = p; - goto found; - } - } - -found: - mutex_unlock(&clocks_mutex); - - return clk; -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return clk->get_rate(); -} -EXPORT_SYMBOL(clk_get_rate); - -int imx_clocks_init(void) -{ - int i; - - mutex_lock(&clocks_mutex); - for (i = 0; i < ARRAY_SIZE(clks); i++) - list_add(&clks[i]->node, &clocks); - mutex_unlock(&clocks_mutex); - - return 0; -} - diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c deleted file mode 100644 index 434b4ca0af6..00000000000 --- a/arch/arm/mach-imx/cpufreq.c +++ /dev/null @@ -1,315 +0,0 @@ -/* - * cpu.c: clock scaling for the iMX - * - * Copyright (C) 2000 2001, The Delft University of Technology - * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de> - * Copyright (C) 2006 Inky Lung <ilung@cwlinux.com> - * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com> - * - * Based on SA1100 version written by: - * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version - * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl): - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -/*#define DEBUG*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/cpufreq.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <asm/system.h> - -#include <mach/hardware.h> - -#include "generic.h" - -#ifndef __val2mfld -#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask)) -#endif -#ifndef __mfld2val -#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1))) -#endif - -#define CR_920T_CLOCK_MODE 0xC0000000 -#define CR_920T_FASTBUS_MODE 0x00000000 -#define CR_920T_ASYNC_MODE 0xC0000000 - -static u32 mpctl0_at_boot; -static u32 bclk_div_at_boot; - -static struct clk *system_clk, *mcu_clk; - -static void imx_set_async_mode(void) -{ - adjust_cr(CR_920T_CLOCK_MODE, CR_920T_ASYNC_MODE); -} - -static void imx_set_fastbus_mode(void) -{ - adjust_cr(CR_920T_CLOCK_MODE, CR_920T_FASTBUS_MODE); -} - -static void imx_set_mpctl0(u32 mpctl0) -{ - unsigned long flags; - - if (mpctl0 == 0) { - local_irq_save(flags); - CSCR &= ~CSCR_MPEN; - local_irq_restore(flags); - return; - } - - local_irq_save(flags); - MPCTL0 = mpctl0; - CSCR |= CSCR_MPEN; - local_irq_restore(flags); -} - -/** - * imx_compute_mpctl - compute new PLL parameters - * @new_mpctl: pointer to location assigned by new PLL control register value - * @cur_mpctl: current PLL control register parameters - * @f_ref: reference source frequency Hz - * @freq: required frequency in Hz - * @relation: is one of %CPUFREQ_RELATION_L (supremum) - * and %CPUFREQ_RELATION_H (infimum) - */ -long imx_compute_mpctl(u32 *new_mpctl, u32 cur_mpctl, u32 f_ref, unsigned long freq, int relation) -{ - u32 mfi; - u32 mfn; - u32 mfd; - u32 pd; - unsigned long long ll; - long l; - long quot; - - /* Fdppl=2*Fref*(MFI+MFN/(MFD+1))/(PD+1) */ - /* PD=<0,15>, MFD=<1,1023>, MFI=<5,15> MFN=<0,1022> */ - - if (cur_mpctl) { - mfd = ((cur_mpctl >> 16) & 0x3ff) + 1; - pd = ((cur_mpctl >> 26) & 0xf) + 1; - } else { - pd=2; mfd=313; - } - - /* pd=2; mfd=313; mfi=8; mfn=183; */ - /* (MFI+MFN/(MFD)) = Fdppl / (2*Fref) * (PD); */ - - quot = (f_ref + (1 << 9)) >> 10; - l = (freq * pd + quot) / (2 * quot); - mfi = l >> 10; - mfn = ((l & ((1 << 10) - 1)) * mfd + (1 << 9)) >> 10; - - mfd -= 1; - pd -= 1; - - *new_mpctl = ((mfi & 0xf) << 10) | (mfn & 0x3ff) | ((mfd & 0x3ff) << 16) - | ((pd & 0xf) << 26); - - ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) ); - quot = (pd+1) * (1<<16); - ll += quot / 2; - do_div(ll, quot); - freq = ll; - - pr_debug(KERN_DEBUG "imx: new PLL parameters pd=%d mfd=%d mfi=%d mfn=%d, freq=%ld\n", - pd, mfd, mfi, mfn, freq); - - return freq; -} - - -static int imx_verify_speed(struct cpufreq_policy *policy) -{ - if (policy->cpu != 0) - return -EINVAL; - - cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); - - return 0; -} - -static unsigned int imx_get_speed(unsigned int cpu) -{ - unsigned int freq; - unsigned int cr; - unsigned int cscr; - unsigned int bclk_div; - - if (cpu) - return 0; - - cscr = CSCR; - bclk_div = __mfld2val(CSCR_BCLK_DIV, cscr) + 1; - cr = get_cr(); - - if((cr & CR_920T_CLOCK_MODE) == CR_920T_FASTBUS_MODE) { - freq = clk_get_rate(system_clk); - freq = (freq + bclk_div/2) / bclk_div; - } else { - freq = clk_get_rate(mcu_clk); - if (cscr & CSCR_MPU_PRESC) - freq /= 2; - } - - freq = (freq + 500) / 1000; - - return freq; -} - -static int imx_set_target(struct cpufreq_policy *policy, - unsigned int target_freq, - unsigned int relation) -{ - struct cpufreq_freqs freqs; - u32 mpctl0 = 0; - u32 cscr; - unsigned long flags; - long freq; - long sysclk; - unsigned int bclk_div = bclk_div_at_boot; - - /* - * Some governors do not respects CPU and policy lower limits - * which leads to bad things (division by zero etc), ensure - * that such things do not happen. - */ - if(target_freq < policy->cpuinfo.min_freq) - target_freq = policy->cpuinfo.min_freq; - - if(target_freq < policy->min) - target_freq = policy->min; - - freq = target_freq * 1000; - - pr_debug(KERN_DEBUG "imx: requested frequency %ld Hz, mpctl0 at boot 0x%08x\n", - freq, mpctl0_at_boot); - - sysclk = clk_get_rate(system_clk); - - if (freq > sysclk / bclk_div_at_boot + 1000000) { - freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, CLK32 * 512, freq, relation); - if (freq < 0) { - printk(KERN_WARNING "imx: target frequency %ld Hz cannot be set\n", freq); - return -EINVAL; - } - } else { - if(freq + 1000 < sysclk) { - if (relation == CPUFREQ_RELATION_L) - bclk_div = (sysclk - 1000) / freq; - else - bclk_div = (sysclk + freq + 1000) / freq; - - if(bclk_div > 16) - bclk_div = 16; - if(bclk_div < bclk_div_at_boot) - bclk_div = bclk_div_at_boot; - } - freq = (sysclk + bclk_div / 2) / bclk_div; - } - - freqs.old = imx_get_speed(0); - freqs.new = (freq + 500) / 1000; - freqs.cpu = 0; - freqs.flags = 0; - - cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); - - local_irq_save(flags); - - imx_set_fastbus_mode(); - - imx_set_mpctl0(mpctl0); - - cscr = CSCR; - cscr &= ~CSCR_BCLK_DIV; - cscr |= __val2mfld(CSCR_BCLK_DIV, bclk_div - 1); - CSCR = cscr; - - if(mpctl0) { - CSCR |= CSCR_MPLL_RESTART; - - /* Wait until MPLL is stabilized */ - while( CSCR & CSCR_MPLL_RESTART ); - - imx_set_async_mode(); - } - - local_irq_restore(flags); - - cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); - - pr_debug(KERN_INFO "imx: set frequency %ld Hz, running from %s\n", - freq, mpctl0? "MPLL": "SPLL"); - - return 0; -} - -static int __init imx_cpufreq_driver_init(struct cpufreq_policy *policy) -{ - printk(KERN_INFO "i.MX cpu freq change driver v1.0\n"); - - if (policy->cpu != 0) - return -EINVAL; - - policy->cur = policy->min = policy->max = imx_get_speed(0); - policy->cpuinfo.min_freq = 8000; - policy->cpuinfo.max_freq = 200000; - /* Manual states, that PLL stabilizes in two CLK32 periods */ - policy->cpuinfo.transition_latency = 4 * 1000000000LL / CLK32; - return 0; -} - -static struct cpufreq_driver imx_driver = { - .flags = CPUFREQ_STICKY, - .verify = imx_verify_speed, - .target = imx_set_target, - .get = imx_get_speed, - .init = imx_cpufreq_driver_init, - .name = "imx", -}; - -static int __init imx_cpufreq_init(void) -{ - bclk_div_at_boot = __mfld2val(CSCR_BCLK_DIV, CSCR) + 1; - mpctl0_at_boot = 0; - - system_clk = clk_get(NULL, "system_clk"); - if (IS_ERR(system_clk)) - return PTR_ERR(system_clk); - - mcu_clk = clk_get(NULL, "mcu_clk"); - if (IS_ERR(mcu_clk)) { - clk_put(system_clk); - return PTR_ERR(mcu_clk); - } - - if((CSCR & CSCR_MPEN) && - ((get_cr() & CR_920T_CLOCK_MODE) != CR_920T_FASTBUS_MODE)) - mpctl0_at_boot = MPCTL0; - - return cpufreq_register_driver(&imx_driver); -} - -arch_initcall(imx_cpufreq_init); - diff --git a/arch/arm/mach-imx/dma.c b/arch/arm/mach-imx/dma.c deleted file mode 100644 index 1536583eece..00000000000 --- a/arch/arm/mach-imx/dma.c +++ /dev/null @@ -1,597 +0,0 @@ -/* - * linux/arch/arm/mach-imx/dma.c - * - * imx DMA registration and IRQ dispatching - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * 2004-03-03 Sascha Hauer <sascha@saschahauer.de> - * initial version heavily inspired by - * linux/arch/arm/mach-pxa/dma.c - * - * 2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz> - * Changed to support scatter gather DMA - * by taking Russell's code from RiscPC - * - * 2006-05-31 Pavel Pisa <pisa@cmp.felk.cvut.cz> - * Corrected error handling code. - * - */ - -#undef DEBUG - -#include <linux/module.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/errno.h> - -#include <asm/scatterlist.h> -#include <asm/system.h> -#include <asm/irq.h> -#include <mach/hardware.h> -#include <mach/dma.h> -#include <mach/imx-dma.h> - -struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; - -/* - * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation - * @dma_ch: i.MX DMA channel number - * @lastcount: number of bytes transferred during last transfer - * - * Functions prepares DMA controller for next sg data chunk transfer. - * The @lastcount argument informs function about number of bytes transferred - * during last block. Zero value can be used for @lastcount to setup DMA - * for the first chunk. - */ -static inline int imx_dma_sg_next(imx_dmach_t dma_ch, unsigned int lastcount) -{ - struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; - unsigned int nextcount; - unsigned int nextaddr; - - if (!imxdma->name) { - printk(KERN_CRIT "%s: called for not allocated channel %d\n", - __func__, dma_ch); - return 0; - } - - imxdma->resbytes -= lastcount; - - if (!imxdma->sg) { - pr_debug("imxdma%d: no sg data\n", dma_ch); - return 0; - } - - imxdma->sgbc += lastcount; - if ((imxdma->sgbc >= imxdma->sg->length) || !imxdma->resbytes) { - if ((imxdma->sgcount <= 1) || !imxdma->resbytes) { - pr_debug("imxdma%d: sg transfer limit reached\n", - dma_ch); - imxdma->sgcount=0; - imxdma->sg = NULL; - return 0; - } else { - imxdma->sgcount--; - imxdma->sg++; - imxdma->sgbc = 0; - } - } - nextcount = imxdma->sg->length - imxdma->sgbc; - nextaddr = imxdma->sg->dma_address + imxdma->sgbc; - - if(imxdma->resbytes < nextcount) - nextcount = imxdma->resbytes; - - if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ) - DAR(dma_ch) = nextaddr; - else - SAR(dma_ch) = nextaddr; - - CNTR(dma_ch) = nextcount; - pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, size 0x%08x\n", - dma_ch, DAR(dma_ch), SAR(dma_ch), CNTR(dma_ch)); - - return nextcount; -} - -/* - * imx_dma_setup_sg_base - scatter-gather DMA emulation - * @dma_ch: i.MX DMA channel number - * @sg: pointer to the scatter-gather list/vector - * @sgcount: scatter-gather list hungs count - * - * Functions sets up i.MX DMA state for emulated scatter-gather transfer - * and sets up channel registers to be ready for the first chunk - */ -static int -imx_dma_setup_sg_base(imx_dmach_t dma_ch, - struct scatterlist *sg, unsigned int sgcount) -{ - struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; - - imxdma->sg = sg; - imxdma->sgcount = sgcount; - imxdma->sgbc = 0; - return imx_dma_sg_next(dma_ch, 0); -} - -/** - * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from device transfer - * @dma_ch: i.MX DMA channel number - * @dma_address: the DMA/physical memory address of the linear data block - * to transfer - * @dma_length: length of the data block in bytes - * @dev_addr: physical device port address - * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory - * or %DMA_MODE_WRITE from memory to the device - * - * The function setups DMA channel source and destination addresses for transfer - * specified by provided parameters. The scatter-gather emulation is disabled, - * because linear data block - * form the physical address range is transferred. - * Return value: if incorrect parameters are provided -%EINVAL. - * Zero indicates success. - */ -int -imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, - unsigned int dma_length, unsigned int dev_addr, - unsigned int dmamode) -{ - struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; - - imxdma->sg = NULL; - imxdma->sgcount = 0; - imxdma->dma_mode = dmamode; - imxdma->resbytes = dma_length; - - if (!dma_address) { - printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n", - dma_ch); - return -EINVAL; - } - - if (!dma_length) { - printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n", - dma_ch); - return -EINVAL; - } - - if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) { - pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for read\n", - dma_ch, (unsigned int)dma_address, dma_length, - dev_addr); - SAR(dma_ch) = dev_addr; - DAR(dma_ch) = (unsigned int)dma_address; - } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { - pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for write\n", - dma_ch, (unsigned int)dma_address, dma_length, - dev_addr); - SAR(dma_ch) = (unsigned int)dma_address; - DAR(dma_ch) = dev_addr; - } else { - printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n", - dma_ch); - return -EINVAL; - } - - CNTR(dma_ch) = dma_length; - - return 0; -} - -/** - * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer - * @dma_ch: i.MX DMA channel number - * @sg: pointer to the scatter-gather list/vector - * @sgcount: scatter-gather list hungs count - * @dma_length: total length of the transfer request in bytes - * @dev_addr: physical device port address - * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory - * or %DMA_MODE_WRITE from memory to the device - * - * The function sets up DMA channel state and registers to be ready for transfer - * specified by provided parameters. The scatter-gather emulation is set up - * according to the parameters. - * - * The full preparation of the transfer requires setup of more register - * by the caller before imx_dma_enable() can be called. - * - * %BLR(dma_ch) holds transfer burst length in bytes, 0 means 64 bytes - * - * %RSSR(dma_ch) has to be set to the DMA request line source %DMA_REQ_xxx - * - * %CCR(dma_ch) has to specify transfer parameters, the next settings is typical - * for linear or simple scatter-gather transfers if %DMA_MODE_READ is specified - * - * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x - * - * The typical setup for %DMA_MODE_WRITE is specified by next options combination - * - * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x - * - * Be careful here and do not mistakenly mix source and target device - * port sizes constants, they are really different: - * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32, - * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32 - * - * Return value: if incorrect parameters are provided -%EINVAL. - * Zero indicates success. - */ -int -imx_dma_setup_sg(imx_dmach_t dma_ch, - struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, - unsigned int dev_addr, unsigned int dmamode) -{ - int res; - struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; - - imxdma->sg = NULL; - imxdma->sgcount = 0; - imxdma->dma_mode = dmamode; - imxdma->resbytes = dma_length; - - if (!sg || !sgcount) { - printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n", - dma_ch); - return -EINVAL; - } - - if (!sg->length) { - printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n", - dma_ch); - return -EINVAL; - } - - if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) { - pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for read\n", - dma_ch, sg, sgcount, dma_length, dev_addr); - SAR(dma_ch) = dev_addr; - } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { - pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for write\n", - dma_ch, sg, sgcount, dma_length, dev_addr); - DAR(dma_ch) = dev_addr; - } else { - printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n", - dma_ch); - return -EINVAL; - } - - res = imx_dma_setup_sg_base(dma_ch, sg, sgcount); - if (res <= 0) { - printk(KERN_ERR "imxdma%d: no sg chunk ready\n", dma_ch); - return -EINVAL; - } - - return 0; -} - -/** - * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification handlers - * @dma_ch: i.MX DMA channel number - * @irq_handler: the pointer to the function called if the transfer - * ends successfully - * @err_handler: the pointer to the function called if the premature - * end caused by error occurs - * @data: user specified value to be passed to the handlers - */ -int -imx_dma_setup_handlers(imx_dmach_t dma_ch, - void (*irq_handler) (int, void *), - void (*err_handler) (int, void *, int), - void *data) -{ - struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; - unsigned long flags; - - if (!imxdma->name) { - printk(KERN_CRIT "%s: called for not allocated channel %d\n", - __func__, dma_ch); - return -ENODEV; - } - - local_irq_save(flags); - DISR = (1 << dma_ch); - imxdma->irq_handler = irq_handler; - imxdma->err_handler = err_handler; - imxdma->data = data; - local_irq_restore(flags); - return 0; -} - -/** - * imx_dma_enable - function to start i.MX DMA channel operation - * @dma_ch: i.MX DMA channel number - * - * The channel has to be allocated by driver through imx_dma_request() - * or imx_dma_request_by_prio() function. - * The transfer parameters has to be set to the channel registers through - * call of the imx_dma_setup_single() or imx_dma_setup_sg() function - * and registers %BLR(dma_ch), %RSSR(dma_ch) and %CCR(dma_ch) has to - * be set prior this function call by the channel user. - */ -void imx_dma_enable(imx_dmach_t dma_ch) -{ - struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; - unsigned long flags; - - pr_debug("imxdma%d: imx_dma_enable\n", dma_ch); - - if (!imxdma->name) { - printk(KERN_CRIT "%s: called for not allocated channel %d\n", - __func__, dma_ch); - return; - } - - local_irq_save(flags); - DISR = (1 << dma_ch); - DIMR &= ~(1 << dma_ch); - CCR(dma_ch) |= CCR_CEN; - local_irq_restore(flags); -} - -/** - * imx_dma_disable - stop, finish i.MX DMA channel operatin - * @dma_ch: i.MX DMA channel number - */ -void imx_dma_disable(imx_dmach_t dma_ch) -{ - unsigned long flags; - - pr_debug("imxdma%d: imx_dma_disable\n", dma_ch); - - local_irq_save(flags); - DIMR |= (1 << dma_ch); - CCR(dma_ch) &= ~CCR_CEN; - DISR = (1 << dma_ch); - local_irq_restore(flags); -} - -/** - * imx_dma_request - request/allocate specified channel number - * @dma_ch: i.MX DMA channel number - * @name: the driver/caller own non-%NULL identification - */ -int imx_dma_request(imx_dmach_t dma_ch, const char *name) -{ - struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; - unsigned long flags; - - /* basic sanity checks */ - if (!name) - return -EINVAL; - - if (dma_ch >= IMX_DMA_CHANNELS) { - printk(KERN_CRIT "%s: called for non-existed channel %d\n", - __func__, dma_ch); - return -EINVAL; - } - - local_irq_save(flags); - if (imxdma->name) { - local_irq_restore(flags); - return -ENODEV; - } - - imxdma->name = name; - imxdma->irq_handler = NULL; - imxdma->err_handler = NULL; - imxdma->data = NULL; - imxdma->sg = NULL; - local_irq_restore(flags); - return 0; -} - -/** - * imx_dma_free - release previously acquired channel - * @dma_ch: i.MX DMA channel number - */ -void imx_dma_free(imx_dmach_t dma_ch) -{ - unsigned long flags; - struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; - - if (!imxdma->name) { - printk(KERN_CRIT - "%s: trying to free channel %d which is already freed\n", - __func__, dma_ch); - return; - } - - local_irq_save(flags); - /* Disable interrupts */ - DIMR |= (1 << dma_ch); - CCR(dma_ch) &= ~CCR_CEN; - imxdma->name = NULL; - local_irq_restore(flags); -} - -/** - * imx_dma_request_by_prio - find and request some of free channels best suiting requested priority - * @name: the driver/caller own non-%NULL identification - * @prio: one of the hardware distinguished priority level: - * %DMA_PRIO_HIGH, %DMA_PRIO_MEDIUM, %DMA_PRIO_LOW - * - * This function tries to find free channel in the specified priority group - * if the priority cannot be achieved it tries to look for free channel - * in the higher and then even lower priority groups. - * - * Return value: If there is no free channel to allocate, -%ENODEV is returned. - * On successful allocation channel is returned. - */ -imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio) -{ - int i; - int best; - - switch (prio) { - case (DMA_PRIO_HIGH): - best = 8; - break; - case (DMA_PRIO_MEDIUM): - best = 4; - break; - case (DMA_PRIO_LOW): - default: - best = 0; - break; - } - - for (i = best; i < IMX_DMA_CHANNELS; i++) { - if (!imx_dma_request(i, name)) { - return i; - } - } - - for (i = best - 1; i >= 0; i--) { - if (!imx_dma_request(i, name)) { - return i; - } - } - - printk(KERN_ERR "%s: no free DMA channel found\n", __func__); - - return -ENODEV; -} - -static irqreturn_t dma_err_handler(int irq, void *dev_id) -{ - int i, disr = DISR; - struct imx_dma_channel *channel; - unsigned int err_mask = DBTOSR | DRTOSR | DSESR | DBOSR; - int errcode; - - DISR = disr & err_mask; - for (i = 0; i < IMX_DMA_CHANNELS; i++) { - if(!(err_mask & (1 << i))) - continue; - channel = &imx_dma_channels[i]; - errcode = 0; - - if (DBTOSR & (1 << i)) { - DBTOSR = (1 << i); - errcode |= IMX_DMA_ERR_BURST; - } - if (DRTOSR & (1 << i)) { - DRTOSR = (1 << i); - errcode |= IMX_DMA_ERR_REQUEST; - } - if (DSESR & (1 << i)) { - DSESR = (1 << i); - errcode |= IMX_DMA_ERR_TRANSFER; - } - if (DBOSR & (1 << i)) { - DBOSR = (1 << i); - errcode |= IMX_DMA_ERR_BUFFER; - } - - /* - * The cleaning of @sg field would be questionable - * there, because its value can help to compute - * remaining/transferred bytes count in the handler - */ - /*imx_dma_channels[i].sg = NULL;*/ - - if (channel->name && channel->err_handler) { - channel->err_handler(i, channel->data, errcode); - continue; - } - - imx_dma_channels[i].sg = NULL; - - printk(KERN_WARNING - "DMA timeout on channel %d (%s) -%s%s%s%s\n", - i, channel->name, - errcode&IMX_DMA_ERR_BURST? " burst":"", - errcode&IMX_DMA_ERR_REQUEST? " request":"", - errcode&IMX_DMA_ERR_TRANSFER? " transfer":"", - errcode&IMX_DMA_ERR_BUFFER? " buffer":""); - } - return IRQ_HANDLED; -} - -static irqreturn_t dma_irq_handler(int irq, void *dev_id) -{ - int i, disr = DISR; - - pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n", - disr); - - DISR = disr; - for (i = 0; i < IMX_DMA_CHANNELS; i++) { - if (disr & (1 << i)) { - struct imx_dma_channel *channel = &imx_dma_channels[i]; - if (channel->name) { - if (imx_dma_sg_next(i, CNTR(i))) { - CCR(i) &= ~CCR_CEN; - mb(); - CCR(i) |= CCR_CEN; - } else { - if (channel->irq_handler) - channel->irq_handler(i, - channel->data); - } - } else { - /* - * IRQ for an unregistered DMA channel: - * let's clear the interrupts and disable it. - */ - printk(KERN_WARNING - "spurious IRQ for DMA channel %d\n", i); - } - } - } - return IRQ_HANDLED; -} - -static int __init imx_dma_init(void) -{ - int ret; - int i; - - /* reset DMA module */ - DCR = DCR_DRST; - - ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL); - if (ret) { - printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n"); - return ret; - } - - ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL); - if (ret) { - printk(KERN_CRIT "Wow! Can't register ERRIRQ for DMA\n"); - free_irq(DMA_INT, NULL); - } - - /* enable DMA module */ - DCR = DCR_DEN; - - /* clear all interrupts */ - DISR = (1 << IMX_DMA_CHANNELS) - 1; - - /* enable interrupts */ - DIMR = (1 << IMX_DMA_CHANNELS) - 1; - - for (i = 0; i < IMX_DMA_CHANNELS; i++) { - imx_dma_channels[i].sg = NULL; - imx_dma_channels[i].dma_num = i; - } - - return ret; -} - -arch_initcall(imx_dma_init); - -EXPORT_SYMBOL(imx_dma_setup_single); -EXPORT_SYMBOL(imx_dma_setup_sg); -EXPORT_SYMBOL(imx_dma_setup_handlers); -EXPORT_SYMBOL(imx_dma_enable); -EXPORT_SYMBOL(imx_dma_disable); -EXPORT_SYMBOL(imx_dma_request); -EXPORT_SYMBOL(imx_dma_free); -EXPORT_SYMBOL(imx_dma_request_by_prio); -EXPORT_SYMBOL(imx_dma_channels); diff --git a/arch/arm/mach-imx/generic.c b/arch/arm/mach-imx/generic.c deleted file mode 100644 index 05f1739ee12..00000000000 --- a/arch/arm/mach-imx/generic.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - * arch/arm/mach-imx/generic.c - * - * author: Sascha Hauer - * Created: april 20th, 2004 - * Copyright: Synertronixx GmbH - * - * Common code for i.MX machines - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ -#include <linux/platform_device.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/string.h> - -#include <asm/errno.h> -#include <mach/hardware.h> -#include <mach/imx-regs.h> - -#include <asm/mach/map.h> -#include <mach/mmc.h> -#include <mach/gpio.h> - -unsigned long imx_gpio_alloc_map[(GPIO_PORT_MAX + 1) * 32 / BITS_PER_LONG]; - -void imx_gpio_mode(int gpio_mode) -{ - unsigned int pin = gpio_mode & GPIO_PIN_MASK; - unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; - unsigned int tmp; - - /* Pullup enable */ - if(gpio_mode & GPIO_PUEN) - PUEN(port) |= (1<<pin); - else - PUEN(port) &= ~(1<<pin); - - /* Data direction */ - if(gpio_mode & GPIO_OUT) - DDIR(port) |= 1<<pin; - else - DDIR(port) &= ~(1<<pin); - - /* Primary / alternate function */ - if(gpio_mode & GPIO_AF) - GPR(port) |= (1<<pin); - else - GPR(port) &= ~(1<<pin); - - /* use as gpio? */ - if(gpio_mode & GPIO_GIUS) - GIUS(port) |= (1<<pin); - else - GIUS(port) &= ~(1<<pin); - - /* Output / input configuration */ - /* FIXME: I'm not very sure about OCR and ICONF, someone - * should have a look over it - */ - if(pin<16) { - tmp = OCR1(port); - tmp &= ~( 3<<(pin*2)); - tmp |= (ocr << (pin*2)); - OCR1(port) = tmp; - - ICONFA1(port) &= ~( 3<<(pin*2)); - ICONFA1(port) |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2); - ICONFB1(port) &= ~( 3<<(pin*2)); - ICONFB1(port) |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2); - } else { - tmp = OCR2(port); - tmp &= ~( 3<<((pin-16)*2)); - tmp |= (ocr << ((pin-16)*2)); - OCR2(port) = tmp; - - ICONFA2(port) &= ~( 3<<((pin-16)*2)); - ICONFA2(port) |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << ((pin-16) * 2); - ICONFB2(port) &= ~( 3<<((pin-16)*2)); - ICONFB2(port) |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << ((pin-16) * 2); - } -} - -EXPORT_SYMBOL(imx_gpio_mode); - -int imx_gpio_request(unsigned gpio, const char *label) -{ - if(gpio >= (GPIO_PORT_MAX + 1) * 32) { - printk(KERN_ERR "imx_gpio: Attempt to request nonexistent GPIO %d for \"%s\"\n", - gpio, label ? label : "?"); - return -EINVAL; - } - - if(test_and_set_bit(gpio, imx_gpio_alloc_map)) { - printk(KERN_ERR "imx_gpio: GPIO %d already used. Allocation for \"%s\" failed\n", - gpio, label ? label : "?"); - return -EBUSY; - } - - return 0; -} - -EXPORT_SYMBOL(imx_gpio_request); - -void imx_gpio_free(unsigned gpio) -{ - if(gpio >= (GPIO_PORT_MAX + 1) * 32) - return; - - clear_bit(gpio, imx_gpio_alloc_map); -} - -EXPORT_SYMBOL(imx_gpio_free); - -int imx_gpio_direction_input(unsigned gpio) -{ - imx_gpio_mode(gpio | GPIO_IN | GPIO_GIUS | GPIO_DR); - return 0; -} - -EXPORT_SYMBOL(imx_gpio_direction_input); - -int imx_gpio_direction_output(unsigned gpio, int value) -{ - imx_gpio_set_value(gpio, value); - imx_gpio_mode(gpio | GPIO_OUT | GPIO_GIUS | GPIO_DR); - return 0; -} - -EXPORT_SYMBOL(imx_gpio_direction_output); - -int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count, - int alloc_mode, const char *label) -{ - const int *p = pin_list; - int i; - unsigned gpio; - unsigned mode; - - for (i = 0; i < count; i++) { - gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); - mode = *p & ~(GPIO_PIN_MASK | GPIO_PORT_MASK); - - if (gpio >= (GPIO_PORT_MAX + 1) * 32) - goto setup_error; - - if (alloc_mode & IMX_GPIO_ALLOC_MODE_RELEASE) - imx_gpio_free(gpio); - else if (!(alloc_mode & IMX_GPIO_ALLOC_MODE_NO_ALLOC)) - if (imx_gpio_request(gpio, label)) - if (!(alloc_mode & IMX_GPIO_ALLOC_MODE_TRY_ALLOC)) - goto setup_error; - - if (!(alloc_mode & (IMX_GPIO_ALLOC_MODE_ALLOC_ONLY | - IMX_GPIO_ALLOC_MODE_RELEASE))) - imx_gpio_mode(gpio | mode); - - p++; - } - return 0; - -setup_error: - if(alloc_mode & (IMX_GPIO_ALLOC_MODE_NO_ALLOC | - IMX_GPIO_ALLOC_MODE_TRY_ALLOC)) - return -EINVAL; - - while (p != pin_list) { - p--; - gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); - imx_gpio_free(gpio); - } - - return -EINVAL; -} - -EXPORT_SYMBOL(imx_gpio_setup_multiple_pins); - -void __imx_gpio_set_value(unsigned gpio, int value) -{ - imx_gpio_set_value_inline(gpio, value); -} - -EXPORT_SYMBOL(__imx_gpio_set_value); - -int imx_gpio_to_irq(unsigned gpio) -{ - return IRQ_GPIOA(0) + gpio; -} - -EXPORT_SYMBOL(imx_gpio_to_irq); - -int imx_irq_to_gpio(unsigned irq) -{ - if (irq < IRQ_GPIOA(0)) - return -EINVAL; - return irq - IRQ_GPIOA(0); -} - -EXPORT_SYMBOL(imx_irq_to_gpio); - -static struct resource imx_mmc_resources[] = { - [0] = { - .start = 0x00214000, - .end = 0x002140FF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = (SDHC_INT), - .end = (SDHC_INT), - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 imxmmmc_dmamask = 0xffffffffUL; - -static struct platform_device imx_mmc_device = { - .name = "imx-mmc", - .id = 0, - .dev = { - .dma_mask = &imxmmmc_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(imx_mmc_resources), - .resource = imx_mmc_resources, -}; - -void __init imx_set_mmc_info(struct imxmmc_platform_data *info) -{ - imx_mmc_device.dev.platform_data = info; -} - -static struct platform_device *devices[] __initdata = { - &imx_mmc_device, -}; - -static struct map_desc imx_io_desc[] __initdata = { - { - .virtual = IMX_IO_BASE, - .pfn = __phys_to_pfn(IMX_IO_PHYS), - .length = IMX_IO_SIZE, - .type = MT_DEVICE - } -}; - -void __init -imx_map_io(void) -{ - iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); -} - -static int __init imx_init(void) -{ - return platform_add_devices(devices, ARRAY_SIZE(devices)); -} - -subsys_initcall(imx_init); diff --git a/arch/arm/mach-imx/generic.h b/arch/arm/mach-imx/generic.h deleted file mode 100644 index e91003e4bef..00000000000 --- a/arch/arm/mach-imx/generic.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * linux/arch/arm/mach-imx/generic.h - * - * Author: Sascha Hauer <sascha@saschahauer.de> - * Copyright: Synertronixx GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -extern void __init imx_map_io(void); -extern void __init imx_init_irq(void); - -struct sys_timer; -extern struct sys_timer imx_timer; diff --git a/arch/arm/mach-imx/include/mach/debug-macro.S b/arch/arm/mach-imx/include/mach/debug-macro.S deleted file mode 100644 index 87802bbfe63..00000000000 --- a/arch/arm/mach-imx/include/mach/debug-macro.S +++ /dev/null @@ -1,34 +0,0 @@ -/* arch/arm/mach-imx/include/mach/debug-macro.S - * - * Debugging macro include header - * - * Copyright (C) 1994-1999 Russell King - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - - .macro addruart,rx - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 @ MMU enabled? - moveq \rx, #0x00000000 @ physical - movne \rx, #0xe0000000 @ virtual - orreq \rx, \rx, #0x00200000 @ physical - orr \rx, \rx, #0x00006000 @ UART1 offset - .endm - - .macro senduart,rd,rx - str \rd, [\rx, #0x40] @ TXDATA - .endm - - .macro waituart,rd,rx - .endm - - .macro busyuart,rd,rx -1002: ldr \rd, [\rx, #0x98] @ SR2 - tst \rd, #1 << 3 @ TXDC - beq 1002b @ wait until transmit done - .endm diff --git a/arch/arm/mach-imx/include/mach/dma.h b/arch/arm/mach-imx/include/mach/dma.h deleted file mode 100644 index 621ff2c730f..00000000000 --- a/arch/arm/mach-imx/include/mach/dma.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * linux/include/asm-arm/imxads/dma.h - * - * Copyright (C) 1997,1998 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_DMA_H -#define __ASM_ARCH_DMA_H - -typedef enum { - DMA_PRIO_HIGH = 0, - DMA_PRIO_MEDIUM = 1, - DMA_PRIO_LOW = 2 -} imx_dma_prio; - -#define DMA_REQ_UART3_T 2 -#define DMA_REQ_UART3_R 3 -#define DMA_REQ_SSI2_T 4 -#define DMA_REQ_SSI2_R 5 -#define DMA_REQ_CSI_STAT 6 -#define DMA_REQ_CSI_R 7 -#define DMA_REQ_MSHC 8 -#define DMA_REQ_DSPA_DCT_DOUT 9 -#define DMA_REQ_DSPA_DCT_DIN 10 -#define DMA_REQ_DSPA_MAC 11 -#define DMA_REQ_EXT 12 -#define DMA_REQ_SDHC 13 -#define DMA_REQ_SPI1_R 14 -#define DMA_REQ_SPI1_T 15 -#define DMA_REQ_SSI_T 16 -#define DMA_REQ_SSI_R 17 -#define DMA_REQ_ASP_DAC 18 -#define DMA_REQ_ASP_ADC 19 -#define DMA_REQ_USP_EP(x) (20+(x)) -#define DMA_REQ_SPI2_R 26 -#define DMA_REQ_SPI2_T 27 -#define DMA_REQ_UART2_T 28 -#define DMA_REQ_UART2_R 29 -#define DMA_REQ_UART1_T 30 -#define DMA_REQ_UART1_R 31 - -#endif /* _ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-imx/include/mach/entry-macro.S b/arch/arm/mach-imx/include/mach/entry-macro.S deleted file mode 100644 index e4db679f776..00000000000 --- a/arch/arm/mach-imx/include/mach/entry-macro.S +++ /dev/null @@ -1,32 +0,0 @@ -/* - * arch/arm/mach-imx/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for iMX-based platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <mach/hardware.h> - - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - -#define AITC_NIVECSR 0x40 - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \base, =IO_ADDRESS(IMX_AITC_BASE) - @ Load offset & priority of the highest priority - @ interrupt pending. - ldr \irqstat, [\base, #AITC_NIVECSR] - @ Shift off the priority leaving the offset or - @ "interrupt number", use arithmetic shift to - @ transform illegal source (0xffff) as -1 - mov \irqnr, \irqstat, asr #16 - adds \tmp, \irqnr, #1 - .endm diff --git a/arch/arm/mach-imx/include/mach/gpio.h b/arch/arm/mach-imx/include/mach/gpio.h deleted file mode 100644 index 6c2942f8292..00000000000 --- a/arch/arm/mach-imx/include/mach/gpio.h +++ /dev/null @@ -1,106 +0,0 @@ -#ifndef _IMX_GPIO_H - -#include <linux/kernel.h> -#include <mach/hardware.h> -#include <mach/imx-regs.h> - -#define IMX_GPIO_ALLOC_MODE_NORMAL 0 -#define IMX_GPIO_ALLOC_MODE_NO_ALLOC 1 -#define IMX_GPIO_ALLOC_MODE_TRY_ALLOC 2 -#define IMX_GPIO_ALLOC_MODE_ALLOC_ONLY 4 -#define IMX_GPIO_ALLOC_MODE_RELEASE 8 - -extern int imx_gpio_request(unsigned gpio, const char *label); - -extern void imx_gpio_free(unsigned gpio); - -extern int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count, - int alloc_mode, const char *label); - -extern int imx_gpio_direction_input(unsigned gpio); - -extern int imx_gpio_direction_output(unsigned gpio, int value); - -extern void __imx_gpio_set_value(unsigned gpio, int value); - -static inline int imx_gpio_get_value(unsigned gpio) -{ - return SSR(gpio >> GPIO_PORT_SHIFT) & (1 << (gpio & GPIO_PIN_MASK)); -} - -static inline void imx_gpio_set_value_inline(unsigned gpio, int value) -{ - unsigned long flags; - - raw_local_irq_save(flags); - if(value) - DR(gpio >> GPIO_PORT_SHIFT) |= (1 << (gpio & GPIO_PIN_MASK)); - else - DR(gpio >> GPIO_PORT_SHIFT) &= ~(1 << (gpio & GPIO_PIN_MASK)); - raw_local_irq_restore(flags); -} - -static inline void imx_gpio_set_value(unsigned gpio, int value) -{ - if(__builtin_constant_p(gpio)) - imx_gpio_set_value_inline(gpio, value); - else - __imx_gpio_set_value(gpio, value); -} - -extern int imx_gpio_to_irq(unsigned gpio); - -extern int imx_irq_to_gpio(unsigned irq); - -/*-------------------------------------------------------------------------*/ - -/* Wrappers for "new style" GPIO calls. These calls i.MX specific versions - * to allow future extension of GPIO logic. - */ - -static inline int gpio_request(unsigned gpio, const char *label) -{ - return imx_gpio_request(gpio, label); -} - -static inline void gpio_free(unsigned gpio) -{ - might_sleep(); - - imx_gpio_free(gpio); -} - -static inline int gpio_direction_input(unsigned gpio) -{ - return imx_gpio_direction_input(gpio); -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ - return imx_gpio_direction_output(gpio, value); -} - -static inline int gpio_get_value(unsigned gpio) -{ - return imx_gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - imx_gpio_set_value(gpio, value); -} - -#include <asm-generic/gpio.h> /* cansleep wrappers */ - -static inline int gpio_to_irq(unsigned gpio) -{ - return imx_gpio_to_irq(gpio); -} - -static inline int irq_to_gpio(unsigned irq) -{ - return imx_irq_to_gpio(irq); -} - - -#endif diff --git a/arch/arm/mach-imx/include/mach/hardware.h b/arch/arm/mach-imx/include/mach/hardware.h deleted file mode 100644 index c73e9e724c7..00000000000 --- a/arch/arm/mach-imx/include/mach/hardware.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * arch/arm/mach-imx/include/mach/hardware.h - * - * Copyright (C) 1999 ARM Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <asm/sizes.h> -#include "imx-regs.h" - -#ifndef __ASSEMBLY__ -# define __REG(x) (*((volatile u32 *)IO_ADDRESS(x))) - -# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) -#endif - -/* - * Memory map - */ - -#define IMX_IO_PHYS 0x00200000 -#define IMX_IO_SIZE 0x00100000 -#define IMX_IO_BASE 0xe0000000 - -#define IMX_CS0_PHYS 0x10000000 -#define IMX_CS0_SIZE 0x02000000 -#define IMX_CS0_VIRT 0xe8000000 - -#define IMX_CS1_PHYS 0x12000000 -#define IMX_CS1_SIZE 0x01000000 -#define IMX_CS1_VIRT 0xea000000 - -#define IMX_CS2_PHYS 0x13000000 -#define IMX_CS2_SIZE 0x01000000 -#define IMX_CS2_VIRT 0xeb000000 - -#define IMX_CS3_PHYS 0x14000000 -#define IMX_CS3_SIZE 0x01000000 -#define IMX_CS3_VIRT 0xec000000 - -#define IMX_CS4_PHYS 0x15000000 -#define IMX_CS4_SIZE 0x01000000 -#define IMX_CS4_VIRT 0xed000000 - -#define IMX_CS5_PHYS 0x16000000 -#define IMX_CS5_SIZE 0x01000000 -#define IMX_CS5_VIRT 0xee000000 - -#define IMX_FB_VIRT 0xF1000000 -#define IMX_FB_SIZE (256*1024) - -/* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) ((x) | IMX_IO_BASE) - -#ifndef __ASSEMBLY__ -/* - * Handy routine to set GPIO functions - */ -extern void imx_gpio_mode( int gpio_mode ); - -#endif - -#define MAXIRQNUM 62 -#define MAXFIQNUM 62 -#define MAXSWINUM 62 - -/* - * Use SDRAM for memory - */ -#define MEM_SIZE 0x01000000 - -#ifdef CONFIG_ARCH_MX1ADS -#include "mx1ads.h" -#endif - -#endif diff --git a/arch/arm/mach-imx/include/mach/imx-dma.h b/arch/arm/mach-imx/include/mach/imx-dma.h deleted file mode 100644 index bbe54df7f0d..00000000000 --- a/arch/arm/mach-imx/include/mach/imx-dma.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * linux/include/asm-arm/imxads/dma.h - * - * Copyright (C) 1997,1998 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <mach/dma.h> - -#ifndef __ASM_ARCH_IMX_DMA_H -#define __ASM_ARCH_IMX_DMA_H - -#define IMX_DMA_CHANNELS 11 - -/* - * struct imx_dma_channel - i.MX specific DMA extension - * @name: name specified by DMA client - * @irq_handler: client callback for end of transfer - * @err_handler: client callback for error condition - * @data: clients context data for callbacks - * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE - * @sg: pointer to the actual read/written chunk for scatter-gather emulation - * @sgbc: counter of processed bytes in the actual read/written chunk - * @resbytes: total residual number of bytes to transfer - * (it can be lower or same as sum of SG mapped chunk sizes) - * @sgcount: number of chunks to be read/written - * - * Structure is used for IMX DMA processing. It would be probably good - * @struct dma_struct in the future for external interfacing and use - * @struct imx_dma_channel only as extension to it. - */ - -struct imx_dma_channel { - const char *name; - void (*irq_handler) (int, void *); - void (*err_handler) (int, void *, int errcode); - void *data; - unsigned int dma_mode; - struct scatterlist *sg; - unsigned int sgbc; - unsigned int sgcount; - unsigned int resbytes; - int dma_num; -}; - -extern struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; - -#define IMX_DMA_ERR_BURST 1 -#define IMX_DMA_ERR_REQUEST 2 -#define IMX_DMA_ERR_TRANSFER 4 -#define IMX_DMA_ERR_BUFFER 8 - -/* The type to distinguish channel numbers parameter from ordinal int type */ -typedef int imx_dmach_t; - -#define DMA_MODE_READ 0 -#define DMA_MODE_WRITE 1 -#define DMA_MODE_MASK 1 - -int -imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, - unsigned int dma_length, unsigned int dev_addr, unsigned int dmamode); - -int -imx_dma_setup_sg(imx_dmach_t dma_ch, - struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, - unsigned int dev_addr, unsigned int dmamode); - -int -imx_dma_setup_handlers(imx_dmach_t dma_ch, - void (*irq_handler) (int, void *), - void (*err_handler) (int, void *, int), void *data); - -void imx_dma_enable(imx_dmach_t dma_ch); - -void imx_dma_disable(imx_dmach_t dma_ch); - -int imx_dma_request(imx_dmach_t dma_ch, const char *name); - -void imx_dma_free(imx_dmach_t dma_ch); - -imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio); - - -#endif /* _ASM_ARCH_IMX_DMA_H */ diff --git a/arch/arm/mach-imx/include/mach/imx-regs.h b/arch/arm/mach-imx/include/mach/imx-regs.h deleted file mode 100644 index 490297fc0e3..00000000000 --- a/arch/arm/mach-imx/include/mach/imx-regs.h +++ /dev/null @@ -1,376 +0,0 @@ -#ifndef _IMX_REGS_H -#define _IMX_REGS_H -/* ------------------------------------------------------------------------ - * Motorola IMX system registers - * ------------------------------------------------------------------------ - * - */ - -/* - * Register BASEs, based on OFFSETs - * - */ -#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) -#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE) -#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE) -#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) -#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE) -#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) -#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE) -#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE) -#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) -#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) -#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) -#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) -#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) -#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) -#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) -#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) -#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) -#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) -#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) -#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) -#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) -#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) -#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) -#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) -#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) -#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) -#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) -#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) - -/* PLL registers */ -#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ -#define CSCR_SPLL_RESTART (1<<22) -#define CSCR_MPLL_RESTART (1<<21) -#define CSCR_SYSTEM_SEL (1<<16) -#define CSCR_BCLK_DIV (0xf<<10) -#define CSCR_MPU_PRESC (1<<15) -#define CSCR_SPEN (1<<1) -#define CSCR_MPEN (1<<0) - -#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ -#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ -#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ -#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ -#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ - -/* - * GPIO Module and I/O Multiplexer - * x = 0..3 for reg_A, reg_B, reg_C, reg_D - */ -#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8) -#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8) -#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8) -#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8) -#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8) -#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8) -#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8) -#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8) -#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8) -#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8) -#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8) -#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8) -#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8) -#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8) -#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8) -#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) -#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) - -#define GPIO_PORT_MAX 3 - -#define GPIO_PIN_MASK 0x1f -#define GPIO_PORT_MASK (0x3 << 5) - -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORTA (0<<5) -#define GPIO_PORTB (1<<5) -#define GPIO_PORTC (2<<5) -#define GPIO_PORTD (3<<5) - -#define GPIO_OUT (1<<7) -#define GPIO_IN (0<<7) -#define GPIO_PUEN (1<<8) - -#define GPIO_PF (0<<9) -#define GPIO_AF (1<<9) - -#define GPIO_OCR_SHIFT 10 -#define GPIO_OCR_MASK (3<<10) -#define GPIO_AIN (0<<10) -#define GPIO_BIN (1<<10) -#define GPIO_CIN (2<<10) -#define GPIO_DR (3<<10) - -#define GPIO_AOUT_SHIFT 12 -#define GPIO_AOUT_MASK (3<<12) -#define GPIO_AOUT (0<<12) -#define GPIO_AOUT_ISR (1<<12) -#define GPIO_AOUT_0 (2<<12) -#define GPIO_AOUT_1 (3<<12) - -#define GPIO_BOUT_SHIFT 14 -#define GPIO_BOUT_MASK (3<<14) -#define GPIO_BOUT (0<<14) -#define GPIO_BOUT_ISR (1<<14) -#define GPIO_BOUT_0 (2<<14) -#define GPIO_BOUT_1 (3<<14) - -#define GPIO_GIUS (1<<16) - -/* assignements for GPIO alternate/primary functions */ - -/* FIXME: This list is not completed. The correct directions are - * missing on some (many) pins - */ -#define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 ) -#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) -#define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 ) -#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) -#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) -#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) -#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) -#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) -#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) -#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) -#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) -#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) -#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) -#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) -#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) -#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) -#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) -#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) -#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) -#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) -#define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 ) -#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) -#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) -#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) -#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) -#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) -#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) -#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) -#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) -#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) -#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) -#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) -#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) -#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) -#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) -#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) -#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) -#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) -#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) -#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) -#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) -#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) -#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) -#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) -#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) -#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) -#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) -#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) -#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) -#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 ) -#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) -#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 ) -#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) -#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 ) -#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) -#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) -#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) -#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) -#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) -#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) -#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) -#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) -#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) -#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) -#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) -#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) -#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) -#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) -#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) -#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) -#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) -#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) -#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) -#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) -#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) -#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) -#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) -#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) -#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) -#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) -#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) -#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) -#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) -#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) -#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) -#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) -#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) -#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) -#define PC24_BIN_UART3_RI ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 ) -#define PC25_BIN_UART3_DSR ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 ) -#define PC26_AOUT_UART3_DTR ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 ) -#define PC27_BIN_UART3_DCD ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 ) -#define PC28_BIN_UART3_CTS ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 ) -#define PC29_AOUT_UART3_RTS ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 ) -#define PC30_BIN_UART3_TX ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 ) -#define PC31_AOUT_UART3_RX ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31) -#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) -#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) -#define PD7_AF_UART2_DTR ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) -#define PD7_AIN_SPI2_SCLK ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 ) -#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) -#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) -#define PD8_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 ) -#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) -#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) -#define PD9_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 ) -#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) -#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) -#define PD10_AIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 ) -#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) -#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) -#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) -#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) -#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) -#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) -#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) -#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) -#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) -#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) -#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) -#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) -#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) -#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) -#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) -#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) -#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) -#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) -#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) -#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) -#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) -#define PD31_BIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 ) - -/* - * PWM controller - */ -#define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */ -#define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */ -#define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */ -#define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */ - -#define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */ -#define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */ -#define PWMC_SWR (0x01<<16) /* Software Reset */ -#define PWMC_CLKSRC (0x01<<15) /* Clock Source */ -#define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */ -#define PWMC_IRQ (0x01<< 7) /* Interrupt Request */ -#define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */ -#define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */ -#define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */ -#define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */ -#define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */ - -#define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */ -#define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */ -#define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */ - -/* - * DMA Controller - */ -#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */ -#define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */ -#define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */ -#define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */ -#define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */ -#define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */ -#define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */ -#define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */ -#define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */ -#define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */ -#define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */ -#define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */ -#define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */ -#define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */ -#define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */ -#define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */ -#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */ -#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */ -#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */ -#define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */ -#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */ -#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */ - -#define DCR_DRST (1<<1) -#define DCR_DEN (1<<0) -#define DBTOCR_EN (1<<15) -#define DBTOCR_CNT(x) ((x) & 0x7fff ) -#define CNTR_CNT(x) ((x) & 0xffffff ) -#define CCR_DMOD_LINEAR ( 0x0 << 12 ) -#define CCR_DMOD_2D ( 0x1 << 12 ) -#define CCR_DMOD_FIFO ( 0x2 << 12 ) -#define CCR_DMOD_EOBFIFO ( 0x3 << 12 ) -#define CCR_SMOD_LINEAR ( 0x0 << 10 ) -#define CCR_SMOD_2D ( 0x1 << 10 ) -#define CCR_SMOD_FIFO ( 0x2 << 10 ) -#define CCR_SMOD_EOBFIFO ( 0x3 << 10 ) -#define CCR_MDIR_DEC (1<<9) -#define CCR_MSEL_B (1<<8) -#define CCR_DSIZ_32 ( 0x0 << 6 ) -#define CCR_DSIZ_8 ( 0x1 << 6 ) -#define CCR_DSIZ_16 ( 0x2 << 6 ) -#define CCR_SSIZ_32 ( 0x0 << 4 ) -#define CCR_SSIZ_8 ( 0x1 << 4 ) -#define CCR_SSIZ_16 ( 0x2 << 4 ) -#define CCR_REN (1<<3) -#define CCR_RPT (1<<2) -#define CCR_FRC (1<<1) -#define CCR_CEN (1<<0) -#define RTOR_EN (1<<15) -#define RTOR_CLK (1<<14) -#define RTOR_PSC (1<<13) - -/* - * Interrupt controller - */ - -#define IMX_INTCNTL __REG(IMX_AITC_BASE+0x00) -#define INTCNTL_FIAD (1<<19) -#define INTCNTL_NIAD (1<<20) - -#define IMX_NIMASK __REG(IMX_AITC_BASE+0x04) -#define IMX_INTENNUM __REG(IMX_AITC_BASE+0x08) -#define IMX_INTDISNUM __REG(IMX_AITC_BASE+0x0c) -#define IMX_INTENABLEH __REG(IMX_AITC_BASE+0x10) -#define IMX_INTENABLEL __REG(IMX_AITC_BASE+0x14) - -/* - * General purpose timers - */ -#define IMX_TCTL(x) __REG( 0x00 + (x)) -#define TCTL_SWR (1<<15) -#define TCTL_FRR (1<<8) -#define TCTL_CAP_RIS (1<<6) -#define TCTL_CAP_FAL (2<<6) -#define TCTL_CAP_RIS_FAL (3<<6) -#define TCTL_OM (1<<5) -#define TCTL_IRQEN (1<<4) -#define TCTL_CLK_PCLK1 (1<<1) -#define TCTL_CLK_PCLK1_16 (2<<1) -#define TCTL_CLK_TIN (3<<1) -#define TCTL_CLK_32 (4<<1) -#define TCTL_TEN (1<<0) - -#define IMX_TPRER(x) __REG( 0x04 + (x)) -#define IMX_TCMP(x) __REG( 0x08 + (x)) -#define IMX_TCR(x) __REG( 0x0C + (x)) -#define IMX_TCN(x) __REG( 0x10 + (x)) -#define IMX_TSTAT(x) __REG( 0x14 + (x)) -#define TSTAT_CAPT (1<<1) -#define TSTAT_COMP (1<<0) - -#endif // _IMX_REGS_H diff --git a/arch/arm/mach-imx/include/mach/imx-uart.h b/arch/arm/mach-imx/include/mach/imx-uart.h deleted file mode 100644 index d54eb1d4802..00000000000 --- a/arch/arm/mach-imx/include/mach/imx-uart.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef ASMARM_ARCH_UART_H -#define ASMARM_ARCH_UART_H - -#define IMXUART_HAVE_RTSCTS (1<<0) - -struct imxuart_platform_data { - int (*init)(struct platform_device *pdev); - void (*exit)(struct platform_device *pdev); - unsigned int flags; -}; - -#endif diff --git a/arch/arm/mach-imx/include/mach/io.h b/arch/arm/mach-imx/include/mach/io.h deleted file mode 100644 index 9e197ae4590..00000000000 --- a/arch/arm/mach-imx/include/mach/io.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * arch/arm/mach-imxads/include/mach/io.h - * - * Copyright (C) 1999 ARM Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) - -#endif diff --git a/arch/arm/mach-imx/include/mach/irqs.h b/arch/arm/mach-imx/include/mach/irqs.h deleted file mode 100644 index 67812c5ac1f..00000000000 --- a/arch/arm/mach-imx/include/mach/irqs.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * arch/arm/mach-imxads/include/mach/irqs.h - * - * Copyright (C) 1999 ARM Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ARM_IRQS_H__ -#define __ARM_IRQS_H__ - -/* Use the imx definitions */ -#include <mach/hardware.h> - -/* - * IMX Interrupt numbers - * - */ -#define INT_SOFTINT 0 -#define CSI_INT 6 -#define DSPA_MAC_INT 7 -#define DSPA_INT 8 -#define COMP_INT 9 -#define MSHC_XINT 10 -#define GPIO_INT_PORTA 11 -#define GPIO_INT_PORTB 12 -#define GPIO_INT_PORTC 13 -#define LCDC_INT 14 -#define SIM_INT 15 -#define SIM_DATA_INT 16 -#define RTC_INT 17 -#define RTC_SAMINT 18 -#define UART2_MINT_PFERR 19 -#define UART2_MINT_RTS 20 -#define UART2_MINT_DTR 21 -#define UART2_MINT_UARTC 22 -#define UART2_MINT_TX 23 -#define UART2_MINT_RX 24 -#define UART1_MINT_PFERR 25 -#define UART1_MINT_RTS 26 -#define UART1_MINT_DTR 27 -#define UART1_MINT_UARTC 28 -#define UART1_MINT_TX 29 -#define UART1_MINT_RX 30 -#define VOICE_DAC_INT 31 -#define VOICE_ADC_INT 32 -#define PEN_DATA_INT 33 -#define PWM_INT 34 -#define SDHC_INT 35 -#define I2C_INT 39 -#define CSPI_INT 41 -#define SSI_TX_INT 42 -#define SSI_TX_ERR_INT 43 -#define SSI_RX_INT 44 -#define SSI_RX_ERR_INT 45 -#define TOUCH_INT 46 -#define USBD_INT0 47 -#define USBD_INT1 48 -#define USBD_INT2 49 -#define USBD_INT3 50 -#define USBD_INT4 51 -#define USBD_INT5 52 -#define USBD_INT6 53 -#define BTSYS_INT 55 -#define BTTIM_INT 56 -#define BTWUI_INT 57 -#define TIM2_INT 58 -#define TIM1_INT 59 -#define DMA_ERR 60 -#define DMA_INT 61 -#define GPIO_INT_PORTD 62 - -#define IMX_IRQS (64) - -/* note: the IMX has four gpio ports (A-D), but only - * the following pins are connected to the outside - * world: - * - * PORT A: bits 0-31 - * PORT B: bits 8-31 - * PORT C: bits 3-17 - * PORT D: bits 6-31 - * - * We map these interrupts straight on. As a result we have - * several holes in the interrupt mapping. We do this for two - * reasons: - * - mapping the interrupts without holes would get - * far more complicated - * - Motorola could well decide to bring some processor - * with more pins connected - */ - -#define IRQ_GPIOA(x) (IMX_IRQS + x) -#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) -#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) -#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) - -/* decode irq number to use with IMR(x), ISR(x) and friends */ -#define IRQ_TO_REG(irq) ((irq - IMX_IRQS) >> 5) - -/* all normal IRQs can be FIQs */ -#define FIQ_START 0 -/* switch betwean IRQ and FIQ */ -extern int imx_set_irq_fiq(unsigned int irq, unsigned int type); - -#define NR_IRQS (IRQ_GPIOD(32) + 1) -#define IRQ_GPIO(x) -#endif diff --git a/arch/arm/mach-imx/include/mach/memory.h b/arch/arm/mach-imx/include/mach/memory.h deleted file mode 100644 index a93df7cba69..00000000000 --- a/arch/arm/mach-imx/include/mach/memory.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * arch/arm/mach-imx/include/mach/memory.h - * - * Copyright (C) 1999 ARM Limited - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_MMU_H -#define __ASM_ARCH_MMU_H - -#define PHYS_OFFSET UL(0x08000000) - -#endif diff --git a/arch/arm/mach-imx/include/mach/mmc.h b/arch/arm/mach-imx/include/mach/mmc.h deleted file mode 100644 index 4712f354dcc..00000000000 --- a/arch/arm/mach-imx/include/mach/mmc.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef ASMARM_ARCH_MMC_H -#define ASMARM_ARCH_MMC_H - -#include <linux/mmc/host.h> - -struct device; - -struct imxmmc_platform_data { - int (*card_present)(struct device *); - int (*get_ro)(struct device *); -}; - -extern void imx_set_mmc_info(struct imxmmc_platform_data *info); - -#endif diff --git a/arch/arm/mach-imx/include/mach/mx1ads.h b/arch/arm/mach-imx/include/mach/mx1ads.h deleted file mode 100644 index def05d510eb..00000000000 --- a/arch/arm/mach-imx/include/mach/mx1ads.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * arch/arm/mach-imx/include/mach/mx1ads.h - * - * Copyright (C) 2004 Robert Schwebel, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#ifndef __ASM_ARCH_MX1ADS_H -#define __ASM_ARCH_MX1ADS_H - -/* ------------------------------------------------------------------------ */ -/* Memory Map for the M9328MX1ADS (MX1ADS) Board */ -/* ------------------------------------------------------------------------ */ - -#define MX1ADS_FLASH_PHYS 0x10000000 -#define MX1ADS_FLASH_SIZE (16*1024*1024) - -#define IMX_FB_PHYS (0x0C000000 - 0x40000) - -#define CLK32 32000 - -#endif /* __ASM_ARCH_MX1ADS_H */ diff --git a/arch/arm/mach-imx/include/mach/spi_imx.h b/arch/arm/mach-imx/include/mach/spi_imx.h deleted file mode 100644 index 4186430feec..00000000000 --- a/arch/arm/mach-imx/include/mach/spi_imx.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * arch/arm/mach-imx/include/mach/spi_imx.h - * - * Copyright (C) 2006 SWAPP - * Andrea Paterniani <a.paterniani@swapp-eng.it> - * - * Initial version inspired by: - * linux-2.6.17-rc3-mm1/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef SPI_IMX_H_ -#define SPI_IMX_H_ - - -/*-------------------------------------------------------------------------*/ -/** - * struct spi_imx_master - device.platform_data for SPI controller devices. - * @num_chipselect: chipselects are used to distinguish individual - * SPI slaves, and are numbered from zero to num_chipselects - 1. - * each slave has a chipselect signal, but it's common that not - * every chipselect is connected to a slave. - * @enable_dma: if true enables DMA driven transfers. -*/ -struct spi_imx_master { - u8 num_chipselect; - u8 enable_dma:1; -}; -/*-------------------------------------------------------------------------*/ - - -/*-------------------------------------------------------------------------*/ -/** - * struct spi_imx_chip - spi_board_info.controller_data for SPI - * slave devices, copied to spi_device.controller_data. - * @enable_loopback : used for test purpouse to internally connect RX and TX - * sections. - * @enable_dma : enables dma transfer (provided that controller driver has - * dma enabled too). - * @ins_ss_pulse : enable /SS pulse insertion between SPI burst. - * @bclk_wait : number of bclk waits between each bits_per_word SPI burst. - * @cs_control : function pointer to board-specific function to assert/deassert - * I/O port to control HW generation of devices chip-select. -*/ -struct spi_imx_chip { - u8 enable_loopback:1; - u8 enable_dma:1; - u8 ins_ss_pulse:1; - u16 bclk_wait:15; - void (*cs_control)(u32 control); -}; - -/* Chip-select state */ -#define SPI_CS_ASSERT (1 << 0) -#define SPI_CS_DEASSERT (1 << 1) -/*-------------------------------------------------------------------------*/ - - -#endif /* SPI_IMX_H_*/ diff --git a/arch/arm/mach-imx/include/mach/system.h b/arch/arm/mach-imx/include/mach/system.h deleted file mode 100644 index 46d4ca91af7..00000000000 --- a/arch/arm/mach-imx/include/mach/system.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * arch/arm/mach-imxads/include/mach/system.h - * - * Copyright (C) 1999 ARM Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -static void -arch_idle(void) -{ - /* - * This should do all the clock switching - * and wait for interrupt tricks - */ - cpu_do_idle(); -} - -static inline void -arch_reset(char mode, const char *cmd) -{ - cpu_reset(0); -} - -#endif diff --git a/arch/arm/mach-imx/include/mach/uncompress.h b/arch/arm/mach-imx/include/mach/uncompress.h deleted file mode 100644 index 70523e67a8f..00000000000 --- a/arch/arm/mach-imx/include/mach/uncompress.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * arch/arm/mach-imxads/include/mach/uncompress.h - * - * - * - * Copyright (C) 1999 ARM Limited - * Copyright (C) Shane Nay (shane@minirl.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#define UART(x) (*(volatile unsigned long *)(serial_port + (x))) - -#define UART1_BASE 0x206000 -#define UART2_BASE 0x207000 -#define USR2 0x98 -#define USR2_TXFE (1<<14) -#define TXR 0x40 -#define UCR1 0x80 -#define UCR1_UARTEN 1 - -/* - * The following code assumes the serial port has already been - * initialized by the bootloader. We search for the first enabled - * port in the most probable order. If you didn't setup a port in - * your bootloader then nothing will appear (which might be desired). - * - * This does not append a newline - */ -static void putc(int c) -{ - unsigned long serial_port; - - do { - serial_port = UART1_BASE; - if ( UART(UCR1) & UCR1_UARTEN ) - break; - serial_port = UART2_BASE; - if ( UART(UCR1) & UCR1_UARTEN ) - break; - return; - } while(0); - - while (!(UART(USR2) & USR2_TXFE)) - barrier(); - - UART(TXR) = c; -} - -static inline void flush(void) -{ -} - -/* - * nothing to do - */ -#define arch_decomp_setup() - -#define arch_decomp_wdog() diff --git a/arch/arm/mach-imx/include/mach/vmalloc.h b/arch/arm/mach-imx/include/mach/vmalloc.h deleted file mode 100644 index 7d7cb0bde3e..00000000000 --- a/arch/arm/mach-imx/include/mach/vmalloc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * arch/arm/mach-imx/include/mach/vmalloc.h - * - * Copyright (C) 2000 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c deleted file mode 100644 index 531b95deadc..00000000000 --- a/arch/arm/mach-imx/irq.c +++ /dev/null @@ -1,311 +0,0 @@ -/* - * linux/arch/arm/mach-imx/irq.c - * - * Copyright (C) 1999 ARM Limited - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * 03/03/2004 Sascha Hauer <sascha@saschahauer.de> - * Copied from the motorola bsp package and added gpio demux - * interrupt handler - */ - -#include <linux/init.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <asm/irq.h> - -#include <asm/mach/irq.h> - -/* - * - * We simply use the ENABLE DISABLE registers inside of the IMX - * to turn on/off specific interrupts. - * - */ - -#define INTCNTL_OFF 0x00 -#define NIMASK_OFF 0x04 -#define INTENNUM_OFF 0x08 -#define INTDISNUM_OFF 0x0C -#define INTENABLEH_OFF 0x10 -#define INTENABLEL_OFF 0x14 -#define INTTYPEH_OFF 0x18 -#define INTTYPEL_OFF 0x1C -#define NIPRIORITY_OFF(x) (0x20+4*(7-(x))) -#define NIVECSR_OFF 0x40 -#define FIVECSR_OFF 0x44 -#define INTSRCH_OFF 0x48 -#define INTSRCL_OFF 0x4C -#define INTFRCH_OFF 0x50 -#define INTFRCL_OFF 0x54 -#define NIPNDH_OFF 0x58 -#define NIPNDL_OFF 0x5C -#define FIPNDH_OFF 0x60 -#define FIPNDL_OFF 0x64 - -#define VA_AITC_BASE IO_ADDRESS(IMX_AITC_BASE) -#define IMX_AITC_INTCNTL (VA_AITC_BASE + INTCNTL_OFF) -#define IMX_AITC_NIMASK (VA_AITC_BASE + NIMASK_OFF) -#define IMX_AITC_INTENNUM (VA_AITC_BASE + INTENNUM_OFF) -#define IMX_AITC_INTDISNUM (VA_AITC_BASE + INTDISNUM_OFF) -#define IMX_AITC_INTENABLEH (VA_AITC_BASE + INTENABLEH_OFF) -#define IMX_AITC_INTENABLEL (VA_AITC_BASE + INTENABLEL_OFF) -#define IMX_AITC_INTTYPEH (VA_AITC_BASE + INTTYPEH_OFF) -#define IMX_AITC_INTTYPEL (VA_AITC_BASE + INTTYPEL_OFF) -#define IMX_AITC_NIPRIORITY(x) (VA_AITC_BASE + NIPRIORITY_OFF(x)) -#define IMX_AITC_NIVECSR (VA_AITC_BASE + NIVECSR_OFF) -#define IMX_AITC_FIVECSR (VA_AITC_BASE + FIVECSR_OFF) -#define IMX_AITC_INTSRCH (VA_AITC_BASE + INTSRCH_OFF) -#define IMX_AITC_INTSRCL (VA_AITC_BASE + INTSRCL_OFF) -#define IMX_AITC_INTFRCH (VA_AITC_BASE + INTFRCH_OFF) -#define IMX_AITC_INTFRCL (VA_AITC_BASE + INTFRCL_OFF) -#define IMX_AITC_NIPNDH (VA_AITC_BASE + NIPNDH_OFF) -#define IMX_AITC_NIPNDL (VA_AITC_BASE + NIPNDL_OFF) -#define IMX_AITC_FIPNDH (VA_AITC_BASE + FIPNDH_OFF) -#define IMX_AITC_FIPNDL (VA_AITC_BASE + FIPNDL_OFF) - -#if 0 -#define DEBUG_IRQ(fmt...) printk(fmt) -#else -#define DEBUG_IRQ(fmt...) do { } while (0) -#endif - -static void -imx_mask_irq(unsigned int irq) -{ - __raw_writel(irq, IMX_AITC_INTDISNUM); -} - -static void -imx_unmask_irq(unsigned int irq) -{ - __raw_writel(irq, IMX_AITC_INTENNUM); -} - -#ifdef CONFIG_FIQ -int imx_set_irq_fiq(unsigned int irq, unsigned int type) -{ - unsigned int irqt; - - if (irq >= IMX_IRQS) - return -EINVAL; - - if (irq < IMX_IRQS / 2) { - irqt = __raw_readl(IMX_AITC_INTTYPEL) & ~(1 << irq); - __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEL); - } else { - irq -= IMX_IRQS / 2; - irqt = __raw_readl(IMX_AITC_INTTYPEH) & ~(1 << irq); - __raw_writel(irqt | (!!type << irq), IMX_AITC_INTTYPEH); - } - - return 0; -} -EXPORT_SYMBOL(imx_set_irq_fiq); -#endif /* CONFIG_FIQ */ - -static int -imx_gpio_irq_type(unsigned int _irq, unsigned int type) -{ - unsigned int irq_type = 0, irq, reg, bit; - - irq = _irq - IRQ_GPIOA(0); - reg = irq >> 5; - bit = 1 << (irq % 32); - - if (type == IRQ_TYPE_PROBE) { - /* Don't mess with enabled GPIOs using preconfigured edges or - GPIOs set to alternate function during probe */ - /* TODO: support probe */ -// if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx]) & -// GPIO_bit(gpio)) -// return 0; -// if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2))) -// return 0; -// type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; - } - - GIUS(reg) |= bit; - DDIR(reg) &= ~(bit); - - DEBUG_IRQ("setting type of irq %d to ", _irq); - - if (type & IRQ_TYPE_EDGE_RISING) { - DEBUG_IRQ("rising edges\n"); - irq_type = 0x0; - } - if (type & IRQ_TYPE_EDGE_FALLING) { - DEBUG_IRQ("falling edges\n"); - irq_type = 0x1; - } - if (type & IRQ_TYPE_LEVEL_LOW) { - DEBUG_IRQ("low level\n"); - irq_type = 0x3; - } - if (type & IRQ_TYPE_LEVEL_HIGH) { - DEBUG_IRQ("high level\n"); - irq_type = 0x2; - } - - if (irq % 32 < 16) { - ICR1(reg) = (ICR1(reg) & ~(0x3 << ((irq % 16) * 2))) | - (irq_type << ((irq % 16) * 2)); - } else { - ICR2(reg) = (ICR2(reg) & ~(0x3 << ((irq % 16) * 2))) | - (irq_type << ((irq % 16) * 2)); - } - - return 0; - -} - -static void -imx_gpio_ack_irq(unsigned int irq) -{ - DEBUG_IRQ("%s: irq %d\n", __func__, irq); - ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32); -} - -static void -imx_gpio_mask_irq(unsigned int irq) -{ - DEBUG_IRQ("%s: irq %d\n", __func__, irq); - IMR(IRQ_TO_REG(irq)) &= ~( 1 << ((irq - IRQ_GPIOA(0)) % 32)); -} - -static void -imx_gpio_unmask_irq(unsigned int irq) -{ - DEBUG_IRQ("%s: irq %d\n", __func__, irq); - IMR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32); -} - -static void -imx_gpio_handler(unsigned int mask, unsigned int irq, - struct irq_desc *desc) -{ - while (mask) { - if (mask & 1) { - DEBUG_IRQ("handling irq %d\n", irq); - generic_handle_irq(irq); - } - irq++; - mask >>= 1; - } -} - -static void -imx_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc) -{ - unsigned int mask, irq; - - mask = ISR(0); - irq = IRQ_GPIOA(0); - imx_gpio_handler(mask, irq, desc); -} - -static void -imx_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc) -{ - unsigned int mask, irq; - - mask = ISR(1); - irq = IRQ_GPIOB(0); - imx_gpio_handler(mask, irq, desc); -} - -static void -imx_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc) -{ - unsigned int mask, irq; - - mask = ISR(2); - irq = IRQ_GPIOC(0); - imx_gpio_handler(mask, irq, desc); -} - -static void -imx_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc) -{ - unsigned int mask, irq; - - mask = ISR(3); - irq = IRQ_GPIOD(0); - imx_gpio_handler(mask, irq, desc); -} - -static struct irq_chip imx_internal_chip = { - .name = "MPU", - .ack = imx_mask_irq, - .mask = imx_mask_irq, - .unmask = imx_unmask_irq, -}; - -static struct irq_chip imx_gpio_chip = { - .name = "GPIO", - .ack = imx_gpio_ack_irq, - .mask = imx_gpio_mask_irq, - .unmask = imx_gpio_unmask_irq, - .set_type = imx_gpio_irq_type, -}; - -void __init -imx_init_irq(void) -{ - unsigned int irq; - - DEBUG_IRQ("Initializing imx interrupts\n"); - - /* Disable all interrupts initially. */ - /* Do not rely on the bootloader. */ - __raw_writel(0, IMX_AITC_INTENABLEH); - __raw_writel(0, IMX_AITC_INTENABLEL); - - /* Mask all GPIO interrupts as well */ - IMR(0) = 0; - IMR(1) = 0; - IMR(2) = 0; - IMR(3) = 0; - - for (irq = 0; irq < IMX_IRQS; irq++) { - set_irq_chip(irq, &imx_internal_chip); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - - for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) { - set_irq_chip(irq, &imx_gpio_chip); - set_irq_handler(irq, handle_edge_irq); - set_irq_flags(irq, IRQF_VALID); - } - - set_irq_chained_handler(GPIO_INT_PORTA, imx_gpioa_demux_handler); - set_irq_chained_handler(GPIO_INT_PORTB, imx_gpiob_demux_handler); - set_irq_chained_handler(GPIO_INT_PORTC, imx_gpioc_demux_handler); - set_irq_chained_handler(GPIO_INT_PORTD, imx_gpiod_demux_handler); - - /* Release masking of interrupts according to priority */ - __raw_writel(-1, IMX_AITC_NIMASK); - -#ifdef CONFIG_FIQ - /* Initialize FIQ */ - init_FIQ(); -#endif -} diff --git a/arch/arm/mach-imx/leds-mx1ads.c b/arch/arm/mach-imx/leds-mx1ads.c deleted file mode 100644 index 1d48f2762cb..00000000000 --- a/arch/arm/mach-imx/leds-mx1ads.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * linux/arch/arm/mach-imx/leds-mx1ads.c - * - * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de> - * - * Original (leds-footbridge.c) by Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> -#include <mach/hardware.h> -#include <asm/system.h> -#include <asm/leds.h> -#include "leds.h" - -/* - * The MX1ADS Board has only one usable LED, - * so select only the timer led or the - * cpu usage led - */ -void -mx1ads_leds_event(led_event_t ledevt) -{ - unsigned long flags; - - local_irq_save(flags); - - switch (ledevt) { -#ifdef CONFIG_LEDS_CPU - case led_idle_start: - DR(0) &= ~(1<<2); - break; - - case led_idle_end: - DR(0) |= 1<<2; - break; -#endif - -#ifdef CONFIG_LEDS_TIMER - case led_timer: - DR(0) ^= 1<<2; -#endif - default: - break; - } - local_irq_restore(flags); -} diff --git a/arch/arm/mach-imx/leds.c b/arch/arm/mach-imx/leds.c deleted file mode 100644 index cf30803e019..00000000000 --- a/arch/arm/mach-imx/leds.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * linux/arch/arm/mach-imx/leds.c - * - * Copyright (C) 2004 Sascha Hauer <sascha@saschahauer.de> - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/kernel.h> -#include <linux/init.h> - -#include <asm/leds.h> -#include <asm/mach-types.h> - -#include "leds.h" - -static int __init -leds_init(void) -{ - if (machine_is_mx1ads()) { - leds_event = mx1ads_leds_event; - } - - return 0; -} - -__initcall(leds_init); diff --git a/arch/arm/mach-imx/leds.h b/arch/arm/mach-imx/leds.h deleted file mode 100644 index 49dc1c1da33..00000000000 --- a/arch/arm/mach-imx/leds.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * arch/arm/mach-imx/leds.h - * - * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de> - * - * blinky lights for IMX-based systems - * - */ -extern void mx1ads_leds_event(led_event_t evt); diff --git a/arch/arm/mach-imx/mx1ads.c b/arch/arm/mach-imx/mx1ads.c deleted file mode 100644 index 87fa1ff43b0..00000000000 --- a/arch/arm/mach-imx/mx1ads.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * arch/arm/mach-imx/mx1ads.c - * - * Initially based on: - * linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c - * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de> - * - * 2004 (c) MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/device.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <asm/system.h> -#include <mach/hardware.h> -#include <asm/irq.h> -#include <asm/pgtable.h> -#include <asm/page.h> - -#include <asm/mach/map.h> -#include <asm/mach-types.h> - -#include <asm/mach/arch.h> -#include <mach/mmc.h> -#include <mach/imx-uart.h> -#include <linux/interrupt.h> -#include "generic.h" - -static struct resource cs89x0_resources[] = { - [0] = { - .start = IMX_CS4_PHYS + 0x300, - .end = IMX_CS4_PHYS + 0x300 + 16, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_GPIOC(17), - .end = IRQ_GPIOC(17), - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device cs89x0_device = { - .name = "cirrus-cs89x0", - .num_resources = ARRAY_SIZE(cs89x0_resources), - .resource = cs89x0_resources, -}; - -static struct imxuart_platform_data uart_pdata = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct resource imx_uart1_resources[] = { - [0] = { - .start = 0x00206000, - .end = 0x002060FF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = (UART1_MINT_RX), - .end = (UART1_MINT_RX), - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = (UART1_MINT_TX), - .end = (UART1_MINT_TX), - .flags = IORESOURCE_IRQ, - }, - [3] = { - .start = UART1_MINT_RTS, - .end = UART1_MINT_RTS, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device imx_uart1_device = { - .name = "imx-uart", - .id = 0, - .num_resources = ARRAY_SIZE(imx_uart1_resources), - .resource = imx_uart1_resources, - .dev = { - .platform_data = &uart_pdata, - } -}; - -static struct resource imx_uart2_resources[] = { - [0] = { - .start = 0x00207000, - .end = 0x002070FF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = (UART2_MINT_RX), - .end = (UART2_MINT_RX), - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = (UART2_MINT_TX), - .end = (UART2_MINT_TX), - .flags = IORESOURCE_IRQ, - }, - [3] = { - .start = UART2_MINT_RTS, - .end = UART2_MINT_RTS, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device imx_uart2_device = { - .name = "imx-uart", - .id = 1, - .num_resources = ARRAY_SIZE(imx_uart2_resources), - .resource = imx_uart2_resources, - .dev = { - .platform_data = &uart_pdata, - } -}; - -static struct platform_device *devices[] __initdata = { - &cs89x0_device, - &imx_uart1_device, - &imx_uart2_device, -}; - -#if defined(CONFIG_MMC_IMX) || defined(CONFIG_MMC_IMX_MODULE) -static int mx1ads_mmc_card_present(struct device *dev) -{ - /* MMC/SD Card Detect is PB 20 on MX1ADS V1.0.7 */ - return (SSR(1) & (1 << 20) ? 0 : 1); -} - -static struct imxmmc_platform_data mx1ads_mmc_info = { - .card_present = mx1ads_mmc_card_present, -}; -#endif - -static void __init -mx1ads_init(void) -{ -#ifdef CONFIG_LEDS - imx_gpio_mode(GPIO_PORTA | GPIO_OUT | 2); -#endif -#if defined(CONFIG_MMC_IMX) || defined(CONFIG_MMC_IMX_MODULE) - /* SD/MMC card detect */ - imx_gpio_mode(GPIO_PORTB | GPIO_GIUS | GPIO_IN | 20); - imx_set_mmc_info(&mx1ads_mmc_info); -#endif - - imx_gpio_mode(PC9_PF_UART1_CTS); - imx_gpio_mode(PC10_PF_UART1_RTS); - imx_gpio_mode(PC11_PF_UART1_TXD); - imx_gpio_mode(PC12_PF_UART1_RXD); - - imx_gpio_mode(PB28_PF_UART2_CTS); - imx_gpio_mode(PB29_PF_UART2_RTS); - imx_gpio_mode(PB30_PF_UART2_TXD); - imx_gpio_mode(PB31_PF_UART2_RXD); - - platform_add_devices(devices, ARRAY_SIZE(devices)); -} - -static void __init -mx1ads_map_io(void) -{ - imx_map_io(); -} - -MACHINE_START(MX1ADS, "Motorola MX1ADS") - /* Maintainer: Sascha Hauer, Pengutronix */ - .phys_io = 0x00200000, - .io_pg_offst = ((0xe0000000) >> 18) & 0xfffc, - .boot_params = 0x08000100, - .map_io = mx1ads_map_io, - .init_irq = imx_init_irq, - .timer = &imx_timer, - .init_machine = mx1ads_init, -MACHINE_END diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c deleted file mode 100644 index 5aef18b599e..00000000000 --- a/arch/arm/mach-imx/time.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * linux/arch/arm/mach-imx/time.c - * - * Copyright (C) 2000-2001 Deep Blue Solutions - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/kernel.h> -#include <linux/sched.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/time.h> -#include <linux/clocksource.h> -#include <linux/clockchips.h> -#include <linux/clk.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <asm/leds.h> -#include <asm/irq.h> -#include <asm/mach/time.h> - -/* Use timer 1 as system timer */ -#define TIMER_BASE IMX_TIM1_BASE - -static struct clock_event_device clockevent_imx; -static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; - -/* - * IRQ handler for the timer - */ -static irqreturn_t -imx_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &clockevent_imx; - uint32_t tstat; - irqreturn_t ret = IRQ_NONE; - - /* clear the interrupt */ - tstat = IMX_TSTAT(TIMER_BASE); - IMX_TSTAT(TIMER_BASE) = 0; - - if (tstat & TSTAT_COMP) { - evt->event_handler(evt); - ret = IRQ_HANDLED; - } - - return ret; -} - -static struct irqaction imx_timer_irq = { - .name = "i.MX Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = imx_timer_interrupt, -}; - -/* - * Set up timer hardware into expected mode and state. - */ -static void __init imx_timer_hardware_init(void) -{ - /* - * Initialise to a known state (all timers off, and timing reset) - */ - IMX_TCTL(TIMER_BASE) = 0; - IMX_TPRER(TIMER_BASE) = 0; - - IMX_TCTL(TIMER_BASE) = TCTL_FRR | TCTL_CLK_PCLK1 | TCTL_TEN; -} - -cycle_t imx_get_cycles(struct clocksource *cs) -{ - return IMX_TCN(TIMER_BASE); -} - -static struct clocksource clocksource_imx = { - .name = "imx_timer1", - .rating = 200, - .read = imx_get_cycles, - .mask = 0xFFFFFFFF, - .shift = 20, - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static int __init imx_clocksource_init(unsigned long rate) -{ - clocksource_imx.mult = - clocksource_hz2mult(rate, clocksource_imx.shift); - clocksource_register(&clocksource_imx); - - return 0; -} - -static int imx_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - unsigned long tcmp; - - tcmp = IMX_TCN(TIMER_BASE) + evt; - IMX_TCMP(TIMER_BASE) = tcmp; - - return (int32_t)(tcmp - IMX_TCN(TIMER_BASE)) < 0 ? -ETIME : 0; -} - -#ifdef DEBUG -static const char *clock_event_mode_label[]={ - [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC", - [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT", - [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN", - [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED" -}; -#endif /*DEBUG*/ - -static void imx_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) -{ - unsigned long flags; - - /* - * The timer interrupt generation is disabled at least - * for enough time to call imx_set_next_event() - */ - local_irq_save(flags); - /* Disable interrupt in GPT module */ - IMX_TCTL(TIMER_BASE) &= ~TCTL_IRQEN; - if (mode != clockevent_mode) { - /* Set event time into far-far future */ - IMX_TCMP(TIMER_BASE) = IMX_TCN(TIMER_BASE) - 3; - /* Clear pending interrupt */ - IMX_TSTAT(TIMER_BASE) &= ~TSTAT_COMP; - } - -#ifdef DEBUG - printk(KERN_INFO "imx_set_mode: changing mode from %s to %s\n", - clock_event_mode_label[clockevent_mode], clock_event_mode_label[mode]); -#endif /*DEBUG*/ - - /* Remember timer mode */ - clockevent_mode = mode; - local_irq_restore(flags); - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - printk(KERN_ERR "imx_set_mode: Periodic mode is not supported for i.MX\n"); - break; - case CLOCK_EVT_MODE_ONESHOT: - /* - * Do not put overhead of interrupt enable/disable into - * imx_set_next_event(), the core has about 4 minutes - * to call imx_set_next_event() or shutdown clock after - * mode switching - */ - local_irq_save(flags); - IMX_TCTL(TIMER_BASE) |= TCTL_IRQEN; - local_irq_restore(flags); - break; - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_RESUME: - /* Left event sources disabled, no more interrupts appears */ - break; - } -} - -static struct clock_event_device clockevent_imx = { - .name = "imx_timer1", - .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, - .set_mode = imx_set_mode, - .set_next_event = imx_set_next_event, - .rating = 200, -}; - -static int __init imx_clockevent_init(unsigned long rate) -{ - clockevent_imx.mult = div_sc(rate, NSEC_PER_SEC, - clockevent_imx.shift); - clockevent_imx.max_delta_ns = - clockevent_delta2ns(0xfffffffe, &clockevent_imx); - clockevent_imx.min_delta_ns = - clockevent_delta2ns(0xf, &clockevent_imx); - - clockevent_imx.cpumask = cpumask_of(0); - - clockevents_register_device(&clockevent_imx); - - return 0; -} - -extern int imx_clocks_init(void); - -static void __init imx_timer_init(void) -{ - struct clk *clk; - unsigned long rate; - - imx_clocks_init(); - - clk = clk_get(NULL, "perclk1"); - clk_enable(clk); - rate = clk_get_rate(clk); - - imx_timer_hardware_init(); - imx_clocksource_init(rate); - - imx_clockevent_init(rate); - - /* - * Make irqs happen for the system timer - */ - setup_irq(TIM1_INT, &imx_timer_irq); -} - -struct sys_timer imx_timer = { - .init = imx_timer_init, -}; diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index 2c5a02b8520..264f4d59f89 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -78,6 +78,12 @@ config MACH_IXDP465 IXDP465 Development Platform (Also known as BMP). For more information on this platform, see <file:Documentation/arm/IXP4xx>. +config MACH_GORAMO_MLR + bool "GORAMO Multi Link Router" + help + Say 'Y' here if you want your kernel to support GORAMO + MultiLink router. + config MACH_KIXRP435 bool "KIXRP435" help diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile index 2e6bbf927a7..47d1f60d23f 100644 --- a/arch/arm/mach-ixp4xx/Makefile +++ b/arch/arm/mach-ixp4xx/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o obj-$(CONFIG_MACH_FSG) += fsg-setup.o +obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_mlr.o obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c new file mode 100644 index 00000000000..a733b8ff3ce --- /dev/null +++ b/arch/arm/mach-ixp4xx/goramo_mlr.c @@ -0,0 +1,507 @@ +/* + * Goramo MultiLink router platform code + * Copyright (C) 2006-2009 Krzysztof Halasa <khc@pm.waw.pl> + */ + +#include <linux/delay.h> +#include <linux/hdlc.h> +#include <linux/i2c-gpio.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/serial_8250.h> +#include <asm/mach-types.h> +#include <asm/system.h> +#include <asm/mach/arch.h> +#include <asm/mach/flash.h> +#include <asm/mach/pci.h> + +#define xgpio_irq(n) (IRQ_IXP4XX_GPIO ## n) +#define gpio_irq(n) xgpio_irq(n) + +#define SLOT_ETHA 0x0B /* IDSEL = AD21 */ +#define SLOT_ETHB 0x0C /* IDSEL = AD20 */ +#define SLOT_MPCI 0x0D /* IDSEL = AD19 */ +#define SLOT_NEC 0x0E /* IDSEL = AD18 */ + +#define IRQ_ETHA IRQ_IXP4XX_GPIO4 +#define IRQ_ETHB IRQ_IXP4XX_GPIO5 +#define IRQ_NEC IRQ_IXP4XX_GPIO3 +#define IRQ_MPCI IRQ_IXP4XX_GPIO12 + +/* GPIO lines */ +#define GPIO_SCL 0 +#define GPIO_SDA 1 +#define GPIO_STR 2 +#define GPIO_HSS0_DCD_N 6 +#define GPIO_HSS1_DCD_N 7 +#define GPIO_HSS0_CTS_N 10 +#define GPIO_HSS1_CTS_N 11 +#define GPIO_HSS1_RTS_N 13 +#define GPIO_HSS0_RTS_N 14 + +/* Control outputs from 74HC4094 */ +#define CONTROL_HSS0_CLK_INT 0 +#define CONTROL_HSS1_CLK_INT 1 +#define CONTROL_HSS0_DTR_N 2 +#define CONTROL_HSS1_DTR_N 3 +#define CONTROL_EXT 4 +#define CONTROL_AUTO_RESET 5 +#define CONTROL_PCI_RESET_N 6 +#define CONTROL_EEPROM_WC_N 7 + +/* offsets from start of flash ROM = 0x50000000 */ +#define CFG_ETH0_ADDRESS 0x40 /* 6 bytes */ +#define CFG_ETH1_ADDRESS 0x46 /* 6 bytes */ +#define CFG_REV 0x4C /* u32 */ +#define CFG_SDRAM_SIZE 0x50 /* u32 */ +#define CFG_SDRAM_CONF 0x54 /* u32 */ +#define CFG_SDRAM_MODE 0x58 /* u32 */ +#define CFG_SDRAM_REFRESH 0x5C /* u32 */ + +#define CFG_HW_BITS 0x60 /* u32 */ +#define CFG_HW_USB_PORTS 0x00000007 /* 0 = no NEC chip, 1-5 = ports # */ +#define CFG_HW_HAS_PCI_SLOT 0x00000008 +#define CFG_HW_HAS_ETH0 0x00000010 +#define CFG_HW_HAS_ETH1 0x00000020 +#define CFG_HW_HAS_HSS0 0x00000040 +#define CFG_HW_HAS_HSS1 0x00000080 +#define CFG_HW_HAS_UART0 0x00000100 +#define CFG_HW_HAS_UART1 0x00000200 +#define CFG_HW_HAS_EEPROM 0x00000400 + +#define FLASH_CMD_READ_ARRAY 0xFF +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_SER_OFF 0x102 /* 0x81 in 16-bit mode */ + +static u32 hw_bits = 0xFFFFFFFD; /* assume all hardware present */; +static u8 control_value; + +static void set_scl(u8 value) +{ + gpio_line_set(GPIO_SCL, !!value); + udelay(3); +} + +static void set_sda(u8 value) +{ + gpio_line_set(GPIO_SDA, !!value); + udelay(3); +} + +static void set_str(u8 value) +{ + gpio_line_set(GPIO_STR, !!value); + udelay(3); +} + +static inline void set_control(int line, int value) +{ + if (value) + control_value |= (1 << line); + else + control_value &= ~(1 << line); +} + + +static void output_control(void) +{ + int i; + + gpio_line_config(GPIO_SCL, IXP4XX_GPIO_OUT); + gpio_line_config(GPIO_SDA, IXP4XX_GPIO_OUT); + + for (i = 0; i < 8; i++) { + set_scl(0); + set_sda(control_value & (0x80 >> i)); /* MSB first */ + set_scl(1); /* active edge */ + } + + set_str(1); + set_str(0); + + set_scl(0); + set_sda(1); /* Be ready for START */ + set_scl(1); +} + + +static void (*set_carrier_cb_tab[2])(void *pdev, int carrier); + +static int hss_set_clock(int port, unsigned int clock_type) +{ + int ctrl_int = port ? CONTROL_HSS1_CLK_INT : CONTROL_HSS0_CLK_INT; + + switch (clock_type) { + case CLOCK_DEFAULT: + case CLOCK_EXT: + set_control(ctrl_int, 0); + output_control(); + return CLOCK_EXT; + + case CLOCK_INT: + set_control(ctrl_int, 1); + output_control(); + return CLOCK_INT; + + default: + return -EINVAL; + } +} + +static irqreturn_t hss_dcd_irq(int irq, void *pdev) +{ + int i, port = (irq == gpio_irq(GPIO_HSS1_DCD_N)); + gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); + set_carrier_cb_tab[port](pdev, !i); + return IRQ_HANDLED; +} + + +static int hss_open(int port, void *pdev, + void (*set_carrier_cb)(void *pdev, int carrier)) +{ + int i, irq; + + if (!port) + irq = gpio_irq(GPIO_HSS0_DCD_N); + else + irq = gpio_irq(GPIO_HSS1_DCD_N); + + gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); + set_carrier_cb(pdev, !i); + + set_carrier_cb_tab[!!port] = set_carrier_cb; + + if ((i = request_irq(irq, hss_dcd_irq, 0, "IXP4xx HSS", pdev)) != 0) { + printk(KERN_ERR "ixp4xx_hss: failed to request IRQ%i (%i)\n", + irq, i); + return i; + } + + set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0); + output_control(); + gpio_line_set(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0); + return 0; +} + +static void hss_close(int port, void *pdev) +{ + free_irq(port ? gpio_irq(GPIO_HSS1_DCD_N) : gpio_irq(GPIO_HSS0_DCD_N), + pdev); + set_carrier_cb_tab[!!port] = NULL; /* catch bugs */ + + set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1); + output_control(); + gpio_line_set(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1); +} + + +/* Flash memory */ +static struct flash_platform_data flash_data = { + .map_name = "cfi_probe", + .width = 2, +}; + +static struct resource flash_resource = { + .flags = IORESOURCE_MEM, +}; + +static struct platform_device device_flash = { + .name = "IXP4XX-Flash", + .id = 0, + .dev = { .platform_data = &flash_data }, + .num_resources = 1, + .resource = &flash_resource, +}; + + +/* I^2C interface */ +static struct i2c_gpio_platform_data i2c_data = { + .sda_pin = GPIO_SDA, + .scl_pin = GPIO_SCL, +}; + +static struct platform_device device_i2c = { + .name = "i2c-gpio", + .id = 0, + .dev = { .platform_data = &i2c_data }, +}; + + +/* IXP425 2 UART ports */ +static struct resource uart_resources[] = { + { + .start = IXP4XX_UART1_BASE_PHYS, + .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, + .flags = IORESOURCE_MEM, + }, + { + .start = IXP4XX_UART2_BASE_PHYS, + .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, + .flags = IORESOURCE_MEM, + } +}; + +static struct plat_serial8250_port uart_data[] = { + { + .mapbase = IXP4XX_UART1_BASE_PHYS, + .membase = (char __iomem *)IXP4XX_UART1_BASE_VIRT + + REG_OFFSET, + .irq = IRQ_IXP4XX_UART1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = IXP4XX_UART_XTAL, + }, + { + .mapbase = IXP4XX_UART2_BASE_PHYS, + .membase = (char __iomem *)IXP4XX_UART2_BASE_VIRT + + REG_OFFSET, + .irq = IRQ_IXP4XX_UART2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = IXP4XX_UART_XTAL, + }, + { }, +}; + +static struct platform_device device_uarts = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev.platform_data = uart_data, + .num_resources = 2, + .resource = uart_resources, +}; + + +/* Built-in 10/100 Ethernet MAC interfaces */ +static struct eth_plat_info eth_plat[] = { + { + .phy = 0, + .rxq = 3, + .txreadyq = 32, + }, { + .phy = 1, + .rxq = 4, + .txreadyq = 33, + } +}; + +static struct platform_device device_eth_tab[] = { + { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEB, + .dev.platform_data = eth_plat, + }, { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEC, + .dev.platform_data = eth_plat + 1, + } +}; + + +/* IXP425 2 synchronous serial ports */ +static struct hss_plat_info hss_plat[] = { + { + .set_clock = hss_set_clock, + .open = hss_open, + .close = hss_close, + .txreadyq = 34, + }, { + .set_clock = hss_set_clock, + .open = hss_open, + .close = hss_close, + .txreadyq = 35, + } +}; + +static struct platform_device device_hss_tab[] = { + { + .name = "ixp4xx_hss", + .id = 0, + .dev.platform_data = hss_plat, + }, { + .name = "ixp4xx_hss", + .id = 1, + .dev.platform_data = hss_plat + 1, + } +}; + + +static struct platform_device *device_tab[6] __initdata = { + &device_flash, /* index 0 */ +}; + +static inline u8 __init flash_readb(u8 __iomem *flash, u32 addr) +{ +#ifdef __ARMEB__ + return __raw_readb(flash + addr); +#else + return __raw_readb(flash + (addr ^ 3)); +#endif +} + +static inline u16 __init flash_readw(u8 __iomem *flash, u32 addr) +{ +#ifdef __ARMEB__ + return __raw_readw(flash + addr); +#else + return __raw_readw(flash + (addr ^ 2)); +#endif +} + +static void __init gmlr_init(void) +{ + u8 __iomem *flash; + int i, devices = 1; /* flash */ + + ixp4xx_sys_init(); + + if ((flash = ioremap(IXP4XX_EXP_BUS_BASE_PHYS, 0x80)) == NULL) + printk(KERN_ERR "goramo-mlr: unable to access system" + " configuration data\n"); + else { + system_rev = __raw_readl(flash + CFG_REV); + hw_bits = __raw_readl(flash + CFG_HW_BITS); + + for (i = 0; i < ETH_ALEN; i++) { + eth_plat[0].hwaddr[i] = + flash_readb(flash, CFG_ETH0_ADDRESS + i); + eth_plat[1].hwaddr[i] = + flash_readb(flash, CFG_ETH1_ADDRESS + i); + } + + __raw_writew(FLASH_CMD_READ_ID, flash); + system_serial_high = flash_readw(flash, FLASH_SER_OFF); + system_serial_high <<= 16; + system_serial_high |= flash_readw(flash, FLASH_SER_OFF + 2); + system_serial_low = flash_readw(flash, FLASH_SER_OFF + 4); + system_serial_low <<= 16; + system_serial_low |= flash_readw(flash, FLASH_SER_OFF + 6); + __raw_writew(FLASH_CMD_READ_ARRAY, flash); + + iounmap(flash); + } + + switch (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) { + case CFG_HW_HAS_UART0: + memset(&uart_data[1], 0, sizeof(uart_data[1])); + device_uarts.num_resources = 1; + break; + + case CFG_HW_HAS_UART1: + device_uarts.dev.platform_data = &uart_data[1]; + device_uarts.resource = &uart_resources[1]; + device_uarts.num_resources = 1; + break; + } + if (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) + device_tab[devices++] = &device_uarts; /* max index 1 */ + + if (hw_bits & CFG_HW_HAS_ETH0) + device_tab[devices++] = &device_eth_tab[0]; /* max index 2 */ + if (hw_bits & CFG_HW_HAS_ETH1) + device_tab[devices++] = &device_eth_tab[1]; /* max index 3 */ + + if (hw_bits & CFG_HW_HAS_HSS0) + device_tab[devices++] = &device_hss_tab[0]; /* max index 4 */ + if (hw_bits & CFG_HW_HAS_HSS1) + device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */ + + if (hw_bits & CFG_HW_HAS_EEPROM) + device_tab[devices++] = &device_i2c; /* max index 6 */ + + gpio_line_config(GPIO_SCL, IXP4XX_GPIO_OUT); + gpio_line_config(GPIO_SDA, IXP4XX_GPIO_OUT); + gpio_line_config(GPIO_STR, IXP4XX_GPIO_OUT); + gpio_line_config(GPIO_HSS0_RTS_N, IXP4XX_GPIO_OUT); + gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); + gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); + gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); + set_irq_type(gpio_irq(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); + set_irq_type(gpio_irq(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); + + set_control(CONTROL_HSS0_DTR_N, 1); + set_control(CONTROL_HSS1_DTR_N, 1); + set_control(CONTROL_EEPROM_WC_N, 1); + set_control(CONTROL_PCI_RESET_N, 1); + output_control(); + + msleep(1); /* Wait for PCI devices to initialize */ + + flash_resource.start = IXP4XX_EXP_BUS_BASE(0); + flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; + + platform_add_devices(device_tab, devices); +} + + +#ifdef CONFIG_PCI +static void __init gmlr_pci_preinit(void) +{ + set_irq_type(IRQ_ETHA, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_ETHB, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_NEC, IRQ_TYPE_LEVEL_LOW); + set_irq_type(IRQ_MPCI, IRQ_TYPE_LEVEL_LOW); + ixp4xx_pci_preinit(); +} + +static void __init gmlr_pci_postinit(void) +{ + if ((hw_bits & CFG_HW_USB_PORTS) >= 2 && + (hw_bits & CFG_HW_USB_PORTS) < 5) { + /* need to adjust number of USB ports on NEC chip */ + u32 value, addr = BIT(32 - SLOT_NEC) | 0xE0; + if (!ixp4xx_pci_read(addr, NP_CMD_CONFIGREAD, &value)) { + value &= ~7; + value |= (hw_bits & CFG_HW_USB_PORTS); + ixp4xx_pci_write(addr, NP_CMD_CONFIGWRITE, value); + } + } +} + +static int __init gmlr_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + switch(slot) { + case SLOT_ETHA: return IRQ_ETHA; + case SLOT_ETHB: return IRQ_ETHB; + case SLOT_NEC: return IRQ_NEC; + default: return IRQ_MPCI; + } +} + +static struct hw_pci gmlr_hw_pci __initdata = { + .nr_controllers = 1, + .preinit = gmlr_pci_preinit, + .postinit = gmlr_pci_postinit, + .swizzle = pci_std_swizzle, + .setup = ixp4xx_setup, + .scan = ixp4xx_scan_bus, + .map_irq = gmlr_map_irq, +}; + +static int __init gmlr_pci_init(void) +{ + if (machine_is_goramo_mlr() && + (hw_bits & (CFG_HW_USB_PORTS | CFG_HW_HAS_PCI_SLOT))) + pci_common_init(&gmlr_hw_pci); + return 0; +} + +subsys_initcall(gmlr_pci_init); +#endif /* CONFIG_PCI */ + + +MACHINE_START(GORAMO_MLR, "MultiLink") + /* Maintainer: Krzysztof Halasa */ + .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS, + .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC, + .map_io = ixp4xx_map_io, + .init_irq = ixp4xx_init_irq, + .timer = &ixp4xx_timer, + .boot_params = 0x0100, + .init_machine = gmlr_init, +MACHINE_END diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h index def7773be67..b2ef65db0e9 100644 --- a/arch/arm/mach-ixp4xx/include/mach/cpu.h +++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h @@ -26,6 +26,8 @@ #define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */ #define IXP46X_PROCESSOR_ID_MASK 0xfffffff0 +#define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \ + IXP42X_PROCESSOR_ID_VALUE) #define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \ IXP42X_PROCESSOR_ID_VALUE) #define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \ @@ -35,8 +37,11 @@ static inline u32 ixp4xx_read_feature_bits(void) { - unsigned int val = ~*IXP4XX_EXP_CFG2; + u32 val = ~*IXP4XX_EXP_CFG2; + if (cpu_is_ixp42x_rev_a0()) + return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP | + IXP4XX_FEATURE_AES); if (cpu_is_ixp42x()) return val & IXP42X_FEATURE_MASK; if (cpu_is_ixp43x()) diff --git a/arch/arm/mach-ixp4xx/include/mach/qmgr.h b/arch/arm/mach-ixp4xx/include/mach/qmgr.h index 0cbe6ceb67c..9e7cad2d54c 100644 --- a/arch/arm/mach-ixp4xx/include/mach/qmgr.h +++ b/arch/arm/mach-ixp4xx/include/mach/qmgr.h @@ -15,7 +15,7 @@ #define DEBUG_QMGR 0 #define HALF_QUEUES 32 -#define QUEUES 64 /* only 32 lower queues currently supported */ +#define QUEUES 64 #define MAX_QUEUE_LENGTH 4 /* in dwords */ #define QUEUE_STAT1_EMPTY 1 /* queue status bits */ @@ -110,48 +110,95 @@ static inline u32 qmgr_get_entry(unsigned int queue) return val; } -static inline int qmgr_get_stat1(unsigned int queue) +static inline int __qmgr_get_stat1(unsigned int queue) { extern struct qmgr_regs __iomem *qmgr_regs; return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) >> ((queue & 7) << 2)) & 0xF; } -static inline int qmgr_get_stat2(unsigned int queue) +static inline int __qmgr_get_stat2(unsigned int queue) { extern struct qmgr_regs __iomem *qmgr_regs; + BUG_ON(queue >= HALF_QUEUES); return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) >> ((queue & 0xF) << 1)) & 0x3; } +/** + * qmgr_stat_empty() - checks if a hardware queue is empty + * @queue: queue number + * + * Returns non-zero value if the queue is empty. + */ static inline int qmgr_stat_empty(unsigned int queue) { - return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY); + BUG_ON(queue >= HALF_QUEUES); + return __qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY; } -static inline int qmgr_stat_nearly_empty(unsigned int queue) +/** + * qmgr_stat_below_low_watermark() - checks if a queue is below low watermark + * @queue: queue number + * + * Returns non-zero value if the queue is below low watermark. + */ +static inline int qmgr_stat_below_low_watermark(unsigned int queue) { - return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY); + extern struct qmgr_regs __iomem *qmgr_regs; + if (queue >= HALF_QUEUES) + return (__raw_readl(&qmgr_regs->statne_h) >> + (queue - HALF_QUEUES)) & 0x01; + return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY; } -static inline int qmgr_stat_nearly_full(unsigned int queue) +/** + * qmgr_stat_above_high_watermark() - checks if a queue is above high watermark + * @queue: queue number + * + * Returns non-zero value if the queue is above high watermark + */ +static inline int qmgr_stat_above_high_watermark(unsigned int queue) { - return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL); + BUG_ON(queue >= HALF_QUEUES); + return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL; } +/** + * qmgr_stat_full() - checks if a hardware queue is full + * @queue: queue number + * + * Returns non-zero value if the queue is full. + */ static inline int qmgr_stat_full(unsigned int queue) { - return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL); + extern struct qmgr_regs __iomem *qmgr_regs; + if (queue >= HALF_QUEUES) + return (__raw_readl(&qmgr_regs->statf_h) >> + (queue - HALF_QUEUES)) & 0x01; + return __qmgr_get_stat1(queue) & QUEUE_STAT1_FULL; } +/** + * qmgr_stat_underflow() - checks if a hardware queue experienced underflow + * @queue: queue number + * + * Returns non-zero value if the queue experienced underflow. + */ static inline int qmgr_stat_underflow(unsigned int queue) { - return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW); + return __qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW; } +/** + * qmgr_stat_overflow() - checks if a hardware queue experienced overflow + * @queue: queue number + * + * Returns non-zero value if the queue experienced overflow. + */ static inline int qmgr_stat_overflow(unsigned int queue) { - return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW); + return __qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW; } #endif diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c index 7bb8e778e4b..47ac69c7ec7 100644 --- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c +++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c @@ -386,15 +386,6 @@ static int npe_reset(struct npe *npe) /* reset the NPE */ ixp4xx_write_feature_bits(val & ~(IXP4XX_FEATURE_RESET_NPEA << npe->id)); - for (i = 0; i < MAX_RETRIES; i++) { - if (!(ixp4xx_read_feature_bits() & - (IXP4XX_FEATURE_RESET_NPEA << npe->id))) - break; /* reset completed */ - udelay(1); - } - if (i == MAX_RETRIES) - return -ETIMEDOUT; - /* deassert reset */ ixp4xx_write_feature_bits(val | (IXP4XX_FEATURE_RESET_NPEA << npe->id)); diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c index bfddc73d0a2..bfdbe4b5a3c 100644 --- a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c +++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c @@ -18,8 +18,8 @@ struct qmgr_regs __iomem *qmgr_regs; static struct resource *mem_res; static spinlock_t qmgr_lock; static u32 used_sram_bitmap[4]; /* 128 16-dword pages */ -static void (*irq_handlers[HALF_QUEUES])(void *pdev); -static void *irq_pdevs[HALF_QUEUES]; +static void (*irq_handlers[QUEUES])(void *pdev); +static void *irq_pdevs[QUEUES]; #if DEBUG_QMGR char qmgr_queue_descs[QUEUES][32]; @@ -28,51 +28,112 @@ char qmgr_queue_descs[QUEUES][32]; void qmgr_set_irq(unsigned int queue, int src, void (*handler)(void *pdev), void *pdev) { - u32 __iomem *reg = &qmgr_regs->irqsrc[queue / 8]; /* 8 queues / u32 */ - int bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */ unsigned long flags; - src &= 7; spin_lock_irqsave(&qmgr_lock, flags); - __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), reg); + if (queue < HALF_QUEUES) { + u32 __iomem *reg; + int bit; + BUG_ON(src > QUEUE_IRQ_SRC_NOT_FULL); + reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */ + bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */ + __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), + reg); + } else + /* IRQ source for queues 32-63 is fixed */ + BUG_ON(src != QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY); + irq_handlers[queue] = handler; irq_pdevs[queue] = pdev; spin_unlock_irqrestore(&qmgr_lock, flags); } -static irqreturn_t qmgr_irq1(int irq, void *pdev) +static irqreturn_t qmgr_irq1_a0(int irq, void *pdev) { - int i; - u32 val = __raw_readl(&qmgr_regs->irqstat[0]); - __raw_writel(val, &qmgr_regs->irqstat[0]); /* ACK */ - - for (i = 0; i < HALF_QUEUES; i++) - if (val & (1 << i)) + int i, ret = 0; + u32 en_bitmap, src, stat; + + /* ACK - it may clear any bits so don't rely on it */ + __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[0]); + + en_bitmap = qmgr_regs->irqen[0]; + while (en_bitmap) { + i = __fls(en_bitmap); /* number of the last "low" queue */ + en_bitmap &= ~BIT(i); + src = qmgr_regs->irqsrc[i >> 3]; + stat = qmgr_regs->stat1[i >> 3]; + if (src & 4) /* the IRQ condition is inverted */ + stat = ~stat; + if (stat & BIT(src & 3)) { irq_handlers[i](irq_pdevs[i]); + ret = IRQ_HANDLED; + } + } + return ret; +} + + +static irqreturn_t qmgr_irq2_a0(int irq, void *pdev) +{ + int i, ret = 0; + u32 req_bitmap; + + /* ACK - it may clear any bits so don't rely on it */ + __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[1]); + + req_bitmap = qmgr_regs->irqen[1] & qmgr_regs->statne_h; + while (req_bitmap) { + i = __fls(req_bitmap); /* number of the last "high" queue */ + req_bitmap &= ~BIT(i); + irq_handlers[HALF_QUEUES + i](irq_pdevs[HALF_QUEUES + i]); + ret = IRQ_HANDLED; + } + return ret; +} - return val ? IRQ_HANDLED : 0; + +static irqreturn_t qmgr_irq(int irq, void *pdev) +{ + int i, half = (irq == IRQ_IXP4XX_QM1 ? 0 : 1); + u32 req_bitmap = __raw_readl(&qmgr_regs->irqstat[half]); + + if (!req_bitmap) + return 0; + __raw_writel(req_bitmap, &qmgr_regs->irqstat[half]); /* ACK */ + + while (req_bitmap) { + i = __fls(req_bitmap); /* number of the last queue */ + req_bitmap &= ~BIT(i); + i += half * HALF_QUEUES; + irq_handlers[i](irq_pdevs[i]); + } + return IRQ_HANDLED; } void qmgr_enable_irq(unsigned int queue) { unsigned long flags; + int half = queue / 32; + u32 mask = 1 << (queue & (HALF_QUEUES - 1)); spin_lock_irqsave(&qmgr_lock, flags); - __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) | (1 << queue), - &qmgr_regs->irqen[0]); + __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask, + &qmgr_regs->irqen[half]); spin_unlock_irqrestore(&qmgr_lock, flags); } void qmgr_disable_irq(unsigned int queue) { unsigned long flags; + int half = queue / 32; + u32 mask = 1 << (queue & (HALF_QUEUES - 1)); spin_lock_irqsave(&qmgr_lock, flags); - __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue), - &qmgr_regs->irqen[0]); - __raw_writel(1 << queue, &qmgr_regs->irqstat[0]); /* clear */ + __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask, + &qmgr_regs->irqen[half]); + __raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */ spin_unlock_irqrestore(&qmgr_lock, flags); } @@ -98,8 +159,7 @@ int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, u32 cfg, addr = 0, mask[4]; /* in 16-dwords */ int err; - if (queue >= HALF_QUEUES) - return -ERANGE; + BUG_ON(queue >= QUEUES); if ((nearly_empty_watermark | nearly_full_watermark) & ~7) return -EINVAL; @@ -180,7 +240,7 @@ void qmgr_release_queue(unsigned int queue) { u32 cfg, addr, mask[4]; - BUG_ON(queue >= HALF_QUEUES); /* not in valid range */ + BUG_ON(queue >= QUEUES); /* not in valid range */ spin_lock_irq(&qmgr_lock); cfg = __raw_readl(&qmgr_regs->sram[queue]); @@ -224,6 +284,8 @@ void qmgr_release_queue(unsigned int queue) static int qmgr_init(void) { int i, err; + irq_handler_t handler1, handler2; + mem_res = request_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE, "IXP4xx Queue Manager"); @@ -247,23 +309,42 @@ static int qmgr_init(void) __raw_writel(0, &qmgr_regs->irqen[i]); } + __raw_writel(0xFFFFFFFF, &qmgr_regs->statne_h); + __raw_writel(0, &qmgr_regs->statf_h); + for (i = 0; i < QUEUES; i++) __raw_writel(0, &qmgr_regs->sram[i]); - err = request_irq(IRQ_IXP4XX_QM1, qmgr_irq1, 0, - "IXP4xx Queue Manager", NULL); + if (cpu_is_ixp42x_rev_a0()) { + handler1 = qmgr_irq1_a0; + handler2 = qmgr_irq2_a0; + } else + handler1 = handler2 = qmgr_irq; + + err = request_irq(IRQ_IXP4XX_QM1, handler1, 0, "IXP4xx Queue Manager", + NULL); if (err) { - printk(KERN_ERR "qmgr: failed to request IRQ%i\n", - IRQ_IXP4XX_QM1); + printk(KERN_ERR "qmgr: failed to request IRQ%i (%i)\n", + IRQ_IXP4XX_QM1, err); goto error_irq; } + err = request_irq(IRQ_IXP4XX_QM2, handler2, 0, "IXP4xx Queue Manager", + NULL); + if (err) { + printk(KERN_ERR "qmgr: failed to request IRQ%i (%i)\n", + IRQ_IXP4XX_QM2, err); + goto error_irq2; + } + used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */ spin_lock_init(&qmgr_lock); printk(KERN_INFO "IXP4xx Queue Manager initialized.\n"); return 0; +error_irq2: + free_irq(IRQ_IXP4XX_QM1, NULL); error_irq: iounmap(qmgr_regs); error_map: @@ -274,7 +355,9 @@ error_map: static void qmgr_remove(void) { free_irq(IRQ_IXP4XX_QM1, NULL); + free_irq(IRQ_IXP4XX_QM2, NULL); synchronize_irq(IRQ_IXP4XX_QM1); + synchronize_irq(IRQ_IXP4XX_QM2); iounmap(qmgr_regs); release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE); } diff --git a/arch/arm/mach-mx1/generic.c b/arch/arm/mach-mx1/generic.c index 0dec6f300ff..7622c9b38c9 100644 --- a/arch/arm/mach-mx1/generic.c +++ b/arch/arm/mach-mx1/generic.c @@ -26,6 +26,7 @@ #include <asm/mach/map.h> +#include <mach/common.h> #include <mach/hardware.h> static struct map_desc imx_io_desc[] __initdata = { @@ -37,7 +38,9 @@ static struct map_desc imx_io_desc[] __initdata = { } }; -void __init mxc_map_io(void) +void __init mx1_map_io(void) { + mxc_set_cpu_type(MXC_CPU_MX1); + iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); } diff --git a/arch/arm/mach-mx1/mx1ads.c b/arch/arm/mach-mx1/mx1ads.c index e54057fb855..e5b0c0a83c3 100644 --- a/arch/arm/mach-mx1/mx1ads.c +++ b/arch/arm/mach-mx1/mx1ads.c @@ -12,77 +12,56 @@ * warranty of any kind, whether express or implied. */ -#include <linux/kernel.h> +#include <linux/i2c.h> +#include <linux/i2c/pcf857x.h> #include <linux/init.h> +#include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/mtd/physmap.h> -#include <linux/i2c.h> -#include <linux/i2c/pcf857x.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> -#include <mach/irqs.h> -#include <mach/hardware.h> #include <mach/common.h> -#include <mach/imx-uart.h> -#include <mach/irqs.h> +#include <mach/hardware.h> #include <mach/i2c.h> +#include <mach/imx-uart.h> #include <mach/iomux.h> +#include <mach/irqs.h> + #include "devices.h" -/* - * UARTs platform data - */ -static int mxc_uart1_pins[] = { +static int mx1ads_pins[] = { + /* UART1 */ PC9_PF_UART1_CTS, PC10_PF_UART1_RTS, PC11_PF_UART1_TXD, PC12_PF_UART1_RXD, -}; - -static int uart1_mxc_init(struct platform_device *pdev) -{ - return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, - ARRAY_SIZE(mxc_uart1_pins), "UART1"); -} - -static int uart1_mxc_exit(struct platform_device *pdev) -{ - mxc_gpio_release_multiple_pins(mxc_uart1_pins, - ARRAY_SIZE(mxc_uart1_pins)); - return 0; -} - -static int mxc_uart2_pins[] = { + /* UART2 */ PB28_PF_UART2_CTS, PB29_PF_UART2_RTS, PB30_PF_UART2_TXD, PB31_PF_UART2_RXD, + /* I2C */ + PA15_PF_I2C_SDA, + PA16_PF_I2C_SCL, + /* SPI */ + PC13_PF_SPI1_SPI_RDY, + PC14_PF_SPI1_SCLK, + PC15_PF_SPI1_SS, + PC16_PF_SPI1_MISO, + PC17_PF_SPI1_MOSI, }; -static int uart2_mxc_init(struct platform_device *pdev) -{ - return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, - ARRAY_SIZE(mxc_uart2_pins), "UART2"); -} - -static int uart2_mxc_exit(struct platform_device *pdev) -{ - mxc_gpio_release_multiple_pins(mxc_uart2_pins, - ARRAY_SIZE(mxc_uart2_pins)); - return 0; -} +/* + * UARTs platform data + */ static struct imxuart_platform_data uart_pdata[] = { { - .init = uart1_mxc_init, - .exit = uart1_mxc_exit, .flags = IMXUART_HAVE_RTSCTS, }, { - .init = uart2_mxc_init, - .exit = uart2_mxc_exit, .flags = IMXUART_HAVE_RTSCTS, }, }; @@ -111,24 +90,6 @@ static struct platform_device flash_device = { /* * I2C */ - -static int i2c_pins[] = { - PA15_PF_I2C_SDA, - PA16_PF_I2C_SCL, -}; - -static int i2c_init(struct device *dev) -{ - return mxc_gpio_setup_multiple_pins(i2c_pins, - ARRAY_SIZE(i2c_pins), "I2C"); -} - -static void i2c_exit(struct device *dev) -{ - mxc_gpio_release_multiple_pins(i2c_pins, - ARRAY_SIZE(i2c_pins)); -} - static struct pcf857x_platform_data pcf857x_data[] = { { .gpio_base = 4 * 32, @@ -139,8 +100,6 @@ static struct pcf857x_platform_data pcf857x_data[] = { static struct imxi2c_platform_data mx1ads_i2c_data = { .bitrate = 100000, - .init = i2c_init, - .exit = i2c_exit, }; static struct i2c_board_info mx1ads_i2c_devices[] = { @@ -160,6 +119,9 @@ static struct i2c_board_info mx1ads_i2c_devices[] = { */ static void __init mx1ads_init(void) { + mxc_gpio_setup_multiple_pins(mx1ads_pins, + ARRAY_SIZE(mx1ads_pins), "mx1ads"); + /* UART */ mxc_register_device(&imx_uart1_device, &uart_pdata[0]); mxc_register_device(&imx_uart2_device, &uart_pdata[1]); @@ -188,7 +150,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS") .phys_io = IMX_IO_PHYS, .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, - .map_io = mxc_map_io, + .map_io = mx1_map_io, .init_irq = mxc_init_irq, .timer = &mx1ads_timer, .init_machine = mx1ads_init, @@ -198,7 +160,7 @@ MACHINE_START(MXLADS, "Freescale MXLADS") .phys_io = IMX_IO_PHYS, .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, - .map_io = mxc_map_io, + .map_io = mx1_map_io, .init_irq = mxc_init_irq, .timer = &mx1ads_timer, .init_machine = mx1ads_init, diff --git a/arch/arm/mach-mx1/scb9328.c b/arch/arm/mach-mx1/scb9328.c index 0e71f3fa28b..20e0b5bcdff 100644 --- a/arch/arm/mach-mx1/scb9328.c +++ b/arch/arm/mach-mx1/scb9328.c @@ -153,7 +153,7 @@ MACHINE_START(SCB9328, "Synertronixx scb9328") .phys_io = 0x00200000, .io_pg_offst = ((0xe0200000) >> 18) & 0xfffc, .boot_params = 0x08000100, - .map_io = mxc_map_io, + .map_io = mx1_map_io, .init_irq = mxc_init_irq, .timer = &scb9328_timer, .init_machine = scb9328_init, diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig index 42a788842f4..61550443a23 100644 --- a/arch/arm/mach-mx2/Kconfig +++ b/arch/arm/mach-mx2/Kconfig @@ -18,6 +18,13 @@ endchoice comment "MX2 platforms:" +config MACH_MX21ADS + bool "MX21ADS platform" + depends on MACH_MX21 + help + Include support for MX21ADS platform. This includes specific + configurations for the board and its peripherals. + config MACH_MX27ADS bool "MX27ADS platform" depends on MACH_MX27 @@ -46,4 +53,10 @@ config MACH_PCM970_BASEBOARD endchoice +config MACH_MX27_3DS + bool "MX27PDK platform" + depends on MACH_MX27 + help + Include support for MX27PDK platform. This includes specific + configurations for the board and its peripherals. endif diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile index 950649a9154..d140e2dcf94 100644 --- a/arch/arm/mach-mx2/Makefile +++ b/arch/arm/mach-mx2/Makefile @@ -11,6 +11,8 @@ obj-$(CONFIG_MACH_MX21) += clock_imx21.o obj-$(CONFIG_MACH_MX27) += cpu_imx27.o obj-$(CONFIG_MACH_MX27) += clock_imx27.o +obj-$(CONFIG_MACH_MX21ADS) += mx21ads.o obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o obj-$(CONFIG_MACH_PCM038) += pcm038.o obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o +obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/generic.c index bd51dd04948..169372f69d8 100644 --- a/arch/arm/mach-mx2/generic.c +++ b/arch/arm/mach-mx2/generic.c @@ -69,7 +69,17 @@ static struct map_desc mxc_io_desc[] __initdata = { * system startup to create static physical to virtual * memory map for the IO modules. */ -void __init mxc_map_io(void) +void __init mx21_map_io(void) { + mxc_set_cpu_type(MXC_CPU_MX21); + iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); } + +void __init mx27_map_io(void) +{ + mxc_set_cpu_type(MXC_CPU_MX27); + + iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); +} + diff --git a/arch/arm/mach-mx2/mx21ads.c b/arch/arm/mach-mx2/mx21ads.c new file mode 100644 index 00000000000..a5ee461cb40 --- /dev/null +++ b/arch/arm/mach-mx2/mx21ads.c @@ -0,0 +1,286 @@ +/* + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/platform_device.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/physmap.h> +#include <linux/gpio.h> +#include <mach/common.h> +#include <mach/hardware.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/mach/map.h> +#include <mach/imx-uart.h> +#include <mach/imxfb.h> +#include <mach/iomux.h> +#include <mach/mxc_nand.h> +#include <mach/mmc.h> +#include <mach/board-mx21ads.h> + +#include "devices.h" + +static unsigned int mx21ads_pins[] = { + + /* CS8900A */ + (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11), + + /* UART1 */ + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, + + /* UART3 (IrDA) - only TXD and RXD */ + PE8_PF_UART3_TXD, + PE9_PF_UART3_RXD, + + /* UART4 */ + PB26_AF_UART4_RTS, + PB28_AF_UART4_TXD, + PB29_AF_UART4_CTS, + PB31_AF_UART4_RXD, + + /* LCDC */ + PA5_PF_LSCLK, + PA6_PF_LD0, + PA7_PF_LD1, + PA8_PF_LD2, + PA9_PF_LD3, + PA10_PF_LD4, + PA11_PF_LD5, + PA12_PF_LD6, + PA13_PF_LD7, + PA14_PF_LD8, + PA15_PF_LD9, + PA16_PF_LD10, + PA17_PF_LD11, + PA18_PF_LD12, + PA19_PF_LD13, + PA20_PF_LD14, + PA21_PF_LD15, + PA22_PF_LD16, + PA24_PF_REV, /* Sharp panel dedicated signal */ + PA25_PF_CLS, /* Sharp panel dedicated signal */ + PA26_PF_PS, /* Sharp panel dedicated signal */ + PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */ + PA28_PF_HSYNC, + PA29_PF_VSYNC, + PA30_PF_CONTRAST, + PA31_PF_OE_ACD, + + /* MMC/SDHC */ + PE18_PF_SD1_D0, + PE19_PF_SD1_D1, + PE20_PF_SD1_D2, + PE21_PF_SD1_D3, + PE22_PF_SD1_CMD, + PE23_PF_SD1_CLK, + + /* NFC */ + PF0_PF_NRFB, + PF1_PF_NFCE, + PF2_PF_NFWP, + PF3_PF_NFCLE, + PF4_PF_NFALE, + PF5_PF_NFRE, + PF6_PF_NFWE, + PF7_PF_NFIO0, + PF8_PF_NFIO1, + PF9_PF_NFIO2, + PF10_PF_NFIO3, + PF11_PF_NFIO4, + PF12_PF_NFIO5, + PF13_PF_NFIO6, + PF14_PF_NFIO7, +}; + +/* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */ +static struct physmap_flash_data mx21ads_flash_data = { + .width = 4, +}; + +static struct resource mx21ads_flash_resource = { + .start = CS0_BASE_ADDR, + .end = CS0_BASE_ADDR + 0x02000000 - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device mx21ads_nor_mtd_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &mx21ads_flash_data, + }, + .num_resources = 1, + .resource = &mx21ads_flash_resource, +}; + +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static struct imxuart_platform_data uart_norts_pdata = { +}; + + +static int mx21ads_fb_init(struct platform_device *pdev) +{ + u16 tmp; + + tmp = __raw_readw(MX21ADS_IO_REG); + tmp |= MX21ADS_IO_LCDON; + __raw_writew(tmp, MX21ADS_IO_REG); + return 0; +} + +static void mx21ads_fb_exit(struct platform_device *pdev) +{ + u16 tmp; + + tmp = __raw_readw(MX21ADS_IO_REG); + tmp &= ~MX21ADS_IO_LCDON; + __raw_writew(tmp, MX21ADS_IO_REG); +} + +/* + * Connected is a portrait Sharp-QVGA display + * of type: LQ035Q7DB02 + */ +static struct imx_fb_platform_data mx21ads_fb_data = { + .pixclock = 188679, /* in ps */ + .xres = 240, + .yres = 320, + + .bpp = 16, + .hsync_len = 2, + .left_margin = 6, + .right_margin = 16, + + .vsync_len = 1, + .upper_margin = 8, + .lower_margin = 10, + .fixed_screen_cpu = 0, + + .pcr = 0xFB108BC7, + .pwmr = 0x00A901ff, + .lscr1 = 0x00120300, + .dmacr = 0x00020008, + + .init = mx21ads_fb_init, + .exit = mx21ads_fb_exit, +}; + +static int mx21ads_sdhc_get_ro(struct device *dev) +{ + return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0; +} + +static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq, + void *data) +{ + int ret; + + ret = request_irq(IRQ_GPIOD(25), detect_irq, + IRQF_TRIGGER_FALLING, "mmc-detect", data); + if (ret) + goto out; + return 0; +out: + return ret; +} + +static void mx21ads_sdhc_exit(struct device *dev, void *data) +{ + free_irq(IRQ_GPIOD(25), data); +} + +static struct imxmmc_platform_data mx21ads_sdhc_pdata = { + .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */ + .get_ro = mx21ads_sdhc_get_ro, + .init = mx21ads_sdhc_init, + .exit = mx21ads_sdhc_exit, +}; + +static struct mxc_nand_platform_data mx21ads_nand_board_info = { + .width = 1, + .hw_ecc = 1, +}; + +static struct map_desc mx21ads_io_desc[] __initdata = { + /* + * Memory-mapped I/O on MX21ADS Base board: + * - CS8900A Ethernet controller + * - ST16C2552CJ UART + * - CPU and Base board version + * - Base board I/O register + */ + { + .virtual = MX21ADS_MMIO_BASE_ADDR, + .pfn = __phys_to_pfn(CS1_BASE_ADDR), + .length = MX21ADS_MMIO_SIZE, + .type = MT_DEVICE, + }, +}; + +static void __init mx21ads_map_io(void) +{ + mx21_map_io(); + iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc)); +} + +static struct platform_device *platform_devices[] __initdata = { + &mx21ads_nor_mtd_device, +}; + +static void __init mx21ads_board_init(void) +{ + mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins), + "mx21ads"); + + mxc_register_device(&mxc_uart_device0, &uart_pdata); + mxc_register_device(&mxc_uart_device2, &uart_norts_pdata); + mxc_register_device(&mxc_uart_device3, &uart_pdata); + mxc_register_device(&mxc_fb_device, &mx21ads_fb_data); + mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata); + mxc_register_device(&mxc_nand_device, &mx21ads_nand_board_info); + + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); +} + +static void __init mx21ads_timer_init(void) +{ + mx21_clocks_init(32768, 26000000); +} + +static struct sys_timer mx21ads_timer = { + .init = mx21ads_timer_init, +}; + +MACHINE_START(MX21ADS, "Freescale i.MX21ADS") + /* maintainer: Freescale Semiconductor, Inc. */ + .phys_io = AIPI_BASE_ADDR, + .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = mx21ads_map_io, + .init_irq = mxc_init_irq, + .init_machine = mx21ads_board_init, + .timer = &mx21ads_timer, +MACHINE_END diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c index 4a3b097adc1..02daddac699 100644 --- a/arch/arm/mach-mx2/mx27ads.c +++ b/arch/arm/mach-mx2/mx27ads.c @@ -23,6 +23,8 @@ #include <linux/mtd/map.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> +#include <linux/i2c.h> +#include <linux/irq.h> #include <mach/common.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -33,9 +35,117 @@ #include <mach/imx-uart.h> #include <mach/iomux.h> #include <mach/board-mx27ads.h> +#include <mach/mxc_nand.h> +#include <mach/i2c.h> +#include <mach/imxfb.h> +#include <mach/mmc.h> #include "devices.h" +static unsigned int mx27ads_pins[] = { + /* UART0 */ + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, + /* UART1 */ + PE3_PF_UART2_CTS, + PE4_PF_UART2_RTS, + PE6_PF_UART2_TXD, + PE7_PF_UART2_RXD, + /* UART2 */ + PE8_PF_UART3_TXD, + PE9_PF_UART3_RXD, + PE10_PF_UART3_CTS, + PE11_PF_UART3_RTS, + /* UART3 */ + PB26_AF_UART4_RTS, + PB28_AF_UART4_TXD, + PB29_AF_UART4_CTS, + PB31_AF_UART4_RXD, + /* UART4 */ + PB18_AF_UART5_TXD, + PB19_AF_UART5_RXD, + PB20_AF_UART5_CTS, + PB21_AF_UART5_RTS, + /* UART5 */ + PB10_AF_UART6_TXD, + PB12_AF_UART6_CTS, + PB11_AF_UART6_RXD, + PB13_AF_UART6_RTS, + /* FEC */ + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, + /* I2C2 */ + PC5_PF_I2C2_SDA, + PC6_PF_I2C2_SCL, + /* FB */ + PA5_PF_LSCLK, + PA6_PF_LD0, + PA7_PF_LD1, + PA8_PF_LD2, + PA9_PF_LD3, + PA10_PF_LD4, + PA11_PF_LD5, + PA12_PF_LD6, + PA13_PF_LD7, + PA14_PF_LD8, + PA15_PF_LD9, + PA16_PF_LD10, + PA17_PF_LD11, + PA18_PF_LD12, + PA19_PF_LD13, + PA20_PF_LD14, + PA21_PF_LD15, + PA22_PF_LD16, + PA23_PF_LD17, + PA24_PF_REV, + PA25_PF_CLS, + PA26_PF_PS, + PA27_PF_SPL_SPR, + PA28_PF_HSYNC, + PA29_PF_VSYNC, + PA30_PF_CONTRAST, + PA31_PF_OE_ACD, + /* OWIRE */ + PE16_AF_OWIRE, + /* SDHC1*/ + PE18_PF_SD1_D0, + PE19_PF_SD1_D1, + PE20_PF_SD1_D2, + PE21_PF_SD1_D3, + PE22_PF_SD1_CMD, + PE23_PF_SD1_CLK, + /* SDHC2*/ + PB4_PF_SD2_D0, + PB5_PF_SD2_D1, + PB6_PF_SD2_D2, + PB7_PF_SD2_D3, + PB8_PF_SD2_CMD, + PB9_PF_SD2_CLK, +}; + +static struct mxc_nand_platform_data mx27ads_nand_board_info = { + .width = 1, + .hw_ecc = 1, +}; + /* ADS's NOR flash */ static struct physmap_flash_data mx27ads_flash_data = { .width = 2, @@ -58,189 +168,113 @@ static struct platform_device mx27ads_nor_mtd_device = { .resource = &mx27ads_flash_resource, }; -static int mxc_uart0_pins[] = { - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS +static struct imxi2c_platform_data mx27ads_i2c_data = { + .bitrate = 100000, }; -static int uart_mxc_port0_init(struct platform_device *pdev) -{ - return mxc_gpio_setup_multiple_pins(mxc_uart0_pins, - ARRAY_SIZE(mxc_uart0_pins), "UART0"); -} - -static int uart_mxc_port0_exit(struct platform_device *pdev) -{ - mxc_gpio_release_multiple_pins(mxc_uart0_pins, - ARRAY_SIZE(mxc_uart0_pins)); - return 0; -} - -static int mxc_uart1_pins[] = { - PE3_PF_UART2_CTS, - PE4_PF_UART2_RTS, - PE6_PF_UART2_TXD, - PE7_PF_UART2_RXD +static struct i2c_board_info mx27ads_i2c_devices[] = { }; -static int uart_mxc_port1_init(struct platform_device *pdev) +void lcd_power(int on) { - return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, - ARRAY_SIZE(mxc_uart1_pins), "UART1"); + if (on) + __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG); + else + __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG); } -static int uart_mxc_port1_exit(struct platform_device *pdev) -{ - mxc_gpio_release_multiple_pins(mxc_uart1_pins, - ARRAY_SIZE(mxc_uart1_pins)); - return 0; -} - -static int mxc_uart2_pins[] = { - PE8_PF_UART3_TXD, - PE9_PF_UART3_RXD, - PE10_PF_UART3_CTS, - PE11_PF_UART3_RTS +static struct imx_fb_platform_data mx27ads_fb_data = { + .pixclock = 188679, + .xres = 240, + .yres = 320, + + .bpp = 16, + .hsync_len = 1, + .left_margin = 9, + .right_margin = 16, + + .vsync_len = 1, + .upper_margin = 7, + .lower_margin = 9, + .fixed_screen_cpu = 0, + + /* + * - HSYNC active high + * - VSYNC active high + * - clk notenabled while idle + * - clock inverted + * - data not inverted + * - data enable low active + * - enable sharp mode + */ + .pcr = 0xFB008BC0, + .pwmr = 0x00A903FF, + .lscr1 = 0x00120300, + .dmacr = 0x00020010, + + .lcd_power = lcd_power, }; -static int uart_mxc_port2_init(struct platform_device *pdev) +static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq, + void *data) { - return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, - ARRAY_SIZE(mxc_uart2_pins), "UART2"); + return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING, + "sdhc1-card-detect", data); } -static int uart_mxc_port2_exit(struct platform_device *pdev) +static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq, + void *data) { - mxc_gpio_release_multiple_pins(mxc_uart2_pins, - ARRAY_SIZE(mxc_uart2_pins)); - return 0; + return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING, + "sdhc2-card-detect", data); } -static int mxc_uart3_pins[] = { - PB26_AF_UART4_RTS, - PB28_AF_UART4_TXD, - PB29_AF_UART4_CTS, - PB31_AF_UART4_RXD -}; - -static int uart_mxc_port3_init(struct platform_device *pdev) +static void mx27ads_sdhc1_exit(struct device *dev, void *data) { - return mxc_gpio_setup_multiple_pins(mxc_uart3_pins, - ARRAY_SIZE(mxc_uart3_pins), "UART3"); + free_irq(IRQ_GPIOE(21), data); } -static int uart_mxc_port3_exit(struct platform_device *pdev) +static void mx27ads_sdhc2_exit(struct device *dev, void *data) { - mxc_gpio_release_multiple_pins(mxc_uart3_pins, - ARRAY_SIZE(mxc_uart3_pins)); - return 0; + free_irq(IRQ_GPIOB(7), data); } -static int mxc_uart4_pins[] = { - PB18_AF_UART5_TXD, - PB19_AF_UART5_RXD, - PB20_AF_UART5_CTS, - PB21_AF_UART5_RTS +static struct imxmmc_platform_data sdhc1_pdata = { + .init = mx27ads_sdhc1_init, + .exit = mx27ads_sdhc1_exit, }; -static int uart_mxc_port4_init(struct platform_device *pdev) -{ - return mxc_gpio_setup_multiple_pins(mxc_uart4_pins, - ARRAY_SIZE(mxc_uart4_pins), "UART4"); -} - -static int uart_mxc_port4_exit(struct platform_device *pdev) -{ - mxc_gpio_release_multiple_pins(mxc_uart4_pins, - ARRAY_SIZE(mxc_uart4_pins)); - return 0; -} - -static int mxc_uart5_pins[] = { - PB10_AF_UART6_TXD, - PB12_AF_UART6_CTS, - PB11_AF_UART6_RXD, - PB13_AF_UART6_RTS +static struct imxmmc_platform_data sdhc2_pdata = { + .init = mx27ads_sdhc2_init, + .exit = mx27ads_sdhc2_exit, }; -static int uart_mxc_port5_init(struct platform_device *pdev) -{ - return mxc_gpio_setup_multiple_pins(mxc_uart5_pins, - ARRAY_SIZE(mxc_uart5_pins), "UART5"); -} - -static int uart_mxc_port5_exit(struct platform_device *pdev) -{ - mxc_gpio_release_multiple_pins(mxc_uart5_pins, - ARRAY_SIZE(mxc_uart5_pins)); - return 0; -} - static struct platform_device *platform_devices[] __initdata = { &mx27ads_nor_mtd_device, &mxc_fec_device, + &mxc_w1_master_device, }; -static int mxc_fec_pins[] = { - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN -}; - -static void gpio_fec_active(void) -{ - mxc_gpio_setup_multiple_pins(mxc_fec_pins, - ARRAY_SIZE(mxc_fec_pins), "FEC"); -} - static struct imxuart_platform_data uart_pdata[] = { { - .init = uart_mxc_port0_init, - .exit = uart_mxc_port0_exit, .flags = IMXUART_HAVE_RTSCTS, }, { - .init = uart_mxc_port1_init, - .exit = uart_mxc_port1_exit, .flags = IMXUART_HAVE_RTSCTS, }, { - .init = uart_mxc_port2_init, - .exit = uart_mxc_port2_exit, .flags = IMXUART_HAVE_RTSCTS, }, { - .init = uart_mxc_port3_init, - .exit = uart_mxc_port3_exit, .flags = IMXUART_HAVE_RTSCTS, }, { - .init = uart_mxc_port4_init, - .exit = uart_mxc_port4_exit, .flags = IMXUART_HAVE_RTSCTS, }, { - .init = uart_mxc_port5_init, - .exit = uart_mxc_port5_exit, .flags = IMXUART_HAVE_RTSCTS, }, }; static void __init mx27ads_board_init(void) { - gpio_fec_active(); + mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins), + "mx27ads"); mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); @@ -248,6 +282,15 @@ static void __init mx27ads_board_init(void) mxc_register_device(&mxc_uart_device3, &uart_pdata[3]); mxc_register_device(&mxc_uart_device4, &uart_pdata[4]); mxc_register_device(&mxc_uart_device5, &uart_pdata[5]); + mxc_register_device(&mxc_nand_device, &mx27ads_nand_board_info); + + /* only the i2c master 1 is used on this CPU card */ + i2c_register_board_info(1, mx27ads_i2c_devices, + ARRAY_SIZE(mx27ads_i2c_devices)); + mxc_register_device(&mxc_i2c_device1, &mx27ads_i2c_data); + mxc_register_device(&mxc_fb_device, &mx27ads_fb_data); + mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); + mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } @@ -277,7 +320,7 @@ static struct map_desc mx27ads_io_desc[] __initdata = { static void __init mx27ads_map_io(void) { - mxc_map_io(); + mx27_map_io(); iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc)); } diff --git a/arch/arm/mach-mx2/mx27pdk.c b/arch/arm/mach-mx2/mx27pdk.c new file mode 100644 index 00000000000..90b1fa5d184 --- /dev/null +++ b/arch/arm/mach-mx2/mx27pdk.c @@ -0,0 +1,95 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <mach/hardware.h> +#include <mach/common.h> +#include <mach/imx-uart.h> +#include <mach/iomux.h> +#include <mach/board-mx27pdk.h> + +#include "devices.h" + +static unsigned int mx27pdk_pins[] = { + /* UART1 */ + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, + /* FEC */ + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, +}; + +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static struct platform_device *platform_devices[] __initdata = { + &mxc_fec_device, +}; + +static void __init mx27pdk_init(void) +{ + mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), + "mx27pdk"); + mxc_register_device(&mxc_uart_device0, &uart_pdata); + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); +} + +static void __init mx27pdk_timer_init(void) +{ + mx27_clocks_init(26000000); +} + +static struct sys_timer mx27pdk_timer = { + .init = mx27pdk_timer_init, +}; + +MACHINE_START(MX27_3DS, "Freescale MX27PDK") + /* maintainer: Freescale Semiconductor, Inc. */ + .phys_io = AIPI_BASE_ADDR, + .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = mxc_map_io, + .init_irq = mxc_init_irq, + .init_machine = mx27pdk_init, + .timer = &mx27pdk_timer, +MACHINE_END diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c index aa4eaa61d1b..a4628d00434 100644 --- a/arch/arm/mach-mx2/pcm038.c +++ b/arch/arm/mach-mx2/pcm038.c @@ -17,28 +17,84 @@ * MA 02110-1301, USA. */ -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/plat-ram.h> -#include <linux/io.h> #include <linux/i2c.h> #include <linux/i2c/at24.h> +#include <linux/io.h> +#include <linux/mtd/plat-ram.h> +#include <linux/mtd/physmap.h> +#include <linux/platform_device.h> -#include <asm/mach/arch.h> #include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include <mach/board-pcm038.h> #include <mach/common.h> #include <mach/hardware.h> -#include <mach/iomux.h> -#ifdef CONFIG_I2C_IMX #include <mach/i2c.h> -#endif -#include <asm/mach/time.h> +#include <mach/iomux.h> #include <mach/imx-uart.h> -#include <mach/board-pcm038.h> #include <mach/mxc_nand.h> #include "devices.h" +static int pcm038_pins[] = { + /* UART1 */ + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, + /* UART2 */ + PE3_PF_UART2_CTS, + PE4_PF_UART2_RTS, + PE6_PF_UART2_TXD, + PE7_PF_UART2_RXD, + /* UART3 */ + PE8_PF_UART3_TXD, + PE9_PF_UART3_RXD, + PE10_PF_UART3_CTS, + PE11_PF_UART3_RTS, + /* FEC */ + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, + /* I2C2 */ + PC5_PF_I2C2_SDA, + PC6_PF_I2C2_SCL, + /* SPI1 */ + PD25_PF_CSPI1_RDY, + PD27_PF_CSPI1_SS1, + PD28_PF_CSPI1_SS0, + PD29_PF_CSPI1_SCLK, + PD30_PF_CSPI1_MISO, + PD31_PF_CSPI1_MOSI, + /* SSI1 */ + PC20_PF_SSI1_FS, + PC21_PF_SSI1_RXD, + PC22_PF_SSI1_TXD, + PC23_PF_SSI1_CLK, + /* SSI4 */ + PC16_PF_SSI4_FS, + PC17_PF_SSI4_RXD, + PC18_PF_SSI4_TXD, + PC19_PF_SSI4_CLK, +}; + /* * Phytec's PCM038 comes with 2MiB battery buffered SRAM, * 16 bit width @@ -88,107 +144,16 @@ static struct platform_device pcm038_nor_mtd_device = { .resource = &pcm038_flash_resource, }; -static int mxc_uart0_pins[] = { - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS -}; - -static int uart_mxc_port0_init(struct platform_device *pdev) -{ - return mxc_gpio_setup_multiple_pins(mxc_uart0_pins, - ARRAY_SIZE(mxc_uart0_pins), "UART0"); -} - -static int uart_mxc_port0_exit(struct platform_device *pdev) -{ - mxc_gpio_release_multiple_pins(mxc_uart0_pins, - ARRAY_SIZE(mxc_uart0_pins)); - return 0; -} - -static int mxc_uart1_pins[] = { - PE3_PF_UART2_CTS, - PE4_PF_UART2_RTS, - PE6_PF_UART2_TXD, - PE7_PF_UART2_RXD -}; - -static int uart_mxc_port1_init(struct platform_device *pdev) -{ - return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, - ARRAY_SIZE(mxc_uart1_pins), "UART1"); -} - -static int uart_mxc_port1_exit(struct platform_device *pdev) -{ - mxc_gpio_release_multiple_pins(mxc_uart1_pins, - ARRAY_SIZE(mxc_uart1_pins)); - return 0; -} - -static int mxc_uart2_pins[] = { PE8_PF_UART3_TXD, - PE9_PF_UART3_RXD, - PE10_PF_UART3_CTS, - PE11_PF_UART3_RTS }; - -static int uart_mxc_port2_init(struct platform_device *pdev) -{ - return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, - ARRAY_SIZE(mxc_uart2_pins), "UART2"); -} - -static int uart_mxc_port2_exit(struct platform_device *pdev) -{ - mxc_gpio_release_multiple_pins(mxc_uart2_pins, - ARRAY_SIZE(mxc_uart2_pins)); - return 0; -} - static struct imxuart_platform_data uart_pdata[] = { { - .init = uart_mxc_port0_init, - .exit = uart_mxc_port0_exit, .flags = IMXUART_HAVE_RTSCTS, }, { - .init = uart_mxc_port1_init, - .exit = uart_mxc_port1_exit, .flags = IMXUART_HAVE_RTSCTS, }, { - .init = uart_mxc_port2_init, - .exit = uart_mxc_port2_exit, .flags = IMXUART_HAVE_RTSCTS, }, }; -static int mxc_fec_pins[] = { - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN -}; - -static void gpio_fec_active(void) -{ - mxc_gpio_setup_multiple_pins(mxc_fec_pins, - ARRAY_SIZE(mxc_fec_pins), "FEC"); -} - static struct mxc_nand_platform_data pcm038_nand_board_info = { .width = 1, .hw_ecc = 1, @@ -210,27 +175,8 @@ static void __init pcm038_init_sram(void) __raw_writel(0x22220a00, CSCR_A(1)); } -#ifdef CONFIG_I2C_IMX -static int mxc_i2c1_pins[] = { - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL -}; - -static int pcm038_i2c_1_init(struct device *dev) -{ - return mxc_gpio_setup_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins), - "I2C1"); -} - -static void pcm038_i2c_1_exit(struct device *dev) -{ - mxc_gpio_release_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins)); -} - static struct imxi2c_platform_data pcm038_i2c_1_data = { .bitrate = 100000, - .init = pcm038_i2c_1_init, - .exit = pcm038_i2c_1_exit, }; static struct at24_platform_data board_eeprom = { @@ -253,11 +199,12 @@ static struct i2c_board_info pcm038_i2c_devices[] = { .type = "lm75" } }; -#endif static void __init pcm038_init(void) { - gpio_fec_active(); + mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins), + "PCM038"); + pcm038_init_sram(); mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); @@ -267,13 +214,11 @@ static void __init pcm038_init(void) mxc_gpio_mode(PE16_AF_OWIRE); mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info); -#ifdef CONFIG_I2C_IMX /* only the i2c master 1 is used on this CPU card */ i2c_register_board_info(1, pcm038_i2c_devices, ARRAY_SIZE(pcm038_i2c_devices)); mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data); -#endif platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); @@ -295,7 +240,7 @@ MACHINE_START(PCM038, "phyCORE-i.MX27") .phys_io = AIPI_BASE_ADDR, .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, - .map_io = mxc_map_io, + .map_io = mx27_map_io, .init_irq = mxc_init_irq, .init_machine = pcm038_init, .timer = &pcm038_timer, diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c index bf4e520bc1b..6a3acaf57dd 100644 --- a/arch/arm/mach-mx2/pcm970-baseboard.c +++ b/arch/arm/mach-mx2/pcm970-baseboard.c @@ -16,71 +16,107 @@ * MA 02110-1301, USA. */ -#include <linux/platform_device.h> #include <linux/gpio.h> #include <linux/irq.h> +#include <linux/platform_device.h> #include <asm/mach/arch.h> -#include <mach/hardware.h> #include <mach/common.h> -#include <mach/mmc.h> -#include <mach/imxfb.h> #include <mach/iomux.h> +#include <mach/imxfb.h> +#include <mach/hardware.h> +#include <mach/mmc.h> #include "devices.h" -static int pcm970_sdhc2_get_ro(struct device *dev) -{ - return gpio_get_value(GPIO_PORTC + 28); -} - -static int pcm970_sdhc2_pins[] = { +static int pcm970_pins[] = { + /* SDHC */ PB4_PF_SD2_D0, PB5_PF_SD2_D1, PB6_PF_SD2_D2, PB7_PF_SD2_D3, PB8_PF_SD2_CMD, PB9_PF_SD2_CLK, + GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN, /* card detect */ + /* display */ + PA5_PF_LSCLK, + PA6_PF_LD0, + PA7_PF_LD1, + PA8_PF_LD2, + PA9_PF_LD3, + PA10_PF_LD4, + PA11_PF_LD5, + PA12_PF_LD6, + PA13_PF_LD7, + PA14_PF_LD8, + PA15_PF_LD9, + PA16_PF_LD10, + PA17_PF_LD11, + PA18_PF_LD12, + PA19_PF_LD13, + PA20_PF_LD14, + PA21_PF_LD15, + PA22_PF_LD16, + PA23_PF_LD17, + PA24_PF_REV, + PA25_PF_CLS, + PA26_PF_PS, + PA27_PF_SPL_SPR, + PA28_PF_HSYNC, + PA29_PF_VSYNC, + PA30_PF_CONTRAST, + PA31_PF_OE_ACD, + /* + * it seems the data line misses a pullup, so we must enable + * the internal pullup as a local workaround + */ + PD17_PF_I2C_DATA | GPIO_PUEN, + PD18_PF_I2C_CLK, + /* Camera */ + PB10_PF_CSI_D0, + PB11_PF_CSI_D1, + PB12_PF_CSI_D2, + PB13_PF_CSI_D3, + PB14_PF_CSI_D4, + PB15_PF_CSI_MCLK, + PB16_PF_CSI_PIXCLK, + PB17_PF_CSI_D5, + PB18_PF_CSI_D6, + PB19_PF_CSI_D7, + PB20_PF_CSI_VSYNC, + PB21_PF_CSI_HSYNC, }; +static int pcm970_sdhc2_get_ro(struct device *dev) +{ + return gpio_get_value(GPIO_PORTC + 28); +} + static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data) { int ret; - ret = mxc_gpio_setup_multiple_pins(pcm970_sdhc2_pins, - ARRAY_SIZE(pcm970_sdhc2_pins), "sdhc2"); - if(ret) - return ret; - - ret = request_irq(IRQ_GPIOC(29), detect_irq, 0, + ret = request_irq(IRQ_GPIOC(29), detect_irq, IRQF_TRIGGER_FALLING, "imx-mmc-detect", data); if (ret) - goto out_release_gpio; - - set_irq_type(IRQ_GPIOC(29), IRQF_TRIGGER_FALLING); + return ret; ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro"); - if (ret) - goto out_release_gpio; + if (ret) { + free_irq(IRQ_GPIOC(29), data); + return ret; + } - mxc_gpio_mode((GPIO_PORTC | 28) | GPIO_GPIO | GPIO_IN); gpio_direction_input(GPIO_PORTC + 28); return 0; - -out_release_gpio: - mxc_gpio_release_multiple_pins(pcm970_sdhc2_pins, - ARRAY_SIZE(pcm970_sdhc2_pins)); - return ret; } static void pcm970_sdhc2_exit(struct device *dev, void *data) { free_irq(IRQ_GPIOC(29), data); gpio_free(GPIO_PORTC + 28); - mxc_gpio_release_multiple_pins(pcm970_sdhc2_pins, - ARRAY_SIZE(pcm970_sdhc2_pins)); } static struct imxmmc_platform_data sdhc_pdata = { @@ -89,29 +125,6 @@ static struct imxmmc_platform_data sdhc_pdata = { .exit = pcm970_sdhc2_exit, }; -static int mxc_fb_pins[] = { - PA5_PF_LSCLK, PA6_PF_LD0, PA7_PF_LD1, PA8_PF_LD2, - PA9_PF_LD3, PA10_PF_LD4, PA11_PF_LD5, PA12_PF_LD6, - PA13_PF_LD7, PA14_PF_LD8, PA15_PF_LD9, PA16_PF_LD10, - PA17_PF_LD11, PA18_PF_LD12, PA19_PF_LD13, PA20_PF_LD14, - PA21_PF_LD15, PA22_PF_LD16, PA23_PF_LD17, PA24_PF_REV, - PA25_PF_CLS, PA26_PF_PS, PA27_PF_SPL_SPR, PA28_PF_HSYNC, - PA29_PF_VSYNC, PA30_PF_CONTRAST, PA31_PF_OE_ACD -}; - -static int pcm038_fb_init(struct platform_device *pdev) -{ - return mxc_gpio_setup_multiple_pins(mxc_fb_pins, - ARRAY_SIZE(mxc_fb_pins), "FB"); -} - -static int pcm038_fb_exit(struct platform_device *pdev) -{ - mxc_gpio_release_multiple_pins(mxc_fb_pins, ARRAY_SIZE(mxc_fb_pins)); - - return 0; -} - /* * Connected is a portrait Sharp-QVGA display * of type: LQ035Q7DH06 @@ -144,9 +157,6 @@ static struct imx_fb_platform_data pcm038_fb_data = { .pwmr = 0x00A903FF, .lscr1 = 0x00120300, .dmacr = 0x00020010, - - .init = pcm038_fb_init, - .exit = pcm038_fb_exit, }; /* @@ -157,6 +167,9 @@ static struct imx_fb_platform_data pcm038_fb_data = { */ void __init pcm970_baseboard_init(void) { + mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins), + "PCM970"); + mxc_register_device(&mxc_fb_device, &pcm038_fb_data); mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); } diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 194b8428bba..32e45155089 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -1,10 +1,12 @@ if ARCH_MX3 config ARCH_MX31 + select ARCH_HAS_RNGA bool config ARCH_MX35 bool + select ARCH_MXC_IOMUX_V3 comment "MX3 platforms:" @@ -66,4 +68,11 @@ config MACH_QONG Include support for Dave/DENX QongEVB-LITE platform. This includes specific configurations for the board and its peripherals. +config MACH_PCM043 + bool "Support Phytec pcm043 (i.MX35) platforms" + select ARCH_MX35 + help + Include support for Phytec pcm043 platform. This includes + specific configurations for the board and its peripherals. + endif diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 272c8a953b3..cd6547b61b1 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard.o mx31moboard-devboard.o \ mx31moboard-marxbot.o obj-$(CONFIG_MACH_QONG) += qong.o +obj-$(CONFIG_MACH_PCM043) += pcm043.o diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index 53a112d4e04..0d76521cb49 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -147,34 +147,16 @@ static struct arm_ahb_div clk_consumer[] = { { .arm = 0, .ahb = 0, .sel = 0}, }; -static struct arm_ahb_div clk_automotive[] = { - { .arm = 1, .ahb = 3, .sel = 0}, - { .arm = 1, .ahb = 2, .sel = 1}, - { .arm = 2, .ahb = 1, .sel = 1}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 1, .ahb = 6, .sel = 0}, - { .arm = 1, .ahb = 4, .sel = 1}, - { .arm = 2, .ahb = 2, .sel = 1}, - { .arm = 0, .ahb = 0, .sel = 0}, -}; - static unsigned long get_rate_arm(void) { unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0); struct arm_ahb_div *aad; unsigned long fref = get_rate_mpll(); - if (pdr0 & 1) { - /* consumer path */ - aad = &clk_consumer[(pdr0 >> 16) & 0xf]; - if (aad->sel) - fref = fref * 2 / 3; - } else { - /* auto path */ - aad = &clk_automotive[(pdr0 >> 9) & 0x7]; - if (aad->sel) - fref = fref * 3 / 4; - } + aad = &clk_consumer[(pdr0 >> 16) & 0xf]; + if (aad->sel) + fref = fref * 2 / 3; + return fref / aad->arm; } @@ -184,12 +166,7 @@ static unsigned long get_rate_ahb(struct clk *clk) struct arm_ahb_div *aad; unsigned long fref = get_rate_mpll(); - if (pdr0 & 1) - /* consumer path */ - aad = &clk_consumer[(pdr0 >> 16) & 0xf]; - else - /* auto path */ - aad = &clk_automotive[(pdr0 >> 9) & 0x7]; + aad = &clk_consumer[(pdr0 >> 16) & 0xf]; return fref / aad->ahb; } @@ -430,7 +407,8 @@ static struct clk_lookup lookups[] __initdata = { _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk) _REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk) - _REGISTER_CLOCK(NULL, "ipu", ipu_clk) + _REGISTER_CLOCK("ipu-core", NULL, ipu_clk) + _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk) _REGISTER_CLOCK(NULL, "kpp", kpp_clk) _REGISTER_CLOCK(NULL, "mlb", mlb_clk) _REGISTER_CLOCK(NULL, "mshc", mshc_clk) @@ -462,8 +440,6 @@ int __init mx35_clocks_init() int i; unsigned int ll = 0; - mxc_set_cpu_type(MXC_CPU_MX35); - #ifdef CONFIG_DEBUG_LL_CONSOLE ll = (3 << 16); #endif diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c index 9957a11533a..28bd11dc89b 100644 --- a/arch/arm/mach-mx3/clock.c +++ b/arch/arm/mach-mx3/clock.c @@ -566,8 +566,6 @@ int __init mx31_clocks_init(unsigned long fref) u32 reg; int i; - mxc_set_cpu_type(MXC_CPU_MX31); - ckih_rate = fref; for (i = 0; i < ARRAY_SIZE(lookups); i++) @@ -581,6 +579,12 @@ int __init mx31_clocks_init(unsigned long fref) MX32, but still required to be set */ MXC_CCM_CGR2); + /* + * Before turning off usb_pll make sure ipg_per_clk is generated + * by ipg_clk and not usb_pll. + */ + __raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR); + usb_pll_disable(&usb_pll_clk); pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk)); diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index 380be0c9b21..d927eddcad4 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c @@ -17,13 +17,17 @@ * Boston, MA 02110-1301, USA. */ +#include <linux/dma-mapping.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/serial.h> #include <linux/gpio.h> +#include <linux/dma-mapping.h> #include <mach/hardware.h> #include <mach/irqs.h> +#include <mach/common.h> #include <mach/imx-uart.h> +#include <mach/mx3_camera.h> #include "devices.h" @@ -283,6 +287,21 @@ struct platform_device mxcsdhc_device1 = { .num_resources = ARRAY_SIZE(mxcsdhc1_resources), .resource = mxcsdhc1_resources, }; + +static struct resource rnga_resources[] = { + { + .start = RNGA_BASE_ADDR, + .end = RNGA_BASE_ADDR + 0x28, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device mxc_rnga_device = { + .name = "mxc_rnga", + .id = -1, + .num_resources = 1, + .resource = rnga_resources, +}; #endif /* CONFIG_ARCH_MX31 */ /* i.MX31 Image Processing Unit */ @@ -329,10 +348,54 @@ struct platform_device mx3_fb = { .num_resources = ARRAY_SIZE(fb_resources), .resource = fb_resources, .dev = { - .coherent_dma_mask = 0xffffffff, + .coherent_dma_mask = DMA_BIT_MASK(32), }, }; +static struct resource camera_resources[] = { + { + .start = IPU_CTRL_BASE_ADDR + 0x60, + .end = IPU_CTRL_BASE_ADDR + 0x87, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device mx3_camera = { + .name = "mx3-camera", + .id = 0, + .num_resources = ARRAY_SIZE(camera_resources), + .resource = camera_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource otg_resources[] = { + { + .start = OTG_BASE_ADDR, + .end = OTG_BASE_ADDR + 0x1ff, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_USB3, + .end = MXC_INT_USB3, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 otg_dmamask = DMA_BIT_MASK(32); + +/* OTG gadget device */ +struct platform_device mxc_otg_udc_device = { + .name = "fsl-usb2-udc", + .id = -1, + .dev = { + .dma_mask = &otg_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), +}; + #ifdef CONFIG_ARCH_MX35 static struct resource mxc_fec_resources[] = { { @@ -359,6 +422,7 @@ static int mx3_devices_init(void) if (cpu_is_mx31()) { mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR; mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff; + mxc_register_device(&mxc_rnga_device, NULL); } if (cpu_is_mx35()) { mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR; diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h index 88c04b296fa..475410ada60 100644 --- a/arch/arm/mach-mx3/devices.h +++ b/arch/arm/mach-mx3/devices.h @@ -11,6 +11,8 @@ extern struct platform_device mxc_i2c_device1; extern struct platform_device mxc_i2c_device2; extern struct platform_device mx3_ipu; extern struct platform_device mx3_fb; +extern struct platform_device mx3_camera; extern struct platform_device mxc_fec_device; extern struct platform_device mxcsdhc_device0; extern struct platform_device mxcsdhc_device1; +extern struct platform_device mxc_otg_udc_device; diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c index 40ffc5a664d..c66ccbcdc11 100644 --- a/arch/arm/mach-mx3/iomux.c +++ b/arch/arm/mach-mx3/iomux.c @@ -21,7 +21,6 @@ #include <linux/module.h> #include <linux/spinlock.h> #include <linux/io.h> -#include <linux/gpio.h> #include <linux/kernel.h> #include <mach/hardware.h> #include <mach/gpio.h> @@ -94,15 +93,13 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config) EXPORT_SYMBOL(mxc_iomux_set_pad); /* - * setups a single pin: + * allocs a single pin: * - reserves the pin so that it is not claimed by another driver * - setups the iomux according to the configuration - * - if the pin is configured as a GPIO, we claim it through kernel gpiolib */ -int mxc_iomux_setup_pin(const unsigned int pin, const char *label) +int mxc_iomux_alloc_pin(const unsigned int pin, const char *label) { unsigned pad = pin & IOMUX_PADNUM_MASK; - unsigned gpio; if (pad >= (PIN_MAX + 1)) { printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n", @@ -113,19 +110,13 @@ int mxc_iomux_setup_pin(const unsigned int pin, const char *label) if (test_and_set_bit(pad, mxc_pin_alloc_map)) { printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n", pad, label ? label : "?"); - return -EINVAL; + return -EBUSY; } mxc_iomux_mode(pin); - /* if we have a gpio, we can allocate it */ - gpio = (pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT; - if (gpio < (GPIO_PORT_MAX + 1) * 32) - if (gpio_request(gpio, label)) - return -EINVAL; - return 0; } -EXPORT_SYMBOL(mxc_iomux_setup_pin); +EXPORT_SYMBOL(mxc_iomux_alloc_pin); int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, const char *label) @@ -135,7 +126,8 @@ int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, int ret = -EINVAL; for (i = 0; i < count; i++) { - if (mxc_iomux_setup_pin(*p, label)) + ret = mxc_iomux_alloc_pin(*p, label); + if (ret) goto setup_error; p++; } @@ -150,14 +142,9 @@ EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins); void mxc_iomux_release_pin(const unsigned int pin) { unsigned pad = pin & IOMUX_PADNUM_MASK; - unsigned gpio; if (pad < (PIN_MAX + 1)) clear_bit(pad, mxc_pin_alloc_map); - - gpio = (pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT; - if (gpio < (GPIO_PORT_MAX + 1) * 32) - gpio_free(gpio); } EXPORT_SYMBOL(mxc_iomux_release_pin); diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c index 9e1459cb4b7..1f5fdd456cb 100644 --- a/arch/arm/mach-mx3/mm.c +++ b/arch/arm/mach-mx3/mm.c @@ -72,8 +72,17 @@ static struct map_desc mxc_io_desc[] __initdata = { * system startup to create static physical to virtual memory mappings * for the IO modules. */ -void __init mxc_map_io(void) +void __init mx31_map_io(void) { + mxc_set_cpu_type(MXC_CPU_MX31); + + iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); +} + +void __init mx35_map_io(void) +{ + mxc_set_cpu_type(MXC_CPU_MX35); + iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); } diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c index a6d6efefa6a..30e2767a78a 100644 --- a/arch/arm/mach-mx3/mx31ads.c +++ b/arch/arm/mach-mx3/mx31ads.c @@ -187,7 +187,7 @@ static void __init mx31ads_init_expio(void) /* * Configure INT line as GPIO input */ - mxc_iomux_setup_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio"); + mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio"); /* disable the interrupt and clear the status */ __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); @@ -511,7 +511,7 @@ static struct map_desc mx31ads_io_desc[] __initdata = { */ static void __init mx31ads_map_io(void) { - mxc_map_io(); + mx31_map_io(); iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc)); } diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c index 894d98cd994..86fe70fa3e1 100644 --- a/arch/arm/mach-mx3/mx31lite.c +++ b/arch/arm/mach-mx3/mx31lite.c @@ -22,6 +22,9 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/memory.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/smsc911x.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -32,11 +35,64 @@ #include <asm/page.h> #include <asm/setup.h> #include <mach/board-mx31lite.h> +#include <mach/imx-uart.h> +#include <mach/iomux-mx3.h> +#include <mach/irqs.h> +#include <mach/mxc_nand.h> +#include "devices.h" /* * This file contains the board-specific initialization routines. */ +static unsigned int mx31lite_pins[] = { + /* UART1 */ + MX31_PIN_CTS1__CTS1, + MX31_PIN_RTS1__RTS1, + MX31_PIN_TXD1__TXD1, + MX31_PIN_RXD1__RXD1, + /* LAN9117 IRQ pin */ + IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), +}; + +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static struct mxc_nand_platform_data mx31lite_nand_board_info = { + .width = 1, + .hw_ecc = 1, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_16BIT, +}; + +static struct resource smsc911x_resources[] = { + [0] = { + .start = CS4_BASE_ADDR, + .end = CS4_BASE_ADDR + 0x100, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IOMUX_TO_IRQ(MX31_PIN_SFS6), + .end = IOMUX_TO_IRQ(MX31_PIN_SFS6), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + /* * This structure defines the MX31 memory map. */ @@ -59,7 +115,7 @@ static struct map_desc mx31lite_io_desc[] __initdata = { */ void __init mx31lite_map_io(void) { - mxc_map_io(); + mx31_map_io(); iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc)); } @@ -68,6 +124,22 @@ void __init mx31lite_map_io(void) */ static void __init mxc_board_init(void) { + int ret; + + mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins), + "mx31lite"); + + mxc_register_device(&mxc_uart_device0, &uart_pdata); + mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info); + + /* SMSC9117 IRQ pin */ + ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq"); + if (ret) + pr_warning("could not get LAN irq gpio\n"); + else { + gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6)); + platform_device_register(&smsc911x_device); + } } static void __init mx31lite_timer_init(void) diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c index d080b4add79..4704405165a 100644 --- a/arch/arm/mach-mx3/mx31moboard-devboard.c +++ b/arch/arm/mach-mx3/mx31moboard-devboard.c @@ -16,33 +16,142 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include <linux/types.h> +#include <linux/fsl_devices.h> +#include <linux/gpio.h> #include <linux/init.h> - +#include <linux/interrupt.h> #include <linux/platform_device.h> +#include <linux/types.h> -#include <mach/hardware.h> #include <mach/common.h> #include <mach/imx-uart.h> #include <mach/iomux-mx3.h> +#include <mach/hardware.h> +#include <mach/mmc.h> #include "devices.h" +static unsigned int devboard_pins[] = { + /* UART1 */ + MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2, + MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2, + /* SDHC2 */ + MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2, + MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0, + MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, + MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, + /* USB OTG */ + MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, + MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, + MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, + MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, + MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, + MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, + MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, + MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, + MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR, + MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP, + MX31_PIN_USB_OC__GPIO1_30, +}; + static struct imxuart_platform_data uart_pdata = { .flags = IMXUART_HAVE_RTSCTS, }; -static int mxc_uart1_pins[] = { - MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2, +#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) +#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW) + +static int devboard_sdhc2_get_ro(struct device *dev) +{ + return gpio_get_value(SDHC2_WP); +} + +static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq, + void *data) +{ + int ret; + + ret = gpio_request(SDHC2_CD, "sdhc-detect"); + if (ret) + return ret; + + gpio_direction_input(SDHC2_CD); + + ret = gpio_request(SDHC2_WP, "sdhc-wp"); + if (ret) + goto err_gpio_free; + gpio_direction_input(SDHC2_WP); + + ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "sdhc2-card-detect", data); + if (ret) + goto err_gpio_free_2; + + return 0; + +err_gpio_free_2: + gpio_free(SDHC2_WP); +err_gpio_free: + gpio_free(SDHC2_CD); + + return ret; +} + +static void devboard_sdhc2_exit(struct device *dev, void *data) +{ + free_irq(gpio_to_irq(SDHC2_CD), data); + gpio_free(SDHC2_WP); + gpio_free(SDHC2_CD); +} + +static struct imxmmc_platform_data sdhc2_pdata = { + .get_ro = devboard_sdhc2_get_ro, + .init = devboard_sdhc2_init, + .exit = devboard_sdhc2_exit, +}; + +static struct fsl_usb2_platform_data usb_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_ULPI, }; +#define OTG_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST) +#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC) + +static void devboard_usbotg_init(void) +{ + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, OTG_PAD_CFG); + + gpio_request(OTG_EN_B, "usb-udc-en"); + gpio_direction_output(OTG_EN_B, 0); +} + /* * system init for baseboard usage. Will be called by mx31moboard init. */ void __init mx31moboard_devboard_init(void) { printk(KERN_INFO "Initializing mx31devboard peripherals\n"); - mxc_iomux_setup_multiple_pins(mxc_uart1_pins, ARRAY_SIZE(mxc_uart1_pins), "uart1"); + + mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins), + "devboard"); + mxc_register_device(&mxc_uart_device1, &uart_pdata); + + mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); + + devboard_usbotg_init(); + mxc_register_device(&mxc_otg_udc_device, &usb_pdata); } diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c index 9ef9566823f..641c3d6153a 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c @@ -16,22 +16,144 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include <linux/types.h> +#include <linux/fsl_devices.h> +#include <linux/gpio.h> #include <linux/init.h> - +#include <linux/interrupt.h> #include <linux/platform_device.h> +#include <linux/types.h> -#include <mach/hardware.h> #include <mach/common.h> +#include <mach/hardware.h> #include <mach/imx-uart.h> #include <mach/iomux-mx3.h> +#include <mach/mmc.h> #include "devices.h" +static unsigned int marxbot_pins[] = { + /* SDHC2 */ + MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2, + MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0, + MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, + MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, + /* CSI */ + MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5, + MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7, + MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9, + MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11, + MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13, + MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15, + MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK, + MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC, + MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1, + MX31_PIN_TXD2__GPIO1_28, + /* USB OTG */ + MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, + MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, + MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, + MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, + MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, + MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, + MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, + MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, + MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR, + MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP, + MX31_PIN_USB_OC__GPIO1_30, +}; + +#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) +#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW) + +static int marxbot_sdhc2_get_ro(struct device *dev) +{ + return gpio_get_value(SDHC2_WP); +} + +static int marxbot_sdhc2_init(struct device *dev, irq_handler_t detect_irq, + void *data) +{ + int ret; + + ret = gpio_request(SDHC2_CD, "sdhc-detect"); + if (ret) + return ret; + + gpio_direction_input(SDHC2_CD); + + ret = gpio_request(SDHC2_WP, "sdhc-wp"); + if (ret) + goto err_gpio_free; + gpio_direction_input(SDHC2_WP); + + ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "sdhc2-card-detect", data); + if (ret) + goto err_gpio_free_2; + + return 0; + +err_gpio_free_2: + gpio_free(SDHC2_WP); +err_gpio_free: + gpio_free(SDHC2_CD); + + return ret; +} + +static void marxbot_sdhc2_exit(struct device *dev, void *data) +{ + free_irq(gpio_to_irq(SDHC2_CD), data); + gpio_free(SDHC2_WP); + gpio_free(SDHC2_CD); +} + +static struct imxmmc_platform_data sdhc2_pdata = { + .get_ro = marxbot_sdhc2_get_ro, + .init = marxbot_sdhc2_init, + .exit = marxbot_sdhc2_exit, +}; + +static struct fsl_usb2_platform_data usb_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_ULPI, +}; + +#define OTG_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST) +#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC) + +static void marxbot_usbotg_init(void) +{ + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, OTG_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, OTG_PAD_CFG); + + gpio_request(OTG_EN_B, "usb-udc-en"); + gpio_direction_output(OTG_EN_B, 0); +} + /* * system init for baseboard usage. Will be called by mx31moboard init. */ void __init mx31moboard_marxbot_init(void) { printk(KERN_INFO "Initializing mx31marxbot peripherals\n"); + + mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins), + "marxbot"); + + mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); + + marxbot_usbotg_init(); + mxc_register_device(&mxc_otg_udc_device, &usb_pdata); } diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c index 34c2a1b99d4..a17f2e41160 100644 --- a/arch/arm/mach-mx3/mx31moboard.c +++ b/arch/arm/mach-mx3/mx31moboard.c @@ -16,26 +16,47 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include <linux/types.h> +#include <linux/gpio.h> #include <linux/init.h> - -#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/memory.h> #include <linux/mtd/physmap.h> #include <linux/mtd/partitions.h> -#include <linux/memory.h> +#include <linux/platform_device.h> +#include <linux/types.h> -#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/mach/map.h> +#include <mach/board-mx31moboard.h> #include <mach/common.h> +#include <mach/hardware.h> #include <mach/imx-uart.h> #include <mach/iomux-mx3.h> -#include <mach/board-mx31moboard.h> +#include <mach/i2c.h> +#include <mach/mmc.h> #include "devices.h" +static unsigned int moboard_pins[] = { + /* UART0 */ + MX31_PIN_CTS1__CTS1, MX31_PIN_RTS1__RTS1, + MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1, + /* UART4 */ + MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5, + MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5, + /* I2C0 */ + MX31_PIN_I2C_DAT__I2C1_SDA, MX31_PIN_I2C_CLK__I2C1_SCL, + /* I2C1 */ + MX31_PIN_DCD_DTE1__I2C2_SDA, MX31_PIN_RI_DTE1__I2C2_SCL, + /* SDHC1 */ + MX31_PIN_SD1_DATA3__SD1_DATA3, MX31_PIN_SD1_DATA2__SD1_DATA2, + MX31_PIN_SD1_DATA1__SD1_DATA1, MX31_PIN_SD1_DATA0__SD1_DATA0, + MX31_PIN_SD1_CLK__SD1_CLK, MX31_PIN_SD1_CMD__SD1_CMD, + MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27, +}; + static struct physmap_flash_data mx31moboard_flash_data = { .width = 2, }; @@ -60,17 +81,69 @@ static struct imxuart_platform_data uart_pdata = { .flags = IMXUART_HAVE_RTSCTS, }; -static struct platform_device *devices[] __initdata = { - &mx31moboard_flash, +static struct imxi2c_platform_data moboard_i2c0_pdata = { + .bitrate = 400000, }; -static int mxc_uart0_pins[] = { - MX31_PIN_CTS1__CTS1, MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1, +static struct imxi2c_platform_data moboard_i2c1_pdata = { + .bitrate = 100000, }; -static int mxc_uart4_pins[] = { - MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5, - MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5, + +#define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0) +#define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1) + +static int moboard_sdhc1_get_ro(struct device *dev) +{ + return gpio_get_value(SDHC1_WP); +} + +static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq, + void *data) +{ + int ret; + + ret = gpio_request(SDHC1_CD, "sdhc-detect"); + if (ret) + return ret; + + gpio_direction_input(SDHC1_CD); + + ret = gpio_request(SDHC1_WP, "sdhc-wp"); + if (ret) + goto err_gpio_free; + gpio_direction_input(SDHC1_WP); + + ret = request_irq(gpio_to_irq(SDHC1_CD), detect_irq, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "sdhc1-card-detect", data); + if (ret) + goto err_gpio_free_2; + + return 0; + +err_gpio_free_2: + gpio_free(SDHC1_WP); +err_gpio_free: + gpio_free(SDHC1_CD); + + return ret; +} + +static void moboard_sdhc1_exit(struct device *dev, void *data) +{ + free_irq(gpio_to_irq(SDHC1_CD), data); + gpio_free(SDHC1_WP); + gpio_free(SDHC1_CD); +} + +static struct imxmmc_platform_data sdhc1_pdata = { + .get_ro = moboard_sdhc1_get_ro, + .init = moboard_sdhc1_init, + .exit = moboard_sdhc1_exit, +}; + +static struct platform_device *devices[] __initdata = { + &mx31moboard_flash, }; static int mx31moboard_baseboard; @@ -81,14 +154,19 @@ core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444); */ static void __init mxc_board_init(void) { + mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins), + "moboard"); + platform_add_devices(devices, ARRAY_SIZE(devices)); - mxc_iomux_setup_multiple_pins(mxc_uart0_pins, ARRAY_SIZE(mxc_uart0_pins), "uart0"); mxc_register_device(&mxc_uart_device0, &uart_pdata); - - mxc_iomux_setup_multiple_pins(mxc_uart4_pins, ARRAY_SIZE(mxc_uart4_pins), "uart4"); mxc_register_device(&mxc_uart_device4, &uart_pdata); + mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata); + mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata); + + mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata); + switch (mx31moboard_baseboard) { case MX31NOBOARD: break; @@ -99,7 +177,8 @@ static void __init mxc_board_init(void) mx31moboard_marxbot_init(); break; default: - printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", mx31moboard_baseboard); + printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", + mx31moboard_baseboard); } } @@ -117,7 +196,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") .phys_io = AIPS1_BASE_ADDR, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, - .map_io = mxc_map_io, + .map_io = mx31_map_io, .init_irq = mxc_init_irq, .init_machine = mxc_board_init, .timer = &mx31moboard_timer, diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mx31pdk.c index bc63f178569..32599e50753 100644 --- a/arch/arm/mach-mx3/mx31pdk.c +++ b/arch/arm/mach-mx3/mx31pdk.c @@ -20,6 +20,7 @@ #include <linux/init.h> #include <linux/clk.h> #include <linux/irq.h> +#include <linux/gpio.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -41,21 +42,159 @@ * @ingroup System */ +static int mx31pdk_pins[] = { + /* UART1 */ + MX31_PIN_CTS1__CTS1, + MX31_PIN_RTS1__RTS1, + MX31_PIN_TXD1__TXD1, + MX31_PIN_RXD1__RXD1, + IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), +}; + static struct imxuart_platform_data uart_pdata = { .flags = IMXUART_HAVE_RTSCTS, }; -static int uart_pins[] = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1 +/* + * Routines for the CPLD on the debug board. It contains a CPLD handling + * LEDs, switches, interrupts for Ethernet. + */ + +static void mx31pdk_expio_irq_handler(uint32_t irq, struct irq_desc *desc) +{ + uint32_t imr_val; + uint32_t int_valid; + uint32_t expio_irq; + + imr_val = __raw_readw(CPLD_INT_MASK_REG); + int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val; + + expio_irq = MXC_EXP_IO_BASE; + for (; int_valid != 0; int_valid >>= 1, expio_irq++) { + if ((int_valid & 1) == 0) + continue; + generic_handle_irq(expio_irq); + } +} + +/* + * Disable an expio pin's interrupt by setting the bit in the imr. + * @param irq an expio virtual irq number + */ +static void expio_mask_irq(uint32_t irq) +{ + uint16_t reg; + uint32_t expio = MXC_IRQ_TO_EXPIO(irq); + + /* mask the interrupt */ + reg = __raw_readw(CPLD_INT_MASK_REG); + reg |= 1 << expio; + __raw_writew(reg, CPLD_INT_MASK_REG); +} + +/* + * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. + * @param irq an expanded io virtual irq number + */ +static void expio_ack_irq(uint32_t irq) +{ + uint32_t expio = MXC_IRQ_TO_EXPIO(irq); + + /* clear the interrupt status */ + __raw_writew(1 << expio, CPLD_INT_RESET_REG); + __raw_writew(0, CPLD_INT_RESET_REG); + /* mask the interrupt */ + expio_mask_irq(irq); +} + +/* + * Enable a expio pin's interrupt by clearing the bit in the imr. + * @param irq a expio virtual irq number + */ +static void expio_unmask_irq(uint32_t irq) +{ + uint16_t reg; + uint32_t expio = MXC_IRQ_TO_EXPIO(irq); + + /* unmask the interrupt */ + reg = __raw_readw(CPLD_INT_MASK_REG); + reg &= ~(1 << expio); + __raw_writew(reg, CPLD_INT_MASK_REG); +} + +static struct irq_chip expio_irq_chip = { + .ack = expio_ack_irq, + .mask = expio_mask_irq, + .unmask = expio_unmask_irq, }; -static inline void mxc_init_imx_uart(void) +static int __init mx31pdk_init_expio(void) { - mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + int i; + int ret; + + /* Check if there's a debug board connected */ + if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) || + (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) || + (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) { + /* No Debug board found */ + return -ENODEV; + } + + pr_info("i.MX31PDK Debug board detected, rev = 0x%04X\n", + __raw_readw(CPLD_CODE_VER_REG)); + + /* + * Configure INT line as GPIO input + */ + ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq"); + if (ret) + pr_warning("could not get LAN irq gpio\n"); + else + gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); + + /* Disable the interrupts and clear the status */ + __raw_writew(0, CPLD_INT_MASK_REG); + __raw_writew(0xFFFF, CPLD_INT_RESET_REG); + __raw_writew(0, CPLD_INT_RESET_REG); + __raw_writew(0x1F, CPLD_INT_MASK_REG); + for (i = MXC_EXP_IO_BASE; + i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); + i++) { + set_irq_chip(i, &expio_irq_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW); + set_irq_chained_handler(EXPIO_PARENT_INT, mx31pdk_expio_irq_handler); + + return 0; +} + +/* + * This structure defines the MX31 memory map. + */ +static struct map_desc mx31pdk_io_desc[] __initdata = { + { + .virtual = SPBA0_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), + .length = SPBA0_SIZE, + .type = MT_DEVICE_NONSHARED, + }, { + .virtual = CS5_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(CS5_BASE_ADDR), + .length = CS5_SIZE, + .type = MT_DEVICE, + }, +}; + +/* + * Set up static virtual mappings. + */ +static void __init mx31pdk_map_io(void) +{ + mx31_map_io(); + iotable_init(mx31pdk_io_desc, ARRAY_SIZE(mx31pdk_io_desc)); } /*! @@ -63,7 +202,12 @@ static inline void mxc_init_imx_uart(void) */ static void __init mxc_board_init(void) { - mxc_init_imx_uart(); + mxc_iomux_setup_multiple_pins(mx31pdk_pins, ARRAY_SIZE(mx31pdk_pins), + "mx31pdk"); + + mxc_register_device(&mxc_uart_device0, &uart_pdata); + + mx31pdk_init_expio(); } static void __init mx31pdk_timer_init(void) @@ -84,7 +228,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") .phys_io = AIPS1_BASE_ADDR, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, - .map_io = mxc_map_io, + .map_io = mx31pdk_map_io, .init_irq = mxc_init_irq, .init_machine = mxc_board_init, .timer = &mx31pdk_timer, diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c index b5227d837b2..c6f61a1f06c 100644 --- a/arch/arm/mach-mx3/pcm037.c +++ b/arch/arm/mach-mx3/pcm037.c @@ -28,6 +28,10 @@ #include <linux/interrupt.h> #include <linux/i2c.h> #include <linux/i2c/at24.h> +#include <linux/delay.h> +#include <linux/spi/spi.h> +#include <linux/irq.h> +#include <linux/fsl_devices.h> #include <mach/hardware.h> #include <asm/mach-types.h> @@ -37,7 +41,9 @@ #include <mach/common.h> #include <mach/imx-uart.h> #include <mach/iomux-mx3.h> +#include <mach/ipu.h> #include <mach/board-pcm037.h> +#include <mach/mx3fb.h> #include <mach/mxc_nand.h> #include <mach/mmc.h> #ifdef CONFIG_I2C_IMX @@ -46,6 +52,76 @@ #include "devices.h" +static unsigned int pcm037_pins[] = { + /* I2C */ + MX31_PIN_CSPI2_MOSI__SCL, + MX31_PIN_CSPI2_MISO__SDA, + /* SDHC1 */ + MX31_PIN_SD1_DATA3__SD1_DATA3, + MX31_PIN_SD1_DATA2__SD1_DATA2, + MX31_PIN_SD1_DATA1__SD1_DATA1, + MX31_PIN_SD1_DATA0__SD1_DATA0, + MX31_PIN_SD1_CLK__SD1_CLK, + MX31_PIN_SD1_CMD__SD1_CMD, + IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */ + IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */ + /* SPI1 */ + MX31_PIN_CSPI1_MOSI__MOSI, + MX31_PIN_CSPI1_MISO__MISO, + MX31_PIN_CSPI1_SCLK__SCLK, + MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, + MX31_PIN_CSPI1_SS0__SS0, + MX31_PIN_CSPI1_SS1__SS1, + MX31_PIN_CSPI1_SS2__SS2, + /* UART1 */ + MX31_PIN_CTS1__CTS1, + MX31_PIN_RTS1__RTS1, + MX31_PIN_TXD1__TXD1, + MX31_PIN_RXD1__RXD1, + /* UART2 */ + MX31_PIN_TXD2__TXD2, + MX31_PIN_RXD2__RXD2, + MX31_PIN_CTS2__CTS2, + MX31_PIN_RTS2__RTS2, + /* UART3 */ + MX31_PIN_CSPI3_MOSI__RXD3, + MX31_PIN_CSPI3_MISO__TXD3, + MX31_PIN_CSPI3_SCLK__RTS3, + MX31_PIN_CSPI3_SPI_RDY__CTS3, + /* LAN9217 irq pin */ + IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO), + /* Onewire */ + MX31_PIN_BATT_LINE__OWIRE, + /* Framebuffer */ + MX31_PIN_LD0__LD0, + MX31_PIN_LD1__LD1, + MX31_PIN_LD2__LD2, + MX31_PIN_LD3__LD3, + MX31_PIN_LD4__LD4, + MX31_PIN_LD5__LD5, + MX31_PIN_LD6__LD6, + MX31_PIN_LD7__LD7, + MX31_PIN_LD8__LD8, + MX31_PIN_LD9__LD9, + MX31_PIN_LD10__LD10, + MX31_PIN_LD11__LD11, + MX31_PIN_LD12__LD12, + MX31_PIN_LD13__LD13, + MX31_PIN_LD14__LD14, + MX31_PIN_LD15__LD15, + MX31_PIN_LD16__LD16, + MX31_PIN_LD17__LD17, + MX31_PIN_VSYNC3__VSYNC3, + MX31_PIN_HSYNC__HSYNC, + MX31_PIN_FPSHIFT__FPSHIFT, + MX31_PIN_DRDY0__DRDY0, + MX31_PIN_D3_REV__D3_REV, + MX31_PIN_CONTRAST__CONTRAST, + MX31_PIN_D3_SPL__D3_SPL, + MX31_PIN_D3_CLS__D3_CLS, + MX31_PIN_LCS0__GPI03_23, +}; + static struct physmap_flash_data pcm037_flash_data = { .width = 2, }; @@ -56,6 +132,54 @@ static struct resource pcm037_flash_resource = { .flags = IORESOURCE_MEM, }; +static int usbotg_pins[] = { + MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, + MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, + MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, + MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, + MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, + MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, + MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, + MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, + MX31_PIN_USBOTG_CLK__USBOTG_CLK, + MX31_PIN_USBOTG_DIR__USBOTG_DIR, + MX31_PIN_USBOTG_NXT__USBOTG_NXT, + MX31_PIN_USBOTG_STP__USBOTG_STP, +}; + +/* USB OTG HS port */ +static int __init gpio_usbotg_hs_activate(void) +{ + int ret = mxc_iomux_setup_multiple_pins(usbotg_pins, + ARRAY_SIZE(usbotg_pins), "usbotg"); + + if (ret < 0) { + printk(KERN_ERR "Cannot set up OTG pins\n"); + return ret; + } + + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + return 0; +} + +/* OTG config */ +static struct fsl_usb2_platform_data usb_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_ULPI, +}; + static struct platform_device pcm037_flash = { .name = "physmap-flash", .id = 0, @@ -127,26 +251,8 @@ static struct mxc_nand_platform_data pcm037_nand_board_info = { }; #ifdef CONFIG_I2C_IMX -static int i2c_1_pins[] = { - MX31_PIN_CSPI2_MOSI__SCL, - MX31_PIN_CSPI2_MISO__SDA, -}; - -static int pcm037_i2c_1_init(struct device *dev) -{ - return mxc_iomux_setup_multiple_pins(i2c_1_pins, ARRAY_SIZE(i2c_1_pins), - "i2c-1"); -} - -static void pcm037_i2c_1_exit(struct device *dev) -{ - mxc_iomux_release_multiple_pins(i2c_1_pins, ARRAY_SIZE(i2c_1_pins)); -} - static struct imxi2c_platform_data pcm037_i2c_1_data = { .bitrate = 100000, - .init = pcm037_i2c_1_init, - .exit = pcm037_i2c_1_exit, }; static struct at24_platform_data board_eeprom = { @@ -166,48 +272,119 @@ static struct i2c_board_info pcm037_i2c_devices[] = { }; #endif -static int sdhc1_pins[] = { - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, -}; +/* Not connected by default */ +#ifdef PCM970_SDHC_RW_SWITCH +static int pcm970_sdhc1_get_ro(struct device *dev) +{ + return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6)); +} +#endif + +#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6) +#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6) -static int pcm970_sdhc1_init(struct device *dev, irq_handler_t h, void *data) +static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq, + void *data) { - return mxc_iomux_setup_multiple_pins(sdhc1_pins, ARRAY_SIZE(sdhc1_pins), - "sdhc-1"); + int ret; + + ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect"); + if (ret) + return ret; + + gpio_direction_input(SDHC1_GPIO_DET); + +#ifdef PCM970_SDHC_RW_SWITCH + ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp"); + if (ret) + goto err_gpio_free; + gpio_direction_input(SDHC1_GPIO_WP); +#endif + + ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq, + IRQF_DISABLED | IRQF_TRIGGER_FALLING, + "sdhc-detect", data); + if (ret) + goto err_gpio_free_2; + + return 0; + +err_gpio_free_2: +#ifdef PCM970_SDHC_RW_SWITCH + gpio_free(SDHC1_GPIO_WP); +err_gpio_free: +#endif + gpio_free(SDHC1_GPIO_DET); + + return ret; } static void pcm970_sdhc1_exit(struct device *dev, void *data) { - mxc_iomux_release_multiple_pins(sdhc1_pins, ARRAY_SIZE(sdhc1_pins)); + free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data); + gpio_free(SDHC1_GPIO_DET); + gpio_free(SDHC1_GPIO_WP); } -/* No card and rw detection at the moment */ static struct imxmmc_platform_data sdhc_pdata = { +#ifdef PCM970_SDHC_RW_SWITCH + .get_ro = pcm970_sdhc1_get_ro, +#endif .init = pcm970_sdhc1_init, .exit = pcm970_sdhc1_exit, }; static struct platform_device *devices[] __initdata = { &pcm037_flash, - &pcm037_eth, &pcm037_sram_device, }; -static int uart0_pins[] = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1 +static struct ipu_platform_data mx3_ipu_data = { + .irq_base = MXC_IPU_IRQ_START, }; -static int uart2_pins[] = { - MX31_PIN_CSPI3_MOSI__RXD3, - MX31_PIN_CSPI3_MISO__TXD3 +static const struct fb_videomode fb_modedb[] = { + { + /* 240x320 @ 60 Hz Sharp */ + .name = "Sharp-LQ035Q7DH06-QVGA", + .refresh = 60, + .xres = 240, + .yres = 320, + .pixclock = 185925, + .left_margin = 9, + .right_margin = 16, + .upper_margin = 7, + .lower_margin = 9, + .hsync_len = 1, + .vsync_len = 1, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | + FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, { + /* 240x320 @ 60 Hz */ + .name = "TX090", + .refresh = 60, + .xres = 240, + .yres = 320, + .pixclock = 38255, + .left_margin = 144, + .right_margin = 0, + .upper_margin = 7, + .lower_margin = 40, + .hsync_len = 96, + .vsync_len = 1, + .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, +}; + +static struct mx3fb_platform_data mx3fb_pdata = { + .dma_dev = &mx3_ipu.dev, + .name = "Sharp-LQ035Q7DH06-QVGA", + .mode = fb_modedb, + .num_modes = ARRAY_SIZE(fb_modedb), }; /* @@ -215,21 +392,28 @@ static int uart2_pins[] = { */ static void __init mxc_board_init(void) { + int ret; + + mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins), + "pcm037"); + platform_add_devices(devices, ARRAY_SIZE(devices)); - mxc_iomux_setup_multiple_pins(uart0_pins, ARRAY_SIZE(uart0_pins), "uart-0"); mxc_register_device(&mxc_uart_device0, &uart_pdata); - - mxc_iomux_setup_multiple_pins(uart2_pins, ARRAY_SIZE(uart2_pins), "uart-2"); + mxc_register_device(&mxc_uart_device1, &uart_pdata); mxc_register_device(&mxc_uart_device2, &uart_pdata); - mxc_iomux_setup_pin(MX31_PIN_BATT_LINE__OWIRE, "batt-0wire"); mxc_register_device(&mxc_w1_master_device, NULL); /* LAN9217 IRQ pin */ - if (!mxc_iomux_setup_pin(IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO), - "pcm037-eth")) + ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); + if (ret) + pr_warning("could not get LAN irq gpio\n"); + else { gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)); + platform_device_register(&pcm037_eth); + } + #ifdef CONFIG_I2C_IMX i2c_register_board_info(1, pcm037_i2c_devices, @@ -239,6 +423,10 @@ static void __init mxc_board_init(void) #endif mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); + mxc_register_device(&mx3_ipu, &mx3_ipu_data); + mxc_register_device(&mx3_fb, &mx3fb_pdata); + if (!gpio_usbotg_hs_activate()) + mxc_register_device(&mxc_otg_udc_device, &usb_pdata); } static void __init pcm037_timer_init(void) @@ -255,7 +443,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037") .phys_io = AIPS1_BASE_ADDR, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, - .map_io = mxc_map_io, + .map_io = mx31_map_io, .init_irq = mxc_init_irq, .init_machine = mxc_board_init, .timer = &pcm037_timer, diff --git a/arch/arm/mach-mx3/pcm043.c b/arch/arm/mach-mx3/pcm043.c new file mode 100644 index 00000000000..8d27c324abf --- /dev/null +++ b/arch/arm/mach-mx3/pcm043.c @@ -0,0 +1,252 @@ +/* + * Copyright (C) 2009 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/types.h> +#include <linux/init.h> + +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/plat-ram.h> +#include <linux/memory.h> +#include <linux/gpio.h> +#include <linux/smc911x.h> +#include <linux/interrupt.h> +#include <linux/i2c.h> +#include <linux/i2c/at24.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/mach/map.h> + +#include <mach/hardware.h> +#include <mach/common.h> +#include <mach/imx-uart.h> +#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE +#include <mach/i2c.h> +#endif +#include <mach/iomux-mx35.h> +#include <mach/ipu.h> +#include <mach/mx3fb.h> + +#include "devices.h" + +static const struct fb_videomode fb_modedb[] = { + { + /* 240x320 @ 60 Hz */ + .name = "Sharp-LQ035Q7", + .refresh = 60, + .xres = 240, + .yres = 320, + .pixclock = 185925, + .left_margin = 9, + .right_margin = 16, + .upper_margin = 7, + .lower_margin = 9, + .hsync_len = 1, + .vsync_len = 1, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, { + /* 240x320 @ 60 Hz */ + .name = "TX090", + .refresh = 60, + .xres = 240, + .yres = 320, + .pixclock = 38255, + .left_margin = 144, + .right_margin = 0, + .upper_margin = 7, + .lower_margin = 40, + .hsync_len = 96, + .vsync_len = 1, + .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, +}; + +static struct ipu_platform_data mx3_ipu_data = { + .irq_base = MXC_IPU_IRQ_START, +}; + +static struct mx3fb_platform_data mx3fb_pdata = { + .dma_dev = &mx3_ipu.dev, + .name = "Sharp-LQ035Q7", + .mode = fb_modedb, + .num_modes = ARRAY_SIZE(fb_modedb), +}; + +static struct physmap_flash_data pcm043_flash_data = { + .width = 2, +}; + +static struct resource pcm043_flash_resource = { + .start = 0xa0000000, + .end = 0xa1ffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device pcm043_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &pcm043_flash_data, + }, + .resource = &pcm043_flash_resource, + .num_resources = 1, +}; + +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE +static struct imxi2c_platform_data pcm043_i2c_1_data = { + .bitrate = 50000, +}; + +static struct at24_platform_data board_eeprom = { + .byte_len = 4096, + .page_size = 32, + .flags = AT24_FLAG_ADDR16, +}; + +static struct i2c_board_info pcm043_i2c_devices[] = { + { + I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ + .platform_data = &board_eeprom, + }, { + I2C_BOARD_INFO("rtc-pcf8563", 0x51), + .type = "pcf8563", + } +}; +#endif + +static struct platform_device *devices[] __initdata = { + &pcm043_flash, + &mxc_fec_device, +}; + +static struct pad_desc pcm043_pads[] = { + /* UART1 */ + MX35_PAD_CTS1__UART1_CTS, + MX35_PAD_RTS1__UART1_RTS, + MX35_PAD_TXD1__UART1_TXD_MUX, + MX35_PAD_RXD1__UART1_RXD_MUX, + /* UART2 */ + MX35_PAD_CTS2__UART2_CTS, + MX35_PAD_RTS2__UART2_RTS, + MX35_PAD_TXD2__UART2_TXD_MUX, + MX35_PAD_RXD2__UART2_RXD_MUX, + /* FEC */ + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, + MX35_PAD_FEC_RX_DV__FEC_RX_DV, + MX35_PAD_FEC_COL__FEC_COL, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_TX_EN__FEC_TX_EN, + MX35_PAD_FEC_MDC__FEC_MDC, + MX35_PAD_FEC_MDIO__FEC_MDIO, + MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, + MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, + MX35_PAD_FEC_CRS__FEC_CRS, + MX35_PAD_FEC_RDATA1__FEC_RDATA_1, + MX35_PAD_FEC_TDATA1__FEC_TDATA_1, + MX35_PAD_FEC_RDATA2__FEC_RDATA_2, + MX35_PAD_FEC_TDATA2__FEC_TDATA_2, + MX35_PAD_FEC_RDATA3__FEC_RDATA_3, + MX35_PAD_FEC_TDATA3__FEC_TDATA_3, + /* I2C1 */ + MX35_PAD_I2C1_CLK__I2C1_SCL, + MX35_PAD_I2C1_DAT__I2C1_SDA, + /* Display */ + MX35_PAD_LD0__IPU_DISPB_DAT_0, + MX35_PAD_LD1__IPU_DISPB_DAT_1, + MX35_PAD_LD2__IPU_DISPB_DAT_2, + MX35_PAD_LD3__IPU_DISPB_DAT_3, + MX35_PAD_LD4__IPU_DISPB_DAT_4, + MX35_PAD_LD5__IPU_DISPB_DAT_5, + MX35_PAD_LD6__IPU_DISPB_DAT_6, + MX35_PAD_LD7__IPU_DISPB_DAT_7, + MX35_PAD_LD8__IPU_DISPB_DAT_8, + MX35_PAD_LD9__IPU_DISPB_DAT_9, + MX35_PAD_LD10__IPU_DISPB_DAT_10, + MX35_PAD_LD11__IPU_DISPB_DAT_11, + MX35_PAD_LD12__IPU_DISPB_DAT_12, + MX35_PAD_LD13__IPU_DISPB_DAT_13, + MX35_PAD_LD14__IPU_DISPB_DAT_14, + MX35_PAD_LD15__IPU_DISPB_DAT_15, + MX35_PAD_LD16__IPU_DISPB_DAT_16, + MX35_PAD_LD17__IPU_DISPB_DAT_17, + MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, + MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, + MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, + MX35_PAD_CONTRAST__IPU_DISPB_CONTR, + MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, + MX35_PAD_D3_REV__IPU_DISPB_D3_REV, + MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, + MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL +}; + +/* + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); + + platform_add_devices(devices, ARRAY_SIZE(devices)); + + mxc_register_device(&mxc_uart_device0, &uart_pdata); + + mxc_register_device(&mxc_uart_device1, &uart_pdata); + +#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE + i2c_register_board_info(0, pcm043_i2c_devices, + ARRAY_SIZE(pcm043_i2c_devices)); + + mxc_register_device(&mxc_i2c_device0, &pcm043_i2c_1_data); +#endif + + mxc_register_device(&mx3_ipu, &mx3_ipu_data); + mxc_register_device(&mx3_fb, &mx3fb_pdata); +} + +static void __init pcm043_timer_init(void) +{ + mx35_clocks_init(); +} + +struct sys_timer pcm043_timer = { + .init = pcm043_timer_init, +}; + +MACHINE_START(PCM043, "Phytec Phycore pcm043") + /* Maintainer: Pengutronix */ + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = mx35_map_io, + .init_irq = mxc_init_irq, + .init_machine = mxc_board_init, + .timer = &pcm043_timer, +MACHINE_END + diff --git a/arch/arm/mach-mx3/qong.c b/arch/arm/mach-mx3/qong.c index 5a01e48fd8f..82b31c4ab11 100644 --- a/arch/arm/mach-mx3/qong.c +++ b/arch/arm/mach-mx3/qong.c @@ -279,7 +279,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") .phys_io = AIPS1_BASE_ADDR, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, - .map_io = mxc_map_io, + .map_io = mx31_map_io, .init_irq = mxc_init_irq, .init_machine = mxc_board_init, .timer = &qong_timer, diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 3a48f2fb0ca..6226e64d99a 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -35,6 +35,11 @@ endif obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o +iommu-y += iommu2.o +iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o + +obj-$(CONFIG_OMAP_IOMMU) += $(iommu-y) + # Specific board support obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c new file mode 100644 index 00000000000..015f22a53ea --- /dev/null +++ b/arch/arm/mach-omap2/iommu2.c @@ -0,0 +1,323 @@ +/* + * omap iommu: omap2/3 architecture specific functions + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, + * Paul Mundt and Toshihiro Kobayashi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/device.h> +#include <linux/jiffies.h> +#include <linux/module.h> +#include <linux/stringify.h> + +#include <mach/iommu.h> + +/* + * omap2 architecture specific register bit definitions + */ +#define IOMMU_ARCH_VERSION 0x00000011 + +/* SYSCONF */ +#define MMU_SYS_IDLE_SHIFT 3 +#define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT) +#define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT) +#define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT) +#define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT) + +#define MMU_SYS_SOFTRESET (1 << 1) +#define MMU_SYS_AUTOIDLE 1 + +/* SYSSTATUS */ +#define MMU_SYS_RESETDONE 1 + +/* IRQSTATUS & IRQENABLE */ +#define MMU_IRQ_MULTIHITFAULT (1 << 4) +#define MMU_IRQ_TABLEWALKFAULT (1 << 3) +#define MMU_IRQ_EMUMISS (1 << 2) +#define MMU_IRQ_TRANSLATIONFAULT (1 << 1) +#define MMU_IRQ_TLBMISS (1 << 0) +#define MMU_IRQ_MASK \ + (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \ + MMU_IRQ_TRANSLATIONFAULT) + +/* MMU_CNTL */ +#define MMU_CNTL_SHIFT 1 +#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT) +#define MMU_CNTL_EML_TLB (1 << 3) +#define MMU_CNTL_TWL_EN (1 << 2) +#define MMU_CNTL_MMU_EN (1 << 1) + +#define get_cam_va_mask(pgsz) \ + (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \ + ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \ + ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \ + ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) + +static int omap2_iommu_enable(struct iommu *obj) +{ + u32 l, pa; + unsigned long timeout; + + if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) + return -EINVAL; + + pa = virt_to_phys(obj->iopgd); + if (!IS_ALIGNED(pa, SZ_16K)) + return -EINVAL; + + iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG); + + timeout = jiffies + msecs_to_jiffies(20); + do { + l = iommu_read_reg(obj, MMU_SYSSTATUS); + if (l & MMU_SYS_RESETDONE) + break; + } while (time_after(jiffies, timeout)); + + if (!(l & MMU_SYS_RESETDONE)) { + dev_err(obj->dev, "can't take mmu out of reset\n"); + return -ENODEV; + } + + l = iommu_read_reg(obj, MMU_REVISION); + dev_info(obj->dev, "%s: version %d.%d\n", obj->name, + (l >> 4) & 0xf, l & 0xf); + + l = iommu_read_reg(obj, MMU_SYSCONFIG); + l &= ~MMU_SYS_IDLE_MASK; + l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE); + iommu_write_reg(obj, l, MMU_SYSCONFIG); + + iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE); + iommu_write_reg(obj, pa, MMU_TTB); + + l = iommu_read_reg(obj, MMU_CNTL); + l &= ~MMU_CNTL_MASK; + l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); + iommu_write_reg(obj, l, MMU_CNTL); + + return 0; +} + +static void omap2_iommu_disable(struct iommu *obj) +{ + u32 l = iommu_read_reg(obj, MMU_CNTL); + + l &= ~MMU_CNTL_MASK; + iommu_write_reg(obj, l, MMU_CNTL); + iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG); + + dev_dbg(obj->dev, "%s is shutting down\n", obj->name); +} + +static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) +{ + int i; + u32 stat, da; + const char *err_msg[] = { + "tlb miss", + "translation fault", + "emulation miss", + "table walk fault", + "multi hit fault", + }; + + stat = iommu_read_reg(obj, MMU_IRQSTATUS); + stat &= MMU_IRQ_MASK; + if (!stat) + return 0; + + da = iommu_read_reg(obj, MMU_FAULT_AD); + *ra = da; + + dev_err(obj->dev, "%s:\tda:%08x ", __func__, da); + + for (i = 0; i < ARRAY_SIZE(err_msg); i++) { + if (stat & (1 << i)) + printk("%s ", err_msg[i]); + } + printk("\n"); + + iommu_write_reg(obj, stat, MMU_IRQSTATUS); + return stat; +} + +static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr) +{ + cr->cam = iommu_read_reg(obj, MMU_READ_CAM); + cr->ram = iommu_read_reg(obj, MMU_READ_RAM); +} + +static void omap2_tlb_load_cr(struct iommu *obj, struct cr_regs *cr) +{ + iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM); + iommu_write_reg(obj, cr->ram, MMU_RAM); +} + +static u32 omap2_cr_to_virt(struct cr_regs *cr) +{ + u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK; + u32 mask = get_cam_va_mask(cr->cam & page_size); + + return cr->cam & mask; +} + +static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e) +{ + struct cr_regs *cr; + + if (e->da & ~(get_cam_va_mask(e->pgsz))) { + dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__, + e->da); + return ERR_PTR(-EINVAL); + } + + cr = kmalloc(sizeof(*cr), GFP_KERNEL); + if (!cr) + return ERR_PTR(-ENOMEM); + + cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz; + cr->ram = e->pa | e->endian | e->elsz | e->mixed; + + return cr; +} + +static inline int omap2_cr_valid(struct cr_regs *cr) +{ + return cr->cam & MMU_CAM_V; +} + +static u32 omap2_get_pte_attr(struct iotlb_entry *e) +{ + u32 attr; + + attr = e->mixed << 5; + attr |= e->endian; + attr |= e->elsz >> 3; + attr <<= ((e->pgsz & MMU_CAM_PGSZ_4K) ? 0 : 6); + + return attr; +} + +static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf) +{ + char *p = buf; + + /* FIXME: Need more detail analysis of cam/ram */ + p += sprintf(p, "%08x %08x\n", cr->cam, cr->ram); + + return p - buf; +} + +#define pr_reg(name) \ + p += sprintf(p, "%20s: %08x\n", \ + __stringify(name), iommu_read_reg(obj, MMU_##name)); + +static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf) +{ + char *p = buf; + + pr_reg(REVISION); + pr_reg(SYSCONFIG); + pr_reg(SYSSTATUS); + pr_reg(IRQSTATUS); + pr_reg(IRQENABLE); + pr_reg(WALKING_ST); + pr_reg(CNTL); + pr_reg(FAULT_AD); + pr_reg(TTB); + pr_reg(LOCK); + pr_reg(LD_TLB); + pr_reg(CAM); + pr_reg(RAM); + pr_reg(GFLUSH); + pr_reg(FLUSH_ENTRY); + pr_reg(READ_CAM); + pr_reg(READ_RAM); + pr_reg(EMU_FAULT_AD); + + return p - buf; +} + +static void omap2_iommu_save_ctx(struct iommu *obj) +{ + int i; + u32 *p = obj->ctx; + + for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { + p[i] = iommu_read_reg(obj, i * sizeof(u32)); + dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); + } + + BUG_ON(p[0] != IOMMU_ARCH_VERSION); +} + +static void omap2_iommu_restore_ctx(struct iommu *obj) +{ + int i; + u32 *p = obj->ctx; + + for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { + iommu_write_reg(obj, p[i], i * sizeof(u32)); + dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); + } + + BUG_ON(p[0] != IOMMU_ARCH_VERSION); +} + +static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) +{ + e->da = cr->cam & MMU_CAM_VATAG_MASK; + e->pa = cr->ram & MMU_RAM_PADDR_MASK; + e->valid = cr->cam & MMU_CAM_V; + e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK; + e->endian = cr->ram & MMU_RAM_ENDIAN_MASK; + e->elsz = cr->ram & MMU_RAM_ELSZ_MASK; + e->mixed = cr->ram & MMU_RAM_MIXED; +} + +static const struct iommu_functions omap2_iommu_ops = { + .version = IOMMU_ARCH_VERSION, + + .enable = omap2_iommu_enable, + .disable = omap2_iommu_disable, + .fault_isr = omap2_iommu_fault_isr, + + .tlb_read_cr = omap2_tlb_read_cr, + .tlb_load_cr = omap2_tlb_load_cr, + + .cr_to_e = omap2_cr_to_e, + .cr_to_virt = omap2_cr_to_virt, + .alloc_cr = omap2_alloc_cr, + .cr_valid = omap2_cr_valid, + .dump_cr = omap2_dump_cr, + + .get_pte_attr = omap2_get_pte_attr, + + .save_ctx = omap2_iommu_save_ctx, + .restore_ctx = omap2_iommu_restore_ctx, + .dump_ctx = omap2_iommu_dump_ctx, +}; + +static int __init omap2_iommu_init(void) +{ + return install_iommu_arch(&omap2_iommu_ops); +} +module_init(omap2_iommu_init); + +static void __exit omap2_iommu_exit(void) +{ + uninstall_iommu_arch(&omap2_iommu_ops); +} +module_exit(omap2_iommu_exit); + +MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); +MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions"); +MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/mach-omap2/omap3-iommu.c b/arch/arm/mach-omap2/omap3-iommu.c new file mode 100644 index 00000000000..194189c746c --- /dev/null +++ b/arch/arm/mach-omap2/omap3-iommu.c @@ -0,0 +1,105 @@ +/* + * omap iommu: omap3 device registration + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/platform_device.h> + +#include <mach/iommu.h> + +#define OMAP3_MMU1_BASE 0x480bd400 +#define OMAP3_MMU2_BASE 0x5d000000 +#define OMAP3_MMU1_IRQ 24 +#define OMAP3_MMU2_IRQ 28 + + +static unsigned long iommu_base[] __initdata = { + OMAP3_MMU1_BASE, + OMAP3_MMU2_BASE, +}; + +static int iommu_irq[] __initdata = { + OMAP3_MMU1_IRQ, + OMAP3_MMU2_IRQ, +}; + +static const struct iommu_platform_data omap3_iommu_pdata[] __initconst = { + { + .name = "isp", + .nr_tlb_entries = 8, + .clk_name = "cam_ick", + }, +#if defined(CONFIG_MPU_BRIDGE_IOMMU) + { + .name = "iva2", + .nr_tlb_entries = 32, + .clk_name = "iva2_ck", + }, +#endif +}; +#define NR_IOMMU_DEVICES ARRAY_SIZE(omap3_iommu_pdata) + +static struct platform_device *omap3_iommu_pdev[NR_IOMMU_DEVICES]; + +static int __init omap3_iommu_init(void) +{ + int i, err; + + for (i = 0; i < NR_IOMMU_DEVICES; i++) { + struct platform_device *pdev; + struct resource res[2]; + + pdev = platform_device_alloc("omap-iommu", i); + if (!pdev) { + err = -ENOMEM; + goto err_out; + } + + memset(res, 0, sizeof(res)); + res[0].start = iommu_base[i]; + res[0].end = iommu_base[i] + MMU_REG_SIZE - 1; + res[0].flags = IORESOURCE_MEM; + res[1].start = res[1].end = iommu_irq[i]; + res[1].flags = IORESOURCE_IRQ; + + err = platform_device_add_resources(pdev, res, + ARRAY_SIZE(res)); + if (err) + goto err_out; + err = platform_device_add_data(pdev, &omap3_iommu_pdata[i], + sizeof(omap3_iommu_pdata[0])); + if (err) + goto err_out; + err = platform_device_add(pdev); + if (err) + goto err_out; + omap3_iommu_pdev[i] = pdev; + } + return 0; + +err_out: + while (i--) + platform_device_put(omap3_iommu_pdev[i]); + return err; +} +module_init(omap3_iommu_init); + +static void __exit omap3_iommu_exit(void) +{ + int i; + + for (i = 0; i < NR_IOMMU_DEVICES; i++) + platform_device_unregister(omap3_iommu_pdev[i]); +} +module_exit(omap3_iommu_exit); + +MODULE_AUTHOR("Hiroshi DOYU"); +MODULE_DESCRIPTION("omap iommu: omap3 device registration"); +MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index 9f88dd3be60..0ab75c60f7c 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -110,6 +110,12 @@ static int remap_area_pages(unsigned long start, unsigned long pfn, return err; } +int ioremap_page(unsigned long virt, unsigned long phys, + const struct mem_type *mtype) +{ + return remap_area_pages(virt, __phys_to_pfn(phys), PAGE_SIZE, mtype); +} +EXPORT_SYMBOL(ioremap_page); void __check_kvm_seq(struct mm_struct *mm) { diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index e6344ece00c..70974d75a07 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -255,6 +255,7 @@ const struct mem_type *get_mem_type(unsigned int type) { return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; } +EXPORT_SYMBOL(get_mem_type); /* * Adjust the PMD section entries according to the CPU in use. diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 17d0e9906d5..8986b741223 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -48,7 +48,14 @@ config MXC_IRQ_PRIOR config MXC_PWM tristate "Enable PWM driver" depends on ARCH_MXC + select HAVE_PWM help Enable support for the i.MX PWM controller(s). +config ARCH_HAS_RNGA + bool + depends on ARCH_MXC + +config ARCH_MXC_IOMUX_V3 + bool endif diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 055406312b6..e3212c8ff42 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -7,4 +7,5 @@ obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o +obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o obj-$(CONFIG_MXC_PWM) += pwm.o diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 89e95798cc3..7506d963be4 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -64,6 +64,8 @@ static void gpio_unmask_irq(u32 irq) _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1); } +static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset); + static int gpio_set_irq_type(u32 irq, u32 type) { u32 gpio = irq_to_gpio(irq); @@ -72,6 +74,7 @@ static int gpio_set_irq_type(u32 irq, u32 type) int edge; void __iomem *reg = port->base; + port->both_edges &= ~(1 << (gpio & 31)); switch (type) { case IRQ_TYPE_EDGE_RISING: edge = GPIO_INT_RISE_EDGE; @@ -79,13 +82,24 @@ static int gpio_set_irq_type(u32 irq, u32 type) case IRQ_TYPE_EDGE_FALLING: edge = GPIO_INT_FALL_EDGE; break; + case IRQ_TYPE_EDGE_BOTH: + val = mxc_gpio_get(&port->chip, gpio & 31); + if (val) { + edge = GPIO_INT_LOW_LEV; + pr_debug("mxc: set GPIO %d to low trigger\n", gpio); + } else { + edge = GPIO_INT_HIGH_LEV; + pr_debug("mxc: set GPIO %d to high trigger\n", gpio); + } + port->both_edges |= 1 << (gpio & 31); + break; case IRQ_TYPE_LEVEL_LOW: edge = GPIO_INT_LOW_LEV; break; case IRQ_TYPE_LEVEL_HIGH: edge = GPIO_INT_HIGH_LEV; break; - default: /* this includes IRQ_TYPE_EDGE_BOTH */ + default: return -EINVAL; } @@ -98,6 +112,34 @@ static int gpio_set_irq_type(u32 irq, u32 type) return 0; } +static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) +{ + void __iomem *reg = port->base; + u32 bit, val; + int edge; + + reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ + bit = gpio & 0xf; + val = __raw_readl(reg); + edge = (val >> (bit << 1)) & 3; + val &= ~(0x3 << (bit << 1)); + switch (edge) { + case GPIO_INT_HIGH_LEV: + edge = GPIO_INT_LOW_LEV; + pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); + break; + case GPIO_INT_LOW_LEV: + edge = GPIO_INT_HIGH_LEV; + pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); + break; + default: + pr_err("mxc: invalid configuration for GPIO %d: %x\n", + gpio, edge); + return; + } + __raw_writel(val | (edge << (bit << 1)), reg); +} + /* handle n interrupts in one status register */ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) { @@ -105,11 +147,16 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) gpio_irq_no = port->virtual_irq_start; for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) { + u32 gpio = irq_to_gpio(gpio_irq_no); if ((irq_stat & 1) == 0) continue; BUG_ON(!(irq_desc[gpio_irq_no].handle_irq)); + + if (port->both_edges & (1 << (gpio & 31))) + mxc_flip_edge(port, gpio); + irq_desc[gpio_irq_no].handle_irq(gpio_irq_no, &irq_desc[gpio_irq_no]); } diff --git a/arch/arm/plat-mxc/include/mach/board-mx21ads.h b/arch/arm/plat-mxc/include/mach/board-mx21ads.h new file mode 100644 index 00000000000..06701df74c4 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-mx21ads.h @@ -0,0 +1,58 @@ +/* + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__ +#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__ + +/* + * MXC UART EVB board level configurations + */ +#define MXC_LL_UART_PADDR UART1_BASE_ADDR +#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR) + +/* + * Memory-mapped I/O on MX21ADS base board + */ +#define MX21ADS_MMIO_BASE_ADDR 0xF5000000 +#define MX21ADS_MMIO_SIZE SZ_16M + +#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \ + (MX21ADS_MMIO_BASE_ADDR + (offset)) + +#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11) +#define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000) +#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000) +#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000) +#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000) + +/* MX21ADS_IO_REG bit definitions */ +#define MX21ADS_IO_SD_WP 0x0001 /* read */ +#define MX21ADS_IO_TP6 0x0001 /* write */ +#define MX21ADS_IO_SW_SEL 0x0002 /* read */ +#define MX21ADS_IO_TP7 0x0002 /* write */ +#define MX21ADS_IO_RESET_E_UART 0x0004 +#define MX21ADS_IO_RESET_BASE 0x0008 +#define MX21ADS_IO_CSI_CTL2 0x0010 +#define MX21ADS_IO_CSI_CTL1 0x0020 +#define MX21ADS_IO_CSI_CTL0 0x0040 +#define MX21ADS_IO_UART1_EN 0x0080 +#define MX21ADS_IO_UART4_EN 0x0100 +#define MX21ADS_IO_LCDON 0x0200 +#define MX21ADS_IO_IRDA_EN 0x0400 +#define MX21ADS_IO_IRDA_FIR_SEL 0x0800 +#define MX21ADS_IO_IRDA_MD0_B 0x1000 +#define MX21ADS_IO_IRDA_MD1 0x2000 +#define MX21ADS_IO_LED4_ON 0x4000 +#define MX21ADS_IO_LED3_ON 0x8000 + +#endif /* __ASM_ARCH_MXC_BOARD_MX21ADS_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h new file mode 100644 index 00000000000..552b55d714d --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h @@ -0,0 +1,19 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__ +#define __ASM_ARCH_MXC_BOARD_MX27PDK_H__ + +/* mandatory for CONFIG_DEBUG_LL */ + +#define MXC_LL_UART_PADDR UART1_BASE_ADDR +#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) + +#endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h index 318c72ada13..06e6895f7f6 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h @@ -114,7 +114,7 @@ #define MXC_MAX_EXP_IO_LINES 16 -/* mandatory for CONFIG_LL_DEBUG */ +/* mandatory for CONFIG_DEBUG_LL */ #define MXC_LL_UART_PADDR UART1_BASE_ADDR #define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h index e4e5cf5ad7d..52fbdf2d6f2 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h @@ -11,28 +11,8 @@ #ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__ #define __ASM_ARCH_MXC_BOARD_MX31LITE_H__ -#define MXC_MAX_EXP_IO_LINES 16 - - -/* - * Memory Size parameters - */ - -/* - * Size of SDRAM memory - */ -#define SDRAM_MEM_SIZE SZ_128M -/* - * Size of MBX buffer memory - */ -#define MXC_MBX_MEM_SIZE SZ_16M -/* - * Size of memory available to kernel - */ -#define MEM_SIZE (SDRAM_MEM_SIZE - MXC_MBX_MEM_SIZE) - #define MXC_LL_UART_PADDR UART1_BASE_ADDR #define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) -#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ +#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h index f8aef1babb7..303fd2434a2 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h @@ -19,7 +19,7 @@ #ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ #define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ -/* mandatory for CONFIG_LL_DEBUG */ +/* mandatory for CONFIG_DEBUG_LL */ #define MXC_LL_UART_PADDR UART1_BASE_ADDR #define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000) diff --git a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h index 2b6b316d0f5..519bab3eb28 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h @@ -11,9 +11,54 @@ #ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__ #define __ASM_ARCH_MXC_BOARD_MX31PDK_H__ -/* mandatory for CONFIG_LL_DEBUG */ +/* mandatory for CONFIG_DEBUG_LL */ #define MXC_LL_UART_PADDR UART1_BASE_ADDR #define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) +/* Definitions for components on the Debug board */ + +/* Base address of CPLD controller on the Debug board */ +#define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(CS5_BASE_ADDR) + +/* LAN9217 ethernet base address */ +#define LAN9217_BASE_ADDR CS5_BASE_ADDR + +/* CPLD config and interrupt base address */ +#define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000) + +/* LED switchs */ +#define CPLD_LED_REG (CPLD_ADDR + 0x00) +/* buttons */ +#define CPLD_SWITCH_BUTTONS_REG (EXPIO_ADDR + 0x08) +/* status, interrupt */ +#define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10) +#define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38) +#define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20) +/* magic word for debug CPLD */ +#define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40) +#define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48) +/* CPLD code version */ +#define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50) +/* magic word for debug CPLD */ +#define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58) +/* module reset register */ +#define CPLD_MODULE_RESET_REG (CPLD_ADDR + 0x60) +/* CPU ID and Personality ID */ +#define CPLD_MCU_BOARD_ID_REG (CPLD_ADDR + 0x68) + +/* CPLD IRQ line for external uart, external ethernet etc */ +#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1) + +#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START) +#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) + +#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0) +#define EXPIO_INT_XUART_A (MXC_EXP_IO_BASE + 1) +#define EXPIO_INT_XUART_B (MXC_EXP_IO_BASE + 2) +#define EXPIO_INT_BUTTON_A (MXC_EXP_IO_BASE + 3) +#define EXPIO_INT_BUTTON_B (MXC_EXP_IO_BASE + 4) + +#define MXC_MAX_EXP_IO_LINES 16 + #endif /* __ASM_ARCH_MXC_BOARD_MX31PDK_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/plat-mxc/include/mach/board-pcm037.h index 82232ba3c8f..f0a1fa1938a 100644 --- a/arch/arm/plat-mxc/include/mach/board-pcm037.h +++ b/arch/arm/plat-mxc/include/mach/board-pcm037.h @@ -19,7 +19,7 @@ #ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__ #define __ASM_ARCH_MXC_BOARD_PCM037_H__ -/* mandatory for CONFIG_LL_DEBUG */ +/* mandatory for CONFIG_DEBUG_LL */ #define MXC_LL_UART_PADDR UART1_BASE_ADDR #define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h index 750c62afd90..4fcd7499e09 100644 --- a/arch/arm/plat-mxc/include/mach/board-pcm038.h +++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h @@ -19,7 +19,7 @@ #ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__ #define __ASM_ARCH_MXC_BOARD_PCM038_H__ -/* mandatory for CONFIG_LL_DEBUG */ +/* mandatory for CONFIG_DEBUG_LL */ #define MXC_LL_UART_PADDR UART1_BASE_ADDR #define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000) diff --git a/arch/arm/mach-imx/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/board-pcm043.h index e22ba789546..15fbdf16abc 100644 --- a/arch/arm/mach-imx/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/board-pcm043.h @@ -1,7 +1,5 @@ /* - * linux/include/asm-arm/imx/timex.h - * - * Copyright (C) 1999 ARM Limited + * Copyright (C) 2008 Sascha Hauer, Pengutronix * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,9 +16,12 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H +#ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__ +#define __ASM_ARCH_MXC_BOARD_PCM043_H__ + +/* mandatory for CONFIG_LL_DEBUG */ -#define CLOCK_TICK_RATE (16000000) +#define MXC_LL_UART_PADDR UART1_BASE_ADDR +#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) -#endif +#endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h index 4ff762dd45c..04033ec637d 100644 --- a/arch/arm/plat-mxc/include/mach/board-qong.h +++ b/arch/arm/plat-mxc/include/mach/board-qong.h @@ -11,7 +11,7 @@ #ifndef __ASM_ARCH_MXC_BOARD_QONG_H__ #define __ASM_ARCH_MXC_BOARD_QONG_H__ -/* mandatory for CONFIG_LL_DEBUG */ +/* mandatory for CONFIG_DEBUG_LL */ #define MXC_LL_UART_PADDR UART1_BASE_ADDR #define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index b2f9b72644d..02c3cd004db 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -14,7 +14,11 @@ struct platform_device; struct clk; -extern void mxc_map_io(void); +extern void mx1_map_io(void); +extern void mx21_map_io(void); +extern void mx27_map_io(void); +extern void mx31_map_io(void); +extern void mx35_map_io(void); extern void mxc_init_irq(void); extern void mxc_timer_init(struct clk *timer_clk); extern int mx1_clocks_init(unsigned long fref); diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index 4f773148bc2..e6b841b15e3 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -25,6 +25,9 @@ #ifdef CONFIG_MACH_MX27ADS #include <mach/board-mx27ads.h> #endif +#ifdef CONFIG_MACH_MX21ADS +#include <mach/board-mx21ads.h> +#endif #ifdef CONFIG_MACH_PCM038 #include <mach/board-pcm038.h> #endif @@ -34,6 +37,12 @@ #ifdef CONFIG_MACH_QONG #include <mach/board-qong.h> #endif +#ifdef CONFIG_MACH_PCM043 +#include <mach/board-pcm043.h> +#endif +#ifdef CONFIG_MACH_MX27_3DS +#include <mach/board-mx27pdk.h> +#endif .macro addruart,rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index ea509f1090f..894d2f87c85 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -35,6 +35,7 @@ struct mxc_gpio_port { int irq; int virtual_irq_start; struct gpio_chip chip; + u32 both_edges; }; int mxc_gpio_init(struct mxc_gpio_port*, int); diff --git a/arch/arm/plat-mxc/include/mach/imx-uart.h b/arch/arm/plat-mxc/include/mach/imx-uart.h index 599217b2e13..90af4d9bc19 100644 --- a/arch/arm/plat-mxc/include/mach/imx-uart.h +++ b/arch/arm/plat-mxc/include/mach/imx-uart.h @@ -23,7 +23,7 @@ struct imxuart_platform_data { int (*init)(struct platform_device *pdev); - int (*exit)(struct platform_device *pdev); + void (*exit)(struct platform_device *pdev); unsigned int flags; }; diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h index 762a7b0430e..9f0101157ec 100644 --- a/arch/arm/plat-mxc/include/mach/imxfb.h +++ b/arch/arm/plat-mxc/include/mach/imxfb.h @@ -76,8 +76,8 @@ struct imx_fb_platform_data { u_char * fixed_screen_cpu; dma_addr_t fixed_screen_dma; - int (*init)(struct platform_device*); - int (*exit)(struct platform_device*); + int (*init)(struct platform_device *); + void (*exit)(struct platform_device *); void (*lcd_power)(int); void (*backlight_power)(int); diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index 57e927a1fd3..27f8d1b2bc6 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -114,7 +114,7 @@ enum iomux_gp_func { * - setups the iomux according to the configuration * - if the pin is configured as a GPIO, we claim it throug kernel gpiolib */ -int mxc_iomux_setup_pin(const unsigned int pin, const char *label); +int mxc_iomux_alloc_pin(const unsigned int pin, const char *label); /* * setups mutliple pins * convenient way to call the above function with tables @@ -633,6 +633,40 @@ enum iomux_pins { #define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) #define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) #define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) +#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_ATA_CS0__GPIO3_26 IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_ATA_CS1__GPIO3_27 IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_PC_PWRON__SD2_DATA3 IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_VS1__SD2_DATA2 IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_READY__SD2_DATA1 IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_WAIT_B__SD2_DATA0 IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_CD2_B__SD2_CLK IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_CD1_B__SD2_CMD IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_ATA_DIOR__GPIO3_28 IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO) +#define MX31_PIN_ATA_DIOW__GPIO3_29 IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D7__CSI_D7 IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D8__CSI_D8 IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D9__CSI_D9 IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D10__CSI_D10 IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D11__CSI_D11 IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D12__CSI_D12 IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D13__CSI_D13 IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D14__CSI_D14 IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D15__CSI_D15 IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_HSYNC__CSI_HSYNC IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_MCLK__CSI_MCLK IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_VSYNC__CSI_VSYNC IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC) +#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 * cspi1_ss1*/ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h new file mode 100644 index 00000000000..00b0ac1db22 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h @@ -0,0 +1,1267 @@ +/* + * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option, NO_PAD_CTRL) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_IOMUX_MX35_H__ +#define __MACH_IOMUX_MX35_H__ + +#include <mach/iomux-v3.h> + +/* + * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> + * If <padname> or <padmode> refers to a GPIO, it is named + * GPIO_<unit>_<num> see also iomux-v3.h + */ + +/* PAD MUX ALT INPSE PATH */ +#define MX35_PAD_CAPTURE__GPT_CAPIN1 IOMUX_PAD(0x328, 0x004, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CAPTURE__GPT_CMPOUT2 IOMUX_PAD(0x328, 0x004, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CAPTURE__CSPI2_SS1 IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL) +#define MX35_PAD_CAPTURE__EPIT1_EPITO IOMUX_PAD(0x328, 0x004, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CAPTURE__CCM_CLK32K IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL) +#define MX35_PAD_CAPTURE__GPIO1_4 IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL) + +#define MX35_PAD_COMPARE__GPT_CMPOUT1 IOMUX_PAD(0x32c, 0x008, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_COMPARE__GPT_CAPIN2 IOMUX_PAD(0x32c, 0x008, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_COMPARE__GPT_CMPOUT3 IOMUX_PAD(0x32c, 0x008, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_COMPARE__EPIT2_EPITO IOMUX_PAD(0x32c, 0x008, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_COMPARE__GPIO1_5 IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL) +#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 IOMUX_PAD(0x32c, 0x008, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_WDOG_RST__WDOG_WDOG_B IOMUX_PAD(0x330, 0x00c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE IOMUX_PAD(0x330, 0x00c, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_WDOG_RST__GPIO1_6 IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL) + +#define MX35_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_0__OWIRE_LINE IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 IOMUX_PAD(0x334, 0x010, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_1__PWM_PWMO IOMUX_PAD(0x338, 0x014, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_1__CSPI1_SS2 IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT IOMUX_PAD(0x338, 0x014, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 IOMUX_PAD(0x338, 0x014, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_GPIO2_0__GPIO2_0 IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK IOMUX_PAD(0x33c, 0x018, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_GPIO3_0__GPIO3_0 IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK IOMUX_PAD(0x340, 0x01c, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B IOMUX_PAD(0x344, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_POR_B__CCM_POR_B IOMUX_PAD(0x348, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CLKO__CCM_CLKO IOMUX_PAD(0x34c, 0x020, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CLKO__GPIO1_8 IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL) + +#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 IOMUX_PAD(0x350, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 IOMUX_PAD(0x354, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 IOMUX_PAD(0x358, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 IOMUX_PAD(0x35c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 IOMUX_PAD(0x360, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_VSTBY__CCM_VSTBY IOMUX_PAD(0x364, 0x024, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_VSTBY__GPIO1_7 IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL) + +#define MX35_PAD_A0__EMI_EIM_DA_L_0 IOMUX_PAD(0x368, 0x028, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A1__EMI_EIM_DA_L_1 IOMUX_PAD(0x36c, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A2__EMI_EIM_DA_L_2 IOMUX_PAD(0x370, 0x030, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A3__EMI_EIM_DA_L_3 IOMUX_PAD(0x374, 0x034, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A4__EMI_EIM_DA_L_4 IOMUX_PAD(0x378, 0x038, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A5__EMI_EIM_DA_L_5 IOMUX_PAD(0x37c, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A6__EMI_EIM_DA_L_6 IOMUX_PAD(0x380, 0x040, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A7__EMI_EIM_DA_L_7 IOMUX_PAD(0x384, 0x044, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A8__EMI_EIM_DA_H_8 IOMUX_PAD(0x388, 0x048, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A9__EMI_EIM_DA_H_9 IOMUX_PAD(0x38c, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A10__EMI_EIM_DA_H_10 IOMUX_PAD(0x390, 0x050, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_MA10__EMI_MA10 IOMUX_PAD(0x394, 0x054, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A11__EMI_EIM_DA_H_11 IOMUX_PAD(0x398, 0x058, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A12__EMI_EIM_DA_H_12 IOMUX_PAD(0x39c, 0x05c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A13__EMI_EIM_DA_H_13 IOMUX_PAD(0x3a0, 0x060, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A14__EMI_EIM_DA_H2_14 IOMUX_PAD(0x3a4, 0x064, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A15__EMI_EIM_DA_H2_15 IOMUX_PAD(0x3a8, 0x068, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A16__EMI_EIM_A_16 IOMUX_PAD(0x3ac, 0x06c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A17__EMI_EIM_A_17 IOMUX_PAD(0x3b0, 0x070, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A18__EMI_EIM_A_18 IOMUX_PAD(0x3b4, 0x074, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A19__EMI_EIM_A_19 IOMUX_PAD(0x3b8, 0x078, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A20__EMI_EIM_A_20 IOMUX_PAD(0x3bc, 0x07c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A21__EMI_EIM_A_21 IOMUX_PAD(0x3c0, 0x080, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A22__EMI_EIM_A_22 IOMUX_PAD(0x3c4, 0x084, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A23__EMI_EIM_A_23 IOMUX_PAD(0x3c8, 0x088, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A24__EMI_EIM_A_24 IOMUX_PAD(0x3cc, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A25__EMI_EIM_A_25 IOMUX_PAD(0x3d0, 0x090, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDBA1__EMI_EIM_SDBA1 IOMUX_PAD(0x3d4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDBA0__EMI_EIM_SDBA0 IOMUX_PAD(0x3d8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD0__EMI_DRAM_D_0 IOMUX_PAD(0x3dc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1__EMI_DRAM_D_1 IOMUX_PAD(0x3e0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD2__EMI_DRAM_D_2 IOMUX_PAD(0x3e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD3__EMI_DRAM_D_3 IOMUX_PAD(0x3e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD4__EMI_DRAM_D_4 IOMUX_PAD(0x3ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD5__EMI_DRAM_D_5 IOMUX_PAD(0x3f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD6__EMI_DRAM_D_6 IOMUX_PAD(0x3f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD7__EMI_DRAM_D_7 IOMUX_PAD(0x3f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD8__EMI_DRAM_D_8 IOMUX_PAD(0x3fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD9__EMI_DRAM_D_9 IOMUX_PAD(0x400, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD10__EMI_DRAM_D_10 IOMUX_PAD(0x404, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD11__EMI_DRAM_D_11 IOMUX_PAD(0x408, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD12__EMI_DRAM_D_12 IOMUX_PAD(0x40c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD13__EMI_DRAM_D_13 IOMUX_PAD(0x410, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD14__EMI_DRAM_D_14 IOMUX_PAD(0x414, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD15__EMI_DRAM_D_15 IOMUX_PAD(0x418, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD16__EMI_DRAM_D_16 IOMUX_PAD(0x41c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD17__EMI_DRAM_D_17 IOMUX_PAD(0x420, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD18__EMI_DRAM_D_18 IOMUX_PAD(0x424, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD19__EMI_DRAM_D_19 IOMUX_PAD(0x428, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD20__EMI_DRAM_D_20 IOMUX_PAD(0x42c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD21__EMI_DRAM_D_21 IOMUX_PAD(0x430, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD22__EMI_DRAM_D_22 IOMUX_PAD(0x434, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD23__EMI_DRAM_D_23 IOMUX_PAD(0x438, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD24__EMI_DRAM_D_24 IOMUX_PAD(0x43c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD25__EMI_DRAM_D_25 IOMUX_PAD(0x440, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD26__EMI_DRAM_D_26 IOMUX_PAD(0x444, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD27__EMI_DRAM_D_27 IOMUX_PAD(0x448, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD28__EMI_DRAM_D_28 IOMUX_PAD(0x44c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD29__EMI_DRAM_D_29 IOMUX_PAD(0x450, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD30__EMI_DRAM_D_30 IOMUX_PAD(0x454, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD31__EMI_DRAM_D_31 IOMUX_PAD(0x458, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_DQM0__EMI_DRAM_DQM_0 IOMUX_PAD(0x45c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_DQM1__EMI_DRAM_DQM_1 IOMUX_PAD(0x460, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_DQM2__EMI_DRAM_DQM_2 IOMUX_PAD(0x464, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_DQM3__EMI_DRAM_DQM_3 IOMUX_PAD(0x468, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_EB0__EMI_EIM_EB0_B IOMUX_PAD(0x46c, 0x094, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_EB1__EMI_EIM_EB1_B IOMUX_PAD(0x470, 0x098, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_OE__EMI_EIM_OE IOMUX_PAD(0x474, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS0__EMI_EIM_CS0 IOMUX_PAD(0x478, 0x0a0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS1__EMI_EIM_CS1 IOMUX_PAD(0x47c, 0x0a4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CS1__EMI_NANDF_CE3 IOMUX_PAD(0x47c, 0x0a4, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS2__EMI_EIM_CS2 IOMUX_PAD(0x480, 0x0a8, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS3__EMI_EIM_CS3 IOMUX_PAD(0x484, 0x0ac, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS4__EMI_EIM_CS4 IOMUX_PAD(0x488, 0x0b0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CS4__EMI_DTACK_B IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL) +#define MX35_PAD_CS4__EMI_NANDF_CE1 IOMUX_PAD(0x488, 0x0b0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CS4__GPIO1_20 IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS5__EMI_EIM_CS5 IOMUX_PAD(0x48c, 0x0b4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CS5__CSPI2_SS2 IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL) +#define MX35_PAD_CS5__CSPI1_SS2 IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL) +#define MX35_PAD_CS5__EMI_NANDF_CE2 IOMUX_PAD(0x48c, 0x0b4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CS5__GPIO1_21 IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL) + +#define MX35_PAD_NF_CE0__EMI_NANDF_CE0 IOMUX_PAD(0x490, 0x0b8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NF_CE0__GPIO1_22 IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL) + +#define MX35_PAD_ECB__EMI_EIM_ECB IOMUX_PAD(0x494, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LBA__EMI_EIM_LBA IOMUX_PAD(0x498, 0x0bc, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_BCLK__EMI_EIM_BCLK IOMUX_PAD(0x49c, 0x0c0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RW__EMI_EIM_RW IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RAS__EMI_DRAM_RAS IOMUX_PAD(0x4a4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CAS__EMI_DRAM_CAS IOMUX_PAD(0x4a8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDWE__EMI_DRAM_SDWE IOMUX_PAD(0x4ac, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 IOMUX_PAD(0x4b0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 IOMUX_PAD(0x4b4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK IOMUX_PAD(0x4b8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 IOMUX_PAD(0x4bc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 IOMUX_PAD(0x4c0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 IOMUX_PAD(0x4c4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 IOMUX_PAD(0x4c8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWE_B__GPIO2_18 IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRE_B__GPIO2_19 IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFALE__EMI_NANDF_ALE IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFALE__USB_TOP_USBH2_STP IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFALE__IPU_DISPB_CS0 IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFALE__GPIO2_20 IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL) +#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFCLE__EMI_NANDF_CLE IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFCLE__GPIO2_21 IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL) +#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWP_B__IPU_DISPB_WR IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWP_B__GPIO2_22 IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFRB__EMI_NANDF_RB IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRB__IPU_DISPB_RD IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRB__GPIO2_23 IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D15__EMI_EIM_D_15 IOMUX_PAD(0x4e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D14__EMI_EIM_D_14 IOMUX_PAD(0x4e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D13__EMI_EIM_D_13 IOMUX_PAD(0x4ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D12__EMI_EIM_D_12 IOMUX_PAD(0x4f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D11__EMI_EIM_D_11 IOMUX_PAD(0x4f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D10__EMI_EIM_D_10 IOMUX_PAD(0x4f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D9__EMI_EIM_D_9 IOMUX_PAD(0x4fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D8__EMI_EIM_D_8 IOMUX_PAD(0x500, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D7__EMI_EIM_D_7 IOMUX_PAD(0x504, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D6__EMI_EIM_D_6 IOMUX_PAD(0x508, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D5__EMI_EIM_D_5 IOMUX_PAD(0x50c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D4__EMI_EIM_D_4 IOMUX_PAD(0x510, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3__EMI_EIM_D_3 IOMUX_PAD(0x514, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D2__EMI_EIM_D_2 IOMUX_PAD(0x518, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D1__EMI_EIM_D_1 IOMUX_PAD(0x51c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D0__EMI_EIM_D_0 IOMUX_PAD(0x520, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D8__IPU_CSI_D_8 IOMUX_PAD(0x524, 0x0e0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D8__KPP_COL_0 IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D8__GPIO1_20 IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL) +#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 IOMUX_PAD(0x524, 0x0e0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D9__IPU_CSI_D_9 IOMUX_PAD(0x528, 0x0e4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D9__KPP_COL_1 IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D9__GPIO1_21 IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL) +#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 IOMUX_PAD(0x528, 0x0e4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D10__IPU_CSI_D_10 IOMUX_PAD(0x52c, 0x0e8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D10__KPP_COL_2 IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D10__GPIO1_22 IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL) +#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 IOMUX_PAD(0x52c, 0x0e8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D11__IPU_CSI_D_11 IOMUX_PAD(0x530, 0x0ec, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D11__KPP_COL_3 IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D11__GPIO1_23 IOMUX_PAD(0x530, 0x0ec, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D12__IPU_CSI_D_12 IOMUX_PAD(0x534, 0x0f0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D12__KPP_ROW_0 IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D12__GPIO1_24 IOMUX_PAD(0x534, 0x0f0, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D13__IPU_CSI_D_13 IOMUX_PAD(0x538, 0x0f4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D13__KPP_ROW_1 IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D13__GPIO1_25 IOMUX_PAD(0x538, 0x0f4, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D14__IPU_CSI_D_14 IOMUX_PAD(0x53c, 0x0f8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D14__KPP_ROW_2 IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D14__GPIO1_26 IOMUX_PAD(0x53c, 0x0f8, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D15__IPU_CSI_D_15 IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D15__KPP_ROW_3 IOMUX_PAD(0x540, 0x0fc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D15__GPIO1_27 IOMUX_PAD(0x540, 0x0fc, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK IOMUX_PAD(0x544, 0x100, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_MCLK__GPIO1_28 IOMUX_PAD(0x544, 0x100, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC IOMUX_PAD(0x548, 0x104, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_VSYNC__GPIO1_29 IOMUX_PAD(0x548, 0x104, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC IOMUX_PAD(0x54c, 0x108, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_HSYNC__GPIO1_30 IOMUX_PAD(0x54c, 0x108, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK IOMUX_PAD(0x550, 0x10c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_PIXCLK__GPIO1_31 IOMUX_PAD(0x550, 0x10c, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_I2C1_CLK__I2C1_SCL IOMUX_PAD(0x554, 0x110, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C1_CLK__GPIO2_24 IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK IOMUX_PAD(0x554, 0x110, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_I2C1_DAT__I2C1_SDA IOMUX_PAD(0x558, 0x114, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C1_DAT__GPIO2_25 IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL) + +#define MX35_PAD_I2C2_CLK__I2C2_SCL IOMUX_PAD(0x55c, 0x118, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_CLK__CAN1_TXCAN IOMUX_PAD(0x55c, 0x118, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR IOMUX_PAD(0x55c, 0x118, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_CLK__GPIO2_26 IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x55c, 0x118, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_I2C2_DAT__I2C2_SDA IOMUX_PAD(0x560, 0x11c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_DAT__CAN1_RXCAN IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_DAT__GPIO2_27 IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x560, 0x11c, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD IOMUX_PAD(0x564, 0x120, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_STXD4__GPIO2_28 IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL) +#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 IOMUX_PAD(0x564, 0x120, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD IOMUX_PAD(0x568, 0x124, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SRXD4__GPIO2_29 IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL) +#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 IOMUX_PAD(0x568, 0x124, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC IOMUX_PAD(0x56c, 0x128, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK4__GPIO2_30 IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 IOMUX_PAD(0x56c, 0x128, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS IOMUX_PAD(0x570, 0x12c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_STXFS4__GPIO2_31 IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL) +#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 IOMUX_PAD(0x570, 0x12c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD IOMUX_PAD(0x574, 0x130, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x574, 0x130, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_STXD5__CSPI2_MOSI IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL) +#define MX35_PAD_STXD5__GPIO1_0 IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL) +#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 IOMUX_PAD(0x574, 0x130, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD IOMUX_PAD(0x578, 0x134, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL) +#define MX35_PAD_SRXD5__CSPI2_MISO IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL) +#define MX35_PAD_SRXD5__GPIO1_1 IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL) +#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 IOMUX_PAD(0x578, 0x134, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC IOMUX_PAD(0x57c, 0x138, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK5__CSPI2_SCLK IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK5__GPIO1_2 IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 IOMUX_PAD(0x57c, 0x138, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS IOMUX_PAD(0x580, 0x13c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_STXFS5__CSPI2_RDY IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL) +#define MX35_PAD_STXFS5__GPIO1_3 IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL) +#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 IOMUX_PAD(0x580, 0x13c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SCKR__ESAI_SCKR IOMUX_PAD(0x584, 0x140, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SCKR__GPIO1_4 IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL) +#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 IOMUX_PAD(0x584, 0x140, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FSR__ESAI_FSR IOMUX_PAD(0x588, 0x144, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FSR__GPIO1_5 IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL) +#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 IOMUX_PAD(0x588, 0x144, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_HCKR__ESAI_HCKR IOMUX_PAD(0x58c, 0x148, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS IOMUX_PAD(0x58c, 0x148, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKR__CSPI2_SS0 IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKR__IPU_FLASH_STROBE IOMUX_PAD(0x58c, 0x148, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKR__GPIO1_6 IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL) +#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 IOMUX_PAD(0x58c, 0x148, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SCKT__ESAI_SCKT IOMUX_PAD(0x590, 0x14c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SCKT__GPIO1_7 IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL) +#define MX35_PAD_SCKT__IPU_CSI_D_0 IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL) +#define MX35_PAD_SCKT__KPP_ROW_2 IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL) + +#define MX35_PAD_FST__ESAI_FST IOMUX_PAD(0x594, 0x150, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FST__GPIO1_8 IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL) +#define MX35_PAD_FST__IPU_CSI_D_1 IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL) +#define MX35_PAD_FST__KPP_ROW_3 IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL) + +#define MX35_PAD_HCKT__ESAI_HCKT IOMUX_PAD(0x598, 0x154, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKT__GPIO1_9 IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKT__IPU_CSI_D_2 IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKT__KPP_COL_3 IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL) + +#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0 IOMUX_PAD(0x59c, 0x158, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC IOMUX_PAD(0x59c, 0x158, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__CSPI2_SS2 IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__CAN2_TXCAN IOMUX_PAD(0x59c, 0x158, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__UART2_DTR IOMUX_PAD(0x59c, 0x158, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__GPIO1_10 IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 IOMUX_PAD(0x59c, 0x158, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1 IOMUX_PAD(0x5a0, 0x15c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS IOMUX_PAD(0x5a0, 0x15c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__CSPI2_SS3 IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__CAN2_RXCAN IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__UART2_DSR IOMUX_PAD(0x5a0, 0x15c, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__GPIO1_11 IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__IPU_CSI_D_3 IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__KPP_ROW_0 IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL) + +#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2 IOMUX_PAD(0x5a4, 0x160, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX3_RX2__I2C3_SCL IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL) +#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1 IOMUX_PAD(0x5a4, 0x160, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX3_RX2__GPIO1_12 IOMUX_PAD(0x5a4, 0x160, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX3_RX2__IPU_CSI_D_4 IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL) +#define MX35_PAD_TX3_RX2__KPP_ROW_1 IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL) + +#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3 IOMUX_PAD(0x5a8, 0x164, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX2_RX3__I2C3_SDA IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL) +#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2 IOMUX_PAD(0x5a8, 0x164, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX2_RX3__GPIO1_13 IOMUX_PAD(0x5a8, 0x164, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX2_RX3__IPU_CSI_D_5 IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL) +#define MX35_PAD_TX2_RX3__KPP_COL_0 IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL) + +#define MX35_PAD_TX1__ESAI_TX1 IOMUX_PAD(0x5ac, 0x168, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX1__CCM_PMIC_RDY IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL) +#define MX35_PAD_TX1__CSPI1_SS2 IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL) +#define MX35_PAD_TX1__EMI_NANDF_CE3 IOMUX_PAD(0x5ac, 0x168, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX1__UART2_RI IOMUX_PAD(0x5ac, 0x168, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX1__GPIO1_14 IOMUX_PAD(0x5ac, 0x168, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX1__IPU_CSI_D_6 IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL) +#define MX35_PAD_TX1__KPP_COL_1 IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL) + +#define MX35_PAD_TX0__ESAI_TX0 IOMUX_PAD(0x5b0, 0x16c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL) +#define MX35_PAD_TX0__CSPI1_SS3 IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL) +#define MX35_PAD_TX0__EMI_DTACK_B IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL) +#define MX35_PAD_TX0__UART2_DCD IOMUX_PAD(0x5b0, 0x16c, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX0__GPIO1_15 IOMUX_PAD(0x5b0, 0x16c, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX0__IPU_CSI_D_7 IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL) +#define MX35_PAD_TX0__KPP_COL_2 IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x5b4, 0x170, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_MOSI__GPIO1_16 IOMUX_PAD(0x5b4, 0x170, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 IOMUX_PAD(0x5b4, 0x170, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x5b8, 0x174, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_MISO__GPIO1_17 IOMUX_PAD(0x5b8, 0x174, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 IOMUX_PAD(0x5b8, 0x174, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x5bc, 0x178, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS0__OWIRE_LINE IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS0__CSPI2_SS3 IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS0__GPIO1_18 IOMUX_PAD(0x5bc, 0x178, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 IOMUX_PAD(0x5bc, 0x178, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x5c0, 0x17c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS1__PWM_PWMO IOMUX_PAD(0x5c0, 0x17c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS1__CCM_CLK32K IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS1__GPIO1_19 IOMUX_PAD(0x5c0, 0x17c, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 IOMUX_PAD(0x5c0, 0x17c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 IOMUX_PAD(0x5c0, 0x17c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x5c4, 0x180, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SCLK__GPIO3_4 IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 IOMUX_PAD(0x5c4, 0x180, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 IOMUX_PAD(0x5c4, 0x180, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY IOMUX_PAD(0x5c8, 0x184, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 IOMUX_PAD(0x5c8, 0x184, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 IOMUX_PAD(0x5c8, 0x184, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RXD1__UART1_RXD_MUX IOMUX_PAD(0x5cc, 0x188, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RXD1__CSPI2_MOSI IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL) +#define MX35_PAD_RXD1__KPP_COL_4 IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL) +#define MX35_PAD_RXD1__GPIO3_6 IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL) +#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 IOMUX_PAD(0x5cc, 0x188, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TXD1__UART1_TXD_MUX IOMUX_PAD(0x5d0, 0x18c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TXD1__CSPI2_MISO IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL) +#define MX35_PAD_TXD1__KPP_COL_5 IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL) +#define MX35_PAD_TXD1__GPIO3_7 IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL) +#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 IOMUX_PAD(0x5d0, 0x18c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RTS1__UART1_RTS IOMUX_PAD(0x5d4, 0x190, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS1__CSPI2_SCLK IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS1__I2C3_SCL IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS1__IPU_CSI_D_0 IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS1__KPP_COL_6 IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS1__GPIO3_8 IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS1__EMI_NANDF_CE1 IOMUX_PAD(0x5d4, 0x190, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 IOMUX_PAD(0x5d4, 0x190, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CTS1__UART1_CTS IOMUX_PAD(0x5d8, 0x194, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS1__CSPI2_RDY IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL) +#define MX35_PAD_CTS1__I2C3_SDA IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL) +#define MX35_PAD_CTS1__IPU_CSI_D_1 IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL) +#define MX35_PAD_CTS1__KPP_COL_7 IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS1__GPIO3_9 IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS1__EMI_NANDF_CE2 IOMUX_PAD(0x5d8, 0x194, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 IOMUX_PAD(0x5d8, 0x194, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RXD2__UART2_RXD_MUX IOMUX_PAD(0x5dc, 0x198, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RXD2__KPP_ROW_4 IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL) +#define MX35_PAD_RXD2__GPIO3_10 IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL) + +#define MX35_PAD_TXD2__UART2_TXD_MUX IOMUX_PAD(0x5e0, 0x19c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL) +#define MX35_PAD_TXD2__KPP_ROW_5 IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL) +#define MX35_PAD_TXD2__GPIO3_11 IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RTS2__UART2_RTS IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1 IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS2__CAN2_RXCAN IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS2__IPU_CSI_D_2 IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS2__KPP_ROW_6 IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS2__GPIO3_12 IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS2__UART3_RXD_MUX IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CTS2__UART2_CTS IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__CAN2_TXCAN IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__IPU_CSI_D_3 IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL) +#define MX35_PAD_CTS2__KPP_ROW_7 IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__GPIO3_13 IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__UART3_TXD_MUX IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RTCK__ARM11P_TOP_RTCK IOMUX_PAD(0x5ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TCK__SJC_TCK IOMUX_PAD(0x5f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TMS__SJC_TMS IOMUX_PAD(0x5f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TDI__SJC_TDI IOMUX_PAD(0x5f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TDO__SJC_TDO IOMUX_PAD(0x5fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TRSTB__SJC_TRSTB IOMUX_PAD(0x600, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_DE_B__SJC_DE_B IOMUX_PAD(0x604, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SJC_MOD__SJC_MOD IOMUX_PAD(0x608, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR IOMUX_PAD(0x60c, 0x1a8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR IOMUX_PAD(0x60c, 0x1a8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_USBOTG_PWR__GPIO3_14 IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL) + +#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC IOMUX_PAD(0x610, 0x1ac, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL) +#define MX35_PAD_USBOTG_OC__GPIO3_15 IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD0__IPU_DISPB_DAT_0 IOMUX_PAD(0x614, 0x1b0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD0__GPIO2_0 IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL) +#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 IOMUX_PAD(0x614, 0x1b0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD1__IPU_DISPB_DAT_1 IOMUX_PAD(0x618, 0x1b4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD1__GPIO2_1 IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL) +#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 IOMUX_PAD(0x618, 0x1b4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD2__IPU_DISPB_DAT_2 IOMUX_PAD(0x61c, 0x1b8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD2__GPIO2_2 IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 IOMUX_PAD(0x61c, 0x1b8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD3__IPU_DISPB_DAT_3 IOMUX_PAD(0x620, 0x1bc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD3__GPIO2_3 IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL) +#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 IOMUX_PAD(0x620, 0x1bc, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD4__IPU_DISPB_DAT_4 IOMUX_PAD(0x624, 0x1c0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD4__GPIO2_4 IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 IOMUX_PAD(0x624, 0x1c0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD5__IPU_DISPB_DAT_5 IOMUX_PAD(0x628, 0x1c4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD5__GPIO2_5 IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL) +#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 IOMUX_PAD(0x628, 0x1c4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD6__IPU_DISPB_DAT_6 IOMUX_PAD(0x62c, 0x1c8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD6__GPIO2_6 IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL) +#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 IOMUX_PAD(0x62c, 0x1c8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD7__IPU_DISPB_DAT_7 IOMUX_PAD(0x630, 0x1cc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD7__GPIO2_7 IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL) +#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 IOMUX_PAD(0x630, 0x1cc, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD8__IPU_DISPB_DAT_8 IOMUX_PAD(0x634, 0x1d0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD8__GPIO2_8 IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD9__IPU_DISPB_DAT_9 IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4 0, NO_PAD_CTRL) +#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD10__IPU_DISPB_DAT_10 IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD10__GPIO2_10 IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL) +#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 IOMUX_PAD(0x63c, 0x1d8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD11__IPU_DISPB_DAT_11 IOMUX_PAD(0x640, 0x1dc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD11__GPIO2_11 IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL) +#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 IOMUX_PAD(0x640, 0x1dc, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4 IOMUX_PAD(0x640, 0x1dc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD12__IPU_DISPB_DAT_12 IOMUX_PAD(0x644, 0x1e0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD12__GPIO2_12 IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL) +#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 IOMUX_PAD(0x644, 0x1e0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5 IOMUX_PAD(0x644, 0x1e0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD13__IPU_DISPB_DAT_13 IOMUX_PAD(0x648, 0x1e4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD13__GPIO2_13 IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL) +#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 IOMUX_PAD(0x648, 0x1e4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6 IOMUX_PAD(0x648, 0x1e4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD14__IPU_DISPB_DAT_14 IOMUX_PAD(0x64c, 0x1e8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD14__GPIO2_14 IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL) +#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x64c, 0x1e8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7 IOMUX_PAD(0x64c, 0x1e8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD15__IPU_DISPB_DAT_15 IOMUX_PAD(0x650, 0x1ec, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD15__GPIO2_15 IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL) +#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x650, 0x1ec, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8 IOMUX_PAD(0x650, 0x1ec, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD16__IPU_DISPB_DAT_16 IOMUX_PAD(0x654, 0x1f0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL) +#define MX35_PAD_LD16__GPIO2_16 IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL) +#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x654, 0x1f0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9 IOMUX_PAD(0x654, 0x1f0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD17__IPU_DISPB_DAT_17 IOMUX_PAD(0x658, 0x1f4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD17__IPU_DISPB_CS2 IOMUX_PAD(0x658, 0x1f4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD17__GPIO2_17 IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL) +#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x658, 0x1f4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10 IOMUX_PAD(0x658, 0x1f4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD18__IPU_DISPB_DAT_18 IOMUX_PAD(0x65c, 0x1f8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL) +#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL) +#define MX35_PAD_LD18__ESDHC3_CMD IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL) +#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD18__GPIO3_24 IOMUX_PAD(0x65c, 0x1f8, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x65c, 0x1f8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11 IOMUX_PAD(0x65c, 0x1f8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD19__IPU_DISPB_DAT_19 IOMUX_PAD(0x660, 0x1fc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__IPU_DISPB_BCLK IOMUX_PAD(0x660, 0x1fc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__IPU_DISPB_CS1 IOMUX_PAD(0x660, 0x1fc, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__ESDHC3_CLK IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__GPIO3_25 IOMUX_PAD(0x660, 0x1fc, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x660, 0x1fc, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12 IOMUX_PAD(0x660, 0x1fc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD20__IPU_DISPB_DAT_20 IOMUX_PAD(0x664, 0x200, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__IPU_DISPB_CS0 IOMUX_PAD(0x664, 0x200, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__IPU_DISPB_SD_CLK IOMUX_PAD(0x664, 0x200, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__ESDHC3_DAT0 IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__GPIO3_26 IOMUX_PAD(0x664, 0x200, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 IOMUX_PAD(0x664, 0x200, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13 IOMUX_PAD(0x664, 0x200, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD21__IPU_DISPB_DAT_21 IOMUX_PAD(0x668, 0x204, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__IPU_DISPB_PAR_RS IOMUX_PAD(0x668, 0x204, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__IPU_DISPB_SER_RS IOMUX_PAD(0x668, 0x204, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__ESDHC3_DAT1 IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__USB_TOP_USBOTG_STP IOMUX_PAD(0x668, 0x204, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__GPIO3_27 IOMUX_PAD(0x668, 0x204, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x668, 0x204, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14 IOMUX_PAD(0x668, 0x204, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD22__IPU_DISPB_DAT_22 IOMUX_PAD(0x66c, 0x208, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__IPU_DISPB_WR IOMUX_PAD(0x66c, 0x208, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__IPU_DISPB_SD_D_I IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__ESDHC3_DAT2 IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__GPIO3_28 IOMUX_PAD(0x66c, 0x208, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x66c, 0x208, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__ARM11P_TOP_TRCTL IOMUX_PAD(0x66c, 0x208, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD23__IPU_DISPB_DAT_23 IOMUX_PAD(0x670, 0x20c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__IPU_DISPB_RD IOMUX_PAD(0x670, 0x20c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL) +#define MX35_PAD_LD23__ESDHC3_DAT3 IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__GPIO3_29 IOMUX_PAD(0x670, 0x20c, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x670, 0x20c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__ARM11P_TOP_TRCLK IOMUX_PAD(0x670, 0x20c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC IOMUX_PAD(0x674, 0x210, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL) +#define MX35_PAD_D3_HSYNC__GPIO3_30 IOMUX_PAD(0x674, 0x210, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x674, 0x210, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 IOMUX_PAD(0x674, 0x210, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK IOMUX_PAD(0x678, 0x214, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK IOMUX_PAD(0x678, 0x214, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_FPSHIFT__GPIO3_31 IOMUX_PAD(0x678, 0x214, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 IOMUX_PAD(0x678, 0x214, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 IOMUX_PAD(0x678, 0x214, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY IOMUX_PAD(0x67c, 0x218, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O IOMUX_PAD(0x67c, 0x218, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_DRDY__GPIO1_0 IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL) +#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 IOMUX_PAD(0x67c, 0x218, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 IOMUX_PAD(0x67c, 0x218, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR IOMUX_PAD(0x680, 0x21c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CONTRAST__GPIO1_1 IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL) +#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 IOMUX_PAD(0x680, 0x21c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 IOMUX_PAD(0x680, 0x21c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC IOMUX_PAD(0x684, 0x220, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 IOMUX_PAD(0x684, 0x220, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_VSYNC__GPIO1_2 IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL) +#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD IOMUX_PAD(0x684, 0x220, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 IOMUX_PAD(0x684, 0x220, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV IOMUX_PAD(0x688, 0x224, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS IOMUX_PAD(0x688, 0x224, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_REV__GPIO1_3 IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL) +#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x688, 0x224, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 IOMUX_PAD(0x688, 0x224, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS IOMUX_PAD(0x68c, 0x228, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_CLS__IPU_DISPB_CS2 IOMUX_PAD(0x68c, 0x228, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_CLS__GPIO1_4 IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL) +#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x68c, 0x228, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 IOMUX_PAD(0x68c, 0x228, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL IOMUX_PAD(0x690, 0x22c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL) +#define MX35_PAD_D3_SPL__GPIO1_5 IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL) +#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x694, 0x230, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CMD__MSHC_SCLK IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL) +#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CMD__GPIO1_6 IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL) +#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x698, 0x234, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CLK__MSHC_BS IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CLK__GPIO1_7 IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL) +#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x69c, 0x238, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA0__MSHC_DATA_0 IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA0__GPIO1_8 IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x6a0, 0x23c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA1__MSHC_DATA_1 IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA1__GPIO1_9 IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x6a4, 0x240, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA2__MSHC_DATA_2 IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA2__GPIO1_10 IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x6a8, 0x244, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA3__MSHC_DATA_3 IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA3__GPIO1_11 IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 IOMUX_PAD(0x6a8, 0x244, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x6ac, 0x248, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__I2C3_SCL IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__ESDHC1_DAT4 IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__IPU_CSI_D_2 IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__GPIO2_0 IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x6ac, 0x248, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL) + +#define MX35_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x6b0, 0x24c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__I2C3_SDA IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__ESDHC1_DAT5 IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__IPU_CSI_D_3 IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__GPIO2_1 IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2 IOMUX_PAD(0x6b0, 0x24c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x6b4, 0x250, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__GPIO2_2 IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL) + +#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x6b8, 0x254, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX IOMUX_PAD(0x6b8, 0x254, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA1__GPIO2_3 IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL) + +#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x6bc, 0x258, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA2__UART3_RTS IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA2__CAN1_RXCAN IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6 IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA2__GPIO2_4 IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL) + +#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x6c0, 0x25c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA3__UART3_CTS IOMUX_PAD(0x6c0, 0x25c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA3__CAN1_TXCAN IOMUX_PAD(0x6c0, 0x25c, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7 IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA3__GPIO2_5 IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL) + +#define MX35_PAD_ATA_CS0__ATA_CS0 IOMUX_PAD(0x6c4, 0x260, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS0__CSPI1_SS3 IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1 IOMUX_PAD(0x6c4, 0x260, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS0__GPIO2_6 IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS0__IPU_DIAGB_0 IOMUX_PAD(0x6c4, 0x260, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 IOMUX_PAD(0x6c4, 0x260, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_CS1__ATA_CS1 IOMUX_PAD(0x6c8, 0x264, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2 IOMUX_PAD(0x6c8, 0x264, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS1__CSPI2_SS0 IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS1__GPIO2_7 IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS1__IPU_DIAGB_1 IOMUX_PAD(0x6c8, 0x264, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 IOMUX_PAD(0x6c8, 0x264, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DIOR__ATA_DIOR IOMUX_PAD(0x6cc, 0x268, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0 IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 IOMUX_PAD(0x6cc, 0x268, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__CSPI2_SS1 IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__GPIO2_8 IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2 IOMUX_PAD(0x6cc, 0x268, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 IOMUX_PAD(0x6cc, 0x268, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DIOW__ATA_DIOW IOMUX_PAD(0x6d0, 0x26c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP IOMUX_PAD(0x6d0, 0x26c, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 IOMUX_PAD(0x6d0, 0x26c, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__CSPI2_MOSI IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__GPIO2_9 IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3 IOMUX_PAD(0x6d0, 0x26c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 IOMUX_PAD(0x6d0, 0x26c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DMACK__ATA_DMACK IOMUX_PAD(0x6d4, 0x270, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2 IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__CSPI2_MISO IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__GPIO2_10 IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4 IOMUX_PAD(0x6d4, 0x270, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 IOMUX_PAD(0x6d4, 0x270, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_RESET_B__ATA_RESET_B IOMUX_PAD(0x6d8, 0x274, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O IOMUX_PAD(0x6d8, 0x274, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__CSPI2_RDY IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__GPIO2_11 IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 IOMUX_PAD(0x6d8, 0x274, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 IOMUX_PAD(0x6d8, 0x274, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_IORDY__ATA_IORDY IOMUX_PAD(0x6dc, 0x278, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4 IOMUX_PAD(0x6dc, 0x278, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4 IOMUX_PAD(0x6dc, 0x278, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__GPIO2_12 IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6 IOMUX_PAD(0x6dc, 0x278, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 IOMUX_PAD(0x6dc, 0x278, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA0__ATA_DATA_0 IOMUX_PAD(0x6e0, 0x27c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5 IOMUX_PAD(0x6e0, 0x27c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5 IOMUX_PAD(0x6e0, 0x27c, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__GPIO2_13 IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7 IOMUX_PAD(0x6e0, 0x27c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 IOMUX_PAD(0x6e0, 0x27c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA1__ATA_DATA_1 IOMUX_PAD(0x6e4, 0x280, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6 IOMUX_PAD(0x6e4, 0x280, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK IOMUX_PAD(0x6e4, 0x280, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6 IOMUX_PAD(0x6e4, 0x280, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__GPIO2_14 IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8 IOMUX_PAD(0x6e4, 0x280, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 IOMUX_PAD(0x6e4, 0x280, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA2__ATA_DATA_2 IOMUX_PAD(0x6e8, 0x284, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7 IOMUX_PAD(0x6e8, 0x284, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS IOMUX_PAD(0x6e8, 0x284, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7 IOMUX_PAD(0x6e8, 0x284, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__GPIO2_15 IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA3__ATA_DATA_3 IOMUX_PAD(0x6e8, 0x288, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__ESDHC3_CLK IOMUX_PAD(0x6e8, 0x288, 1, 0x814, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x6e8, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__CSPI2_SCLK IOMUX_PAD(0x6e8, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__GPIO2_16 IOMUX_PAD(0x6e8, 0x288, 5, 0x884, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 IOMUX_PAD(0x6e8, 0x288, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 IOMUX_PAD(0x6e8, 0x288, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA4__ATA_DATA_4 IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA4__ESDHC3_CMD IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA4__GPIO2_17 IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11 IOMUX_PAD(0x6f0, 0x28c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 IOMUX_PAD(0x6f0, 0x28c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA5__ATA_DATA_5 IOMUX_PAD(0x6f4, 0x290, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA5__GPIO2_18 IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12 IOMUX_PAD(0x6f4, 0x290, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 IOMUX_PAD(0x6f4, 0x290, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA6__ATA_DATA_6 IOMUX_PAD(0x6f8, 0x294, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA6__CAN1_TXCAN IOMUX_PAD(0x6f8, 0x294, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA6__UART1_DTR IOMUX_PAD(0x6f8, 0x294, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA6__GPIO2_19 IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13 IOMUX_PAD(0x6f8, 0x294, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA7__ATA_DATA_7 IOMUX_PAD(0x6fc, 0x298, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA7__CAN1_RXCAN IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA7__UART1_DSR IOMUX_PAD(0x6fc, 0x298, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA7__GPIO2_20 IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14 IOMUX_PAD(0x6fc, 0x298, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA8__ATA_DATA_8 IOMUX_PAD(0x700, 0x29c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA8__UART3_RTS IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA8__UART1_RI IOMUX_PAD(0x700, 0x29c, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA8__GPIO2_21 IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15 IOMUX_PAD(0x700, 0x29c, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA9__ATA_DATA_9 IOMUX_PAD(0x704, 0x2a0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA9__UART3_CTS IOMUX_PAD(0x704, 0x2a0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA9__UART1_DCD IOMUX_PAD(0x704, 0x2a0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA9__GPIO2_22 IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16 IOMUX_PAD(0x704, 0x2a0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA10__ATA_DATA_10 IOMUX_PAD(0x708, 0x2a4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA10__GPIO2_23 IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17 IOMUX_PAD(0x708, 0x2a4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA11__ATA_DATA_11 IOMUX_PAD(0x70c, 0x2a8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX IOMUX_PAD(0x70c, 0x2a8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA11__GPIO2_24 IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18 IOMUX_PAD(0x70c, 0x2a8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA12__ATA_DATA_12 IOMUX_PAD(0x710, 0x2ac, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA12__I2C3_SCL IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA12__GPIO2_25 IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19 IOMUX_PAD(0x710, 0x2ac, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA13__ATA_DATA_13 IOMUX_PAD(0x714, 0x2b0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA13__I2C3_SDA IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA13__GPIO2_26 IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20 IOMUX_PAD(0x714, 0x2b0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA14__ATA_DATA_14 IOMUX_PAD(0x718, 0x2b4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA14__KPP_ROW_0 IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA14__GPIO2_27 IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21 IOMUX_PAD(0x718, 0x2b4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA15__ATA_DATA_15 IOMUX_PAD(0x71c, 0x2b8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA15__KPP_ROW_1 IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA15__GPIO2_28 IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22 IOMUX_PAD(0x71c, 0x2b8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_INTRQ__ATA_INTRQ IOMUX_PAD(0x720, 0x2bc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL) +#define MX35_PAD_ATA_INTRQ__KPP_ROW_2 IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_INTRQ__GPIO2_29 IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 IOMUX_PAD(0x720, 0x2bc, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN IOMUX_PAD(0x724, 0x2c0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL) +#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_BUFF_EN__GPIO2_30 IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 IOMUX_PAD(0x724, 0x2c0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DMARQ__ATA_DMARQ IOMUX_PAD(0x728, 0x2c4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMARQ__KPP_COL_0 IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMARQ__GPIO2_31 IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 IOMUX_PAD(0x728, 0x2c4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 IOMUX_PAD(0x728, 0x2c4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DA0__ATA_DA_0 IOMUX_PAD(0x72c, 0x2c8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA0__IPU_CSI_D_5 IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA0__KPP_COL_1 IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA0__GPIO3_0 IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA0__IPU_DIAGB_26 IOMUX_PAD(0x72c, 0x2c8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 IOMUX_PAD(0x72c, 0x2c8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DA1__ATA_DA_1 IOMUX_PAD(0x730, 0x2cc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA1__IPU_CSI_D_6 IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA1__KPP_COL_2 IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA1__GPIO3_1 IOMUX_PAD(0x730, 0x2cc, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA1__IPU_DIAGB_27 IOMUX_PAD(0x730, 0x2cc, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 IOMUX_PAD(0x730, 0x2cc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DA2__ATA_DA_2 IOMUX_PAD(0x734, 0x2d0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA2__IPU_CSI_D_7 IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA2__KPP_COL_3 IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA2__GPIO3_2 IOMUX_PAD(0x734, 0x2d0, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA2__IPU_DIAGB_28 IOMUX_PAD(0x734, 0x2d0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 IOMUX_PAD(0x734, 0x2d0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_MLB_CLK__MLB_MLBCLK IOMUX_PAD(0x738, 0x2d4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_MLB_CLK__GPIO3_3 IOMUX_PAD(0x738, 0x2d4, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_MLB_DAT__MLB_MLBDAT IOMUX_PAD(0x73c, 0x2d8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_MLB_DAT__GPIO3_4 IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL) + +#define MX35_PAD_MLB_SIG__MLB_MLBSIG IOMUX_PAD(0x740, 0x2dc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_MLB_SIG__GPIO3_5 IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x744, 0x2e0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__GPIO3_6 IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 IOMUX_PAD(0x744, 0x2e0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK IOMUX_PAD(0x748, 0x2e4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX IOMUX_PAD(0x748, 0x2e4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP IOMUX_PAD(0x748, 0x2e4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__GPIO3_7 IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 IOMUX_PAD(0x748, 0x2e4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x74c, 0x2e8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__UART3_RTS IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__GPIO3_8 IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK IOMUX_PAD(0x74c, 0x2e8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 IOMUX_PAD(0x74c, 0x2e8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_COL__FEC_COL IOMUX_PAD(0x750, 0x2ec, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__ESDHC1_DAT7 IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__UART3_CTS IOMUX_PAD(0x750, 0x2ec, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__CSPI2_RDY IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__GPIO3_9 IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS IOMUX_PAD(0x750, 0x2ec, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 IOMUX_PAD(0x750, 0x2ec, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0 IOMUX_PAD(0x754, 0x2f0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__PWM_PWMO IOMUX_PAD(0x754, 0x2f0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__UART3_DTR IOMUX_PAD(0x754, 0x2f0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__CSPI2_SS0 IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__GPIO3_10 IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 IOMUX_PAD(0x754, 0x2f0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 IOMUX_PAD(0x754, 0x2f0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0 IOMUX_PAD(0x758, 0x2f4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x758, 0x2f4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__UART3_DSR IOMUX_PAD(0x758, 0x2f4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__CSPI2_SS1 IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__GPIO3_11 IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 IOMUX_PAD(0x758, 0x2f4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 IOMUX_PAD(0x758, 0x2f4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x75c, 0x2f8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__UART3_RI IOMUX_PAD(0x75c, 0x2f8, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__GPIO3_12 IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS IOMUX_PAD(0x75c, 0x2f8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 IOMUX_PAD(0x75c, 0x2f8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x760, 0x2fc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__CAN2_TXCAN IOMUX_PAD(0x760, 0x2fc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__UART3_DCD IOMUX_PAD(0x760, 0x2fc, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__GPIO3_13 IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__IPU_DISPB_WR IOMUX_PAD(0x760, 0x2fc, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 IOMUX_PAD(0x760, 0x2fc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x764, 0x300, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDIO__CAN2_RXCAN IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDIO__GPIO3_14 IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD IOMUX_PAD(0x764, 0x300, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 IOMUX_PAD(0x764, 0x300, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR IOMUX_PAD(0x768, 0x304, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__GPIO3_15 IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 IOMUX_PAD(0x768, 0x304, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR IOMUX_PAD(0x76c, 0x308, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_ERR__KPP_COL_4 IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_ERR__GPIO3_16 IOMUX_PAD(0x76c, 0x308, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL) + +#define MX35_PAD_FEC_CRS__FEC_CRS IOMUX_PAD(0x770, 0x30c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_CRS__IPU_CSI_D_1 IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR IOMUX_PAD(0x770, 0x30c, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_CRS__KPP_COL_5 IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_CRS__GPIO3_17 IOMUX_PAD(0x770, 0x30c, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE IOMUX_PAD(0x770, 0x30c, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1 IOMUX_PAD(0x774, 0x310, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC IOMUX_PAD(0x774, 0x310, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__KPP_COL_6 IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__GPIO3_18 IOMUX_PAD(0x774, 0x310, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 IOMUX_PAD(0x774, 0x310, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1 IOMUX_PAD(0x778, 0x314, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA1__KPP_COL_7 IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA1__GPIO3_19 IOMUX_PAD(0x778, 0x314, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 IOMUX_PAD(0x778, 0x314, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2 IOMUX_PAD(0x77c, 0x318, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA2__KPP_ROW_4 IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA2__GPIO3_20 IOMUX_PAD(0x77c, 0x318, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2 IOMUX_PAD(0x780, 0x31c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA2__KPP_ROW_5 IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA2__GPIO3_21 IOMUX_PAD(0x780, 0x31c, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3 IOMUX_PAD(0x784, 0x320, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA3__KPP_ROW_6 IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA3__GPIO3_22 IOMUX_PAD(0x784, 0x320, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3 IOMUX_PAD(0x788, 0x324, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA3__KPP_ROW_7 IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA3__GPIO3_23 IOMUX_PAD(0x788, 0x324, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK IOMUX_PAD(0x78c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TEST_MODE__TCU_TEST_MODE IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + + +#endif /* __MACH_IOMUX_MX35_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h new file mode 100644 index 00000000000..7cd84547658 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * <armlinux@phytec.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_IOMUX_V3_H__ +#define __MACH_IOMUX_V3_H__ + +/* + * build IOMUX_PAD structure + * + * This iomux scheme is based around pads, which are the physical balls + * on the processor. + * + * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls + * things like driving strength and pullup/pulldown. + * - Each pad can have but not necessarily does have an output routing register + * (IOMUXC_SW_MUX_CTL_PAD_x). + * - Each pad can have but not necessarily does have an input routing register + * (IOMUXC_x_SELECT_INPUT) + * + * The three register sets do not have a fixed offset to each other, + * hence we order this table by pad control registers (which all pads + * have) and put the optional i/o routing registers into additional + * fields. + * + * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> + * If <padname> or <padmode> refers to a GPIO, it is named + * GPIO_<unit>_<num> + * + */ + +struct pad_desc { + unsigned mux_ctrl_ofs:12; /* IOMUXC_SW_MUX_CTL_PAD offset */ + unsigned mux_mode:8; + unsigned pad_ctrl_ofs:12; /* IOMUXC_SW_PAD_CTRL offset */ +#define NO_PAD_CTRL (1 << 16) + unsigned pad_ctrl:17; + unsigned select_input_ofs:12; /* IOMUXC_SELECT_INPUT offset */ + unsigned select_input:3; +}; + +#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \ + _select_input, _pad_ctrl) \ + { \ + .mux_ctrl_ofs = _mux_ctrl_ofs, \ + .mux_mode = _mux_mode, \ + .pad_ctrl_ofs = _pad_ctrl_ofs, \ + .pad_ctrl = _pad_ctrl, \ + .select_input_ofs = _select_input_ofs, \ + .select_input = _select_input, \ + } + +/* + * Use to set PAD control + */ +#define PAD_CTL_DRIVE_VOLTAGE_3_3_V 0 +#define PAD_CTL_DRIVE_VOLTAGE_1_8_V 1 + +#define PAD_CTL_NO_HYSTERESIS 0 +#define PAD_CTL_HYSTERESIS 1 + +#define PAD_CTL_PULL_DISABLED 0x0 +#define PAD_CTL_PULL_KEEPER 0xa +#define PAD_CTL_PULL_DOWN_100K 0xc +#define PAD_CTL_PULL_UP_47K 0xd +#define PAD_CTL_PULL_UP_100K 0xe +#define PAD_CTL_PULL_UP_22K 0xf + +#define PAD_CTL_OUTPUT_CMOS 0 +#define PAD_CTL_OUTPUT_OPEN_DRAIN 1 + +#define PAD_CTL_DRIVE_STRENGTH_NORM 0 +#define PAD_CTL_DRIVE_STRENGTH_HIGH 1 +#define PAD_CTL_DRIVE_STRENGTH_MAX 2 + +#define PAD_CTL_SLEW_RATE_SLOW 0 +#define PAD_CTL_SLEW_RATE_FAST 1 + +/* + * setups a single pad: + * - reserves the pad so that it is not claimed by another driver + * - setups the iomux according to the configuration + */ +int mxc_iomux_v3_setup_pad(struct pad_desc *pad); + +/* + * setups mutliple pads + * convenient way to call the above function with tables + */ +int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count); + +/* + * releases a single pad: + * - make it available for a future use by another driver + * - DOES NOT reconfigure the IOMUX in its reset state + */ +void mxc_iomux_v3_release_pad(struct pad_desc *pad); + +/* + * releases multiple pads + * convenvient way to call the above function with tables + */ +void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count); + +#endif /* __MACH_IOMUX_V3_H__*/ + diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index eca37d09f3f..6065e00176e 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -32,4 +32,12 @@ #define CONSISTENT_DMA_SIZE SZ_4M #endif /* CONFIG_MX1_VIDEO */ +#if defined(CONFIG_MX3_VIDEO) +/* + * Increase size of DMA-consistent memory region. + * This is required for mx3 camera driver to capture at least two QXGA frames. + */ +#define CONSISTENT_DMA_SIZE SZ_8M +#endif /* CONFIG_MX3_VIDEO */ + #endif /* __ASM_ARCH_MXC_MEMORY_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index b92e02324d8..1000bf330bc 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -179,7 +179,7 @@ #define DMA_REQ_UART1_T 30 #define DMA_REQ_UART1_R 31 -/* mandatory for CONFIG_LL_DEBUG */ +/* mandatory for CONFIG_DEBUG_LL */ #define MXC_LL_UART_PADDR UART1_BASE_ADDR #define MXC_LL_UART_VADDR IO_ADDRESS(UART1_BASE_ADDR) diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index 3878c6085d5..b559a4bb576 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -48,6 +48,9 @@ #define CS4_SIZE SZ_32M #define CS5_BASE_ADDR 0xB6000000 +#define CS5_BASE_ADDR_VIRT 0xF6000000 +#define CS5_SIZE SZ_32M + #define PCMCIA_MEM_BASE_ADDR 0xBC000000 /* @@ -191,6 +194,9 @@ #define CS4_IO_ADDRESS(x) \ (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) +#define CS5_IO_ADDRESS(x) \ + (((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT) + #define X_MEMC_IO_ADDRESS(x) \ (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) diff --git a/arch/arm/plat-mxc/include/mach/mxc_timer.h b/arch/arm/plat-mxc/include/mach/mxc_timer.h deleted file mode 100644 index 6c19a134744..00000000000 --- a/arch/arm/plat-mxc/include/mach/mxc_timer.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * mxc_timer.h - * - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. - */ - -#ifndef __PLAT_MXC_TIMER_H -#define __PLAT_MXC_TIMER_H - -#include <linux/clk.h> -#include <mach/hardware.h> - -#ifdef CONFIG_ARCH_MX1 -#define TIMER_BASE IO_ADDRESS(TIM1_BASE_ADDR) -#define TIMER_INTERRUPT TIM1_INT - -#define TCTL_VAL TCTL_CLK_PCLK1 -#define TCTL_IRQEN (1<<4) -#define TCTL_FRR (1<<8) -#define TCTL_CLK_PCLK1 (1<<1) -#define TCTL_CLK_PCLK1_4 (2<<1) -#define TCTL_CLK_TIN (3<<1) -#define TCTL_CLK_32 (4<<1) - -#define MXC_TCTL 0x00 -#define MXC_TPRER 0x04 -#define MXC_TCMP 0x08 -#define MXC_TCR 0x0c -#define MXC_TCN 0x10 -#define MXC_TSTAT 0x14 -#define TSTAT_CAPT (1<<1) -#define TSTAT_COMP (1<<0) - -static inline void gpt_irq_disable(void) -{ - unsigned int tmp; - - tmp = __raw_readl(TIMER_BASE + MXC_TCTL); - __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL); -} - -static inline void gpt_irq_enable(void) -{ - __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN, - TIMER_BASE + MXC_TCTL); -} - -static void gpt_irq_acknowledge(void) -{ - __raw_writel(0, TIMER_BASE + MXC_TSTAT); -} -#endif /* CONFIG_ARCH_MX1 */ - -#ifdef CONFIG_ARCH_MX2 -#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR) -#define TIMER_INTERRUPT MXC_INT_GPT1 - -#define MXC_TCTL 0x00 -#define TCTL_VAL TCTL_CLK_PCLK1 -#define TCTL_CLK_PCLK1 (1<<1) -#define TCTL_CLK_PCLK1_4 (2<<1) -#define TCTL_IRQEN (1<<4) -#define TCTL_FRR (1<<8) -#define MXC_TPRER 0x04 -#define MXC_TCMP 0x08 -#define MXC_TCR 0x0c -#define MXC_TCN 0x10 -#define MXC_TSTAT 0x14 -#define TSTAT_CAPT (1<<1) -#define TSTAT_COMP (1<<0) - -static inline void gpt_irq_disable(void) -{ - unsigned int tmp; - - tmp = __raw_readl(TIMER_BASE + MXC_TCTL); - __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL); -} - -static inline void gpt_irq_enable(void) -{ - __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN, - TIMER_BASE + MXC_TCTL); -} - -static void gpt_irq_acknowledge(void) -{ - __raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT); -} -#endif /* CONFIG_ARCH_MX2 */ - -#ifdef CONFIG_ARCH_MX3 -#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR) -#define TIMER_INTERRUPT MXC_INT_GPT - -#define MXC_TCTL 0x00 -#define TCTL_VAL (TCTL_CLK_IPG | TCTL_WAITEN) -#define TCTL_CLK_IPG (1<<6) -#define TCTL_FRR (1<<9) -#define TCTL_WAITEN (1<<3) - -#define MXC_TPRER 0x04 -#define MXC_TSTAT 0x08 -#define TSTAT_OF1 (1<<0) -#define TSTAT_OF2 (1<<1) -#define TSTAT_OF3 (1<<2) -#define TSTAT_IF1 (1<<3) -#define TSTAT_IF2 (1<<4) -#define TSTAT_ROV (1<<5) -#define MXC_IR 0x0c -#define MXC_TCMP 0x10 -#define MXC_TCMP2 0x14 -#define MXC_TCMP3 0x18 -#define MXC_TCR 0x1c -#define MXC_TCN 0x24 - -static inline void gpt_irq_disable(void) -{ - __raw_writel(0, TIMER_BASE + MXC_IR); -} - -static inline void gpt_irq_enable(void) -{ - __raw_writel(1<<0, TIMER_BASE + MXC_IR); -} - -static inline void gpt_irq_acknowledge(void) -{ - __raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT); -} -#endif /* CONFIG_ARCH_MX3 */ - -#define TCTL_SWR (1<<15) -#define TCTL_CC (1<<10) -#define TCTL_OM (1<<9) -#define TCTL_CAP_RIS (1<<6) -#define TCTL_CAP_FAL (2<<6) -#define TCTL_CAP_RIS_FAL (3<<6) -#define TCTL_CAP_ENA (1<<5) -#define TCTL_TEN (1<<0) - -#endif diff --git a/arch/arm/plat-mxc/include/mach/usb.h b/arch/arm/plat-mxc/include/mach/usb.h index 2dacb3086f1..be273371f34 100644 --- a/arch/arm/plat-mxc/include/mach/usb.h +++ b/arch/arm/plat-mxc/include/mach/usb.h @@ -17,7 +17,7 @@ struct imxusb_platform_data { int (*init)(struct device *); - int (*exit)(struct device *); + void (*exit)(struct device *); }; #endif /* __ASM_ARCH_MXC_USB */ diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c new file mode 100644 index 00000000000..77a078f9513 --- /dev/null +++ b/arch/arm/plat-mxc/iomux-v3.c @@ -0,0 +1,98 @@ +/* + * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * <armlinux@phytec.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/string.h> +#include <linux/gpio.h> + +#include <mach/hardware.h> +#include <asm/mach/map.h> +#include <mach/iomux-v3.h> + +#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR) + +static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG]; + +/* + * setups a single pin: + * - reserves the pin so that it is not claimed by another driver + * - setups the iomux according to the configuration + */ +int mxc_iomux_v3_setup_pad(struct pad_desc *pad) +{ + unsigned int pad_ofs = pad->pad_ctrl_ofs; + + if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map)) + return -EBUSY; + if (pad->mux_ctrl_ofs) + __raw_writel(pad->mux_mode, IOMUX_BASE + pad->mux_ctrl_ofs); + + if (pad->select_input_ofs) + __raw_writel(pad->select_input, + IOMUX_BASE + pad->select_input_ofs); + + if (!(pad->pad_ctrl & NO_PAD_CTRL)) + __raw_writel(pad->pad_ctrl, IOMUX_BASE + pad->pad_ctrl_ofs); + return 0; +} +EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); + +int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count) +{ + struct pad_desc *p = pad_list; + int i; + int ret; + + for (i = 0; i < count; i++) { + ret = mxc_iomux_v3_setup_pad(p); + if (ret) + goto setup_error; + p++; + } + return 0; + +setup_error: + mxc_iomux_v3_release_multiple_pads(pad_list, i); + return ret; +} +EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads); + +void mxc_iomux_v3_release_pad(struct pad_desc *pad) +{ + unsigned int pad_ofs = pad->pad_ctrl_ofs; + + clear_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map); +} +EXPORT_SYMBOL(mxc_iomux_v3_release_pad); + +void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count) +{ + struct pad_desc *p = pad_list; + int i; + + for (i = 0; i < count; i++) { + mxc_iomux_v3_release_pad(p); + p++; + } +} +EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads); diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c index 0fb68a531f5..8aee76304f8 100644 --- a/arch/arm/plat-mxc/irq.c +++ b/arch/arm/plat-mxc/irq.c @@ -24,31 +24,27 @@ #include <asm/mach/irq.h> #include <mach/hardware.h> -#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR) -#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */ -#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */ -#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */ -#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */ -#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */ -#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */ -#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */ -#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */ -#define AVIC_NIPRIORITY(x) (AVIC_BASE + (0x20 + 4 * (7 - (x)))) /* int priority */ -#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */ -#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */ -#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */ -#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */ -#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */ -#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */ -#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */ -#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */ -#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */ -#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */ - -#define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20) -#define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24) -#define IIM_PROD_REV_SH 3 -#define IIM_PROD_REV_LEN 5 +#define AVIC_INTCNTL 0x00 /* int control reg */ +#define AVIC_NIMASK 0x04 /* int mask reg */ +#define AVIC_INTENNUM 0x08 /* int enable number reg */ +#define AVIC_INTDISNUM 0x0C /* int disable number reg */ +#define AVIC_INTENABLEH 0x10 /* int enable reg high */ +#define AVIC_INTENABLEL 0x14 /* int enable reg low */ +#define AVIC_INTTYPEH 0x18 /* int type reg high */ +#define AVIC_INTTYPEL 0x1C /* int type reg low */ +#define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */ +#define AVIC_NIVECSR 0x40 /* norm int vector/status */ +#define AVIC_FIVECSR 0x44 /* fast int vector/status */ +#define AVIC_INTSRCH 0x48 /* int source reg high */ +#define AVIC_INTSRCL 0x4C /* int source reg low */ +#define AVIC_INTFRCH 0x50 /* int force reg high */ +#define AVIC_INTFRCL 0x54 /* int force reg low */ +#define AVIC_NIPNDH 0x58 /* norm int pending high */ +#define AVIC_NIPNDL 0x5C /* norm int pending low */ +#define AVIC_FIPNDH 0x60 /* fast int pending high */ +#define AVIC_FIPNDL 0x64 /* fast int pending low */ + +static void __iomem *avic_base; int imx_irq_set_priority(unsigned char irq, unsigned char prio) { @@ -59,11 +55,11 @@ int imx_irq_set_priority(unsigned char irq, unsigned char prio) if (irq >= MXC_INTERNAL_IRQS) return -EINVAL;; - temp = __raw_readl(AVIC_NIPRIORITY(irq / 8)); + temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8)); temp &= ~mask; temp |= prio & mask; - __raw_writel(temp, AVIC_NIPRIORITY(irq / 8)); + __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8)); return 0; #else @@ -81,12 +77,12 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type) return -EINVAL; if (irq < MXC_INTERNAL_IRQS / 2) { - irqt = __raw_readl(AVIC_INTTYPEL) & ~(1 << irq); - __raw_writel(irqt | (!!type << irq), AVIC_INTTYPEL); + irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq); + __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL); } else { irq -= MXC_INTERNAL_IRQS / 2; - irqt = __raw_readl(AVIC_INTTYPEH) & ~(1 << irq); - __raw_writel(irqt | (!!type << irq), AVIC_INTTYPEH); + irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq); + __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH); } return 0; @@ -97,13 +93,13 @@ EXPORT_SYMBOL(mxc_set_irq_fiq); /* Disable interrupt number "irq" in the AVIC */ static void mxc_mask_irq(unsigned int irq) { - __raw_writel(irq, AVIC_INTDISNUM); + __raw_writel(irq, avic_base + AVIC_INTDISNUM); } /* Enable interrupt number "irq" in the AVIC */ static void mxc_unmask_irq(unsigned int irq) { - __raw_writel(irq, AVIC_INTENNUM); + __raw_writel(irq, avic_base + AVIC_INTENNUM); } static struct irq_chip mxc_avic_chip = { @@ -121,19 +117,21 @@ void __init mxc_init_irq(void) { int i; + avic_base = IO_ADDRESS(AVIC_BASE_ADDR); + /* put the AVIC into the reset value with * all interrupts disabled */ - __raw_writel(0, AVIC_INTCNTL); - __raw_writel(0x1f, AVIC_NIMASK); + __raw_writel(0, avic_base + AVIC_INTCNTL); + __raw_writel(0x1f, avic_base + AVIC_NIMASK); /* disable all interrupts */ - __raw_writel(0, AVIC_INTENABLEH); - __raw_writel(0, AVIC_INTENABLEL); + __raw_writel(0, avic_base + AVIC_INTENABLEH); + __raw_writel(0, avic_base + AVIC_INTENABLEL); /* all IRQ no FIQ */ - __raw_writel(0, AVIC_INTTYPEH); - __raw_writel(0, AVIC_INTTYPEL); + __raw_writel(0, avic_base + AVIC_INTTYPEH); + __raw_writel(0, avic_base + AVIC_INTTYPEL); for (i = 0; i < MXC_INTERNAL_IRQS; i++) { set_irq_chip(i, &mxc_avic_chip); set_irq_handler(i, handle_level_irq); @@ -142,7 +140,7 @@ void __init mxc_init_irq(void) /* Set default priority value (0) for all IRQ's */ for (i = 0; i < 8; i++) - __raw_writel(0, AVIC_NIPRIORITY(i)); + __raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); /* init architectures chained interrupt handler */ mxc_register_gpios(); @@ -154,3 +152,4 @@ void __init mxc_init_irq(void) printk(KERN_INFO "MXC IRQ initialized\n"); } + diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c index 9bffbc507cc..ae34198a79d 100644 --- a/arch/arm/plat-mxc/pwm.c +++ b/arch/arm/plat-mxc/pwm.c @@ -15,65 +15,26 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/pwm.h> +#include <mach/hardware.h> + + +/* i.MX1 and i.MX21 share the same PWM function block: */ + +#define MX1_PWMC 0x00 /* PWM Control Register */ +#define MX1_PWMS 0x04 /* PWM Sample Register */ +#define MX1_PWMP 0x08 /* PWM Period Register */ + + +/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */ + +#define MX3_PWMCR 0x00 /* PWM Control Register */ +#define MX3_PWMSAR 0x0C /* PWM Sample Register */ +#define MX3_PWMPR 0x10 /* PWM Period Register */ +#define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) +#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16) +#define MX3_PWMCR_EN (1 << 0) + -#if defined CONFIG_ARCH_MX1 || defined CONFIG_ARCH_MX21 -#define PWM_VER_1 - -#define PWMCR 0x00 /* PWM Control Register */ -#define PWMSR 0x04 /* PWM Sample Register */ -#define PWMPR 0x08 /* PWM Period Register */ -#define PWMCNR 0x0C /* PWM Counter Register */ - -#define PWMCR_HCTR (1 << 18) /* Halfword FIFO Data Swapping */ -#define PWMCR_BCTR (1 << 17) /* Byte FIFO Data Swapping */ -#define PWMCR_SWR (1 << 16) /* Software Reset */ -#define PWMCR_CLKSRC_PERCLK (0 << 15) /* PERCLK Clock Source */ -#define PWMCR_CLKSRC_CLK32 (1 << 15) /* 32KHz Clock Source */ -#define PWMCR_PRESCALER(x) (((x - 1) & 0x7F) << 8) /* PRESCALER */ -#define PWMCR_IRQ (1 << 7) /* Interrupt Request */ -#define PWMCR_IRQEN (1 << 6) /* Interrupt Request Enable */ -#define PWMCR_FIFOAV (1 << 5) /* FIFO Available */ -#define PWMCR_EN (1 << 4) /* Enables/Disables the PWM */ -#define PWMCR_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */ -#define PWMCR_DIV(x) (((x) & 0x03) << 0) /* Clock divider 2/4/8/16 */ - -#define MAX_DIV (128 * 16) -#endif - -#if defined CONFIG_MACH_MX27 || defined CONFIG_ARCH_MX31 -#define PWM_VER_2 - -#define PWMCR 0x00 /* PWM Control Register */ -#define PWMSR 0x04 /* PWM Status Register */ -#define PWMIR 0x08 /* PWM Interrupt Register */ -#define PWMSAR 0x0C /* PWM Sample Register */ -#define PWMPR 0x10 /* PWM Period Register */ -#define PWMCNR 0x14 /* PWM Counter Register */ - -#define PWMCR_EN (1 << 0) /* Enables/Disables the PWM */ -#define PWMCR_REPEAT(x) (((x) & 0x03) << 1) /* Sample Repeats */ -#define PWMCR_SWR (1 << 3) /* Software Reset */ -#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)/* PRESCALER */ -#define PWMCR_CLKSRC(x) (((x) & 0x3) << 16) -#define PWMCR_CLKSRC_OFF (0 << 16) -#define PWMCR_CLKSRC_IPG (1 << 16) -#define PWMCR_CLKSRC_IPG_HIGH (2 << 16) -#define PWMCR_CLKSRC_CLK32 (3 << 16) -#define PWMCR_POUTC -#define PWMCR_HCTR (1 << 20) /* Halfword FIFO Data Swapping */ -#define PWMCR_BCTR (1 << 21) /* Byte FIFO Data Swapping */ -#define PWMCR_DBGEN (1 << 22) /* Debug Mode */ -#define PWMCR_WAITEN (1 << 23) /* Wait Mode */ -#define PWMCR_DOZEN (1 << 24) /* Doze Mode */ -#define PWMCR_STOPEN (1 << 25) /* Stop Mode */ -#define PWMCR_FWM(x) (((x) & 0x3) << 26) /* FIFO Water Mark */ - -#define MAX_DIV 4096 -#endif - -#define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */ -#define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */ -#define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */ struct pwm_device { struct list_head node; @@ -91,32 +52,52 @@ struct pwm_device { int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) { - unsigned long long c; - unsigned long period_cycles, duty_cycles, prescale; - if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) return -EINVAL; - c = clk_get_rate(pwm->clk); - c = c * period_ns; - do_div(c, 1000000000); - period_cycles = c; - - prescale = period_cycles / 0x10000 + 1; - - period_cycles /= prescale; - c = (unsigned long long)period_cycles * duty_ns; - do_div(c, period_ns); - duty_cycles = c; - -#ifdef PWM_VER_2 - writel(duty_cycles, pwm->mmio_base + PWMSAR); - writel(period_cycles, pwm->mmio_base + PWMPR); - writel(PWMCR_PRESCALER(prescale - 1) | PWMCR_CLKSRC_IPG_HIGH | PWMCR_EN, - pwm->mmio_base + PWMCR); -#elif defined PWM_VER_1 -#error PWM not yet working on MX1 / MX21 -#endif + if (cpu_is_mx27() || cpu_is_mx3()) { + unsigned long long c; + unsigned long period_cycles, duty_cycles, prescale; + c = clk_get_rate(pwm->clk); + c = c * period_ns; + do_div(c, 1000000000); + period_cycles = c; + + prescale = period_cycles / 0x10000 + 1; + + period_cycles /= prescale; + c = (unsigned long long)period_cycles * duty_ns; + do_div(c, period_ns); + duty_cycles = c; + + writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR); + writel(period_cycles, pwm->mmio_base + MX3_PWMPR); + writel(MX3_PWMCR_PRESCALER(prescale - 1) | + MX3_PWMCR_CLKSRC_IPG_HIGH | MX3_PWMCR_EN, + pwm->mmio_base + MX3_PWMCR); + } else if (cpu_is_mx1() || cpu_is_mx21()) { + /* The PWM subsystem allows for exact frequencies. However, + * I cannot connect a scope on my device to the PWM line and + * thus cannot provide the program the PWM controller + * exactly. Instead, I'm relying on the fact that the + * Bootloader (u-boot or WinCE+haret) has programmed the PWM + * function group already. So I'll just modify the PWM sample + * register to follow the ratio of duty_ns vs. period_ns + * accordingly. + * + * This is good enought for programming the brightness of + * the LCD backlight. + * + * The real implementation would divide PERCLK[0] first by + * both the prescaler (/1 .. /128) and then by CLKSEL + * (/2 .. /16). + */ + u32 max = readl(pwm->mmio_base + MX1_PWMP); + u32 p = max * duty_ns / period_ns; + writel(max - p, pwm->mmio_base + MX1_PWMS); + } else { + BUG(); + } return 0; } @@ -297,4 +278,3 @@ module_exit(mxc_pwm_exit); MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); - diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index dab3357196f..88fb3a57e02 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c @@ -29,22 +29,85 @@ #include <mach/hardware.h> #include <asm/mach/time.h> #include <mach/common.h> -#include <mach/mxc_timer.h> + +/* defines common for all i.MX */ +#define MXC_TCTL 0x00 +#define MXC_TCTL_TEN (1 << 0) +#define MXC_TPRER 0x04 + +/* MX1, MX21, MX27 */ +#define MX1_2_TCTL_CLK_PCLK1 (1 << 1) +#define MX1_2_TCTL_IRQEN (1 << 4) +#define MX1_2_TCTL_FRR (1 << 8) +#define MX1_2_TCMP 0x08 +#define MX1_2_TCN 0x10 +#define MX1_2_TSTAT 0x14 + +/* MX21, MX27 */ +#define MX2_TSTAT_CAPT (1 << 1) +#define MX2_TSTAT_COMP (1 << 0) + +/* MX31, MX35 */ +#define MX3_TCTL_WAITEN (1 << 3) +#define MX3_TCTL_CLK_IPG (1 << 6) +#define MX3_TCTL_FRR (1 << 9) +#define MX3_IR 0x0c +#define MX3_TSTAT 0x08 +#define MX3_TSTAT_OF1 (1 << 0) +#define MX3_TCN 0x24 +#define MX3_TCMP 0x10 static struct clock_event_device clockevent_mxc; static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; -/* clock source */ +static void __iomem *timer_base; -static cycle_t mxc_get_cycles(struct clocksource *cs) +static inline void gpt_irq_disable(void) { - return __raw_readl(TIMER_BASE + MXC_TCN); + unsigned int tmp; + + if (cpu_is_mx3()) + __raw_writel(0, timer_base + MX3_IR); + else { + tmp = __raw_readl(timer_base + MXC_TCTL); + __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); + } +} + +static inline void gpt_irq_enable(void) +{ + if (cpu_is_mx3()) + __raw_writel(1<<0, timer_base + MX3_IR); + else { + __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, + timer_base + MXC_TCTL); + } +} + +static void gpt_irq_acknowledge(void) +{ + if (cpu_is_mx1()) + __raw_writel(0, timer_base + MX1_2_TSTAT); + if (cpu_is_mx2()) + __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT); + if (cpu_is_mx3()) + __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT); +} + +static cycle_t mx1_2_get_cycles(struct clocksource *cs) +{ + return __raw_readl(timer_base + MX1_2_TCN); +} + +static cycle_t mx3_get_cycles(struct clocksource *cs) +{ + return __raw_readl(timer_base + MX3_TCN); } static struct clocksource clocksource_mxc = { .name = "mxc_timer1", .rating = 200, - .read = mxc_get_cycles, + .read = mx1_2_get_cycles, .mask = CLOCKSOURCE_MASK(32), .shift = 20, .flags = CLOCK_SOURCE_IS_CONTINUOUS, @@ -54,6 +117,9 @@ static int __init mxc_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); + if (cpu_is_mx3()) + clocksource_mxc.read = mx3_get_cycles; + clocksource_mxc.mult = clocksource_hz2mult(c, clocksource_mxc.shift); clocksource_register(&clocksource_mxc); @@ -63,15 +129,29 @@ static int __init mxc_clocksource_init(struct clk *timer_clk) /* clock event */ -static int mxc_set_next_event(unsigned long evt, +static int mx1_2_set_next_event(unsigned long evt, struct clock_event_device *unused) { unsigned long tcmp; - tcmp = __raw_readl(TIMER_BASE + MXC_TCN) + evt; - __raw_writel(tcmp, TIMER_BASE + MXC_TCMP); + tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt; - return (int)(tcmp - __raw_readl(TIMER_BASE + MXC_TCN)) < 0 ? + __raw_writel(tcmp, timer_base + MX1_2_TCMP); + + return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ? + -ETIME : 0; +} + +static int mx3_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long tcmp; + + tcmp = __raw_readl(timer_base + MX3_TCN) + evt; + + __raw_writel(tcmp, timer_base + MX3_TCMP); + + return (int)(tcmp - __raw_readl(timer_base + MX3_TCN)) < 0 ? -ETIME : 0; } @@ -100,8 +180,13 @@ static void mxc_set_mode(enum clock_event_mode mode, if (mode != clockevent_mode) { /* Set event time into far-far future */ - __raw_writel(__raw_readl(TIMER_BASE + MXC_TCN) - 3, - TIMER_BASE + MXC_TCMP); + if (cpu_is_mx3()) + __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3, + timer_base + MX3_TCMP); + else + __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3, + timer_base + MX1_2_TCMP); + /* Clear pending interrupt */ gpt_irq_acknowledge(); } @@ -148,7 +233,10 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) struct clock_event_device *evt = &clockevent_mxc; uint32_t tstat; - tstat = __raw_readl(TIMER_BASE + MXC_TSTAT); + if (cpu_is_mx3()) + tstat = __raw_readl(timer_base + MX3_TSTAT); + else + tstat = __raw_readl(timer_base + MX1_2_TSTAT); gpt_irq_acknowledge(); @@ -168,7 +256,7 @@ static struct clock_event_device clockevent_mxc = { .features = CLOCK_EVT_FEAT_ONESHOT, .shift = 32, .set_mode = mxc_set_mode, - .set_next_event = mxc_set_next_event, + .set_next_event = mx1_2_set_next_event, .rating = 200, }; @@ -176,6 +264,9 @@ static int __init mxc_clockevent_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); + if (cpu_is_mx3()) + clockevent_mxc.set_next_event = mx3_set_next_event; + clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, clockevent_mxc.shift); clockevent_mxc.max_delta_ns = @@ -192,23 +283,47 @@ static int __init mxc_clockevent_init(struct clk *timer_clk) void __init mxc_timer_init(struct clk *timer_clk) { + uint32_t tctl_val; + int irq; + clk_enable(timer_clk); + if (cpu_is_mx1()) { +#ifdef CONFIG_ARCH_MX1 + timer_base = IO_ADDRESS(TIM1_BASE_ADDR); + irq = TIM1_INT; +#endif + } else if (cpu_is_mx2()) { +#ifdef CONFIG_ARCH_MX2 + timer_base = IO_ADDRESS(GPT1_BASE_ADDR); + irq = MXC_INT_GPT1; +#endif + } else if (cpu_is_mx3()) { +#ifdef CONFIG_ARCH_MX3 + timer_base = IO_ADDRESS(GPT1_BASE_ADDR); + irq = MXC_INT_GPT; +#endif + } else + BUG(); + /* * Initialise to a known state (all timers off, and timing reset) */ - __raw_writel(0, TIMER_BASE + MXC_TCTL); - __raw_writel(0, TIMER_BASE + MXC_TPRER); /* see datasheet note */ - __raw_writel(TCTL_FRR | /* free running */ - TCTL_VAL | /* set clocksource and arch specific bits */ - TCTL_TEN, /* start the timer */ - TIMER_BASE + MXC_TCTL); + __raw_writel(0, timer_base + MXC_TCTL); + __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ + + if (cpu_is_mx3()) + tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; + else + tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; + + __raw_writel(tctl_val, timer_base + MXC_TCTL); /* init and register the timer to the framework */ mxc_clocksource_init(timer_clk); mxc_clockevent_init(timer_clk); /* Make irqs happen */ - setup_irq(TIMER_INTERRUPT, &mxc_timer_irq); + setup_irq(irq, &mxc_timer_irq); } diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index f8a61249f7d..9a6ecc7159b 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -120,6 +120,9 @@ config OMAP_MBOX_FWK Say Y here if you want to use OMAP Mailbox framework support for DSP, IVA1.0 and IVA2 in OMAP1/2/3. +config OMAP_IOMMU + tristate + choice prompt "System timer" default OMAP_MPU_TIMER diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 04a100cfb8e..a8327952395 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -13,6 +13,7 @@ obj- := obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o +obj-$(CONFIG_OMAP_IOMMU) += iommu.o iovmm.o obj-$(CONFIG_CPU_FREQ) += cpu-omap.o obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o diff --git a/arch/arm/plat-omap/include/mach/iommu.h b/arch/arm/plat-omap/include/mach/iommu.h new file mode 100644 index 00000000000..769b00b4c34 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/iommu.h @@ -0,0 +1,168 @@ +/* + * omap iommu: main structures + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_IOMMU_H +#define __MACH_IOMMU_H + +struct iotlb_entry { + u32 da; + u32 pa; + u32 pgsz, prsvd, valid; + union { + u16 ap; + struct { + u32 endian, elsz, mixed; + }; + }; +}; + +struct iommu { + const char *name; + struct module *owner; + struct clk *clk; + void __iomem *regbase; + struct device *dev; + + unsigned int refcount; + struct mutex iommu_lock; /* global for this whole object */ + + /* + * We don't change iopgd for a situation like pgd for a task, + * but share it globally for each iommu. + */ + u32 *iopgd; + spinlock_t page_table_lock; /* protect iopgd */ + + int nr_tlb_entries; + + struct list_head mmap; + struct mutex mmap_lock; /* protect mmap */ + + int (*isr)(struct iommu *obj); + + void *ctx; /* iommu context: registres saved area */ +}; + +struct cr_regs { + union { + struct { + u16 cam_l; + u16 cam_h; + }; + u32 cam; + }; + union { + struct { + u16 ram_l; + u16 ram_h; + }; + u32 ram; + }; +}; + +struct iotlb_lock { + short base; + short vict; +}; + +/* architecture specific functions */ +struct iommu_functions { + unsigned long version; + + int (*enable)(struct iommu *obj); + void (*disable)(struct iommu *obj); + u32 (*fault_isr)(struct iommu *obj, u32 *ra); + + void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr); + void (*tlb_load_cr)(struct iommu *obj, struct cr_regs *cr); + + struct cr_regs *(*alloc_cr)(struct iommu *obj, struct iotlb_entry *e); + int (*cr_valid)(struct cr_regs *cr); + u32 (*cr_to_virt)(struct cr_regs *cr); + void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e); + ssize_t (*dump_cr)(struct iommu *obj, struct cr_regs *cr, char *buf); + + u32 (*get_pte_attr)(struct iotlb_entry *e); + + void (*save_ctx)(struct iommu *obj); + void (*restore_ctx)(struct iommu *obj); + ssize_t (*dump_ctx)(struct iommu *obj, char *buf); +}; + +struct iommu_platform_data { + const char *name; + const char *clk_name; + const int nr_tlb_entries; +}; + +#if defined(CONFIG_ARCH_OMAP1) +#error "iommu for this processor not implemented yet" +#else +#include <mach/iommu2.h> +#endif + +/* + * utilities for super page(16MB, 1MB, 64KB and 4KB) + */ + +#define iopgsz_max(bytes) \ + (((bytes) >= SZ_16M) ? SZ_16M : \ + ((bytes) >= SZ_1M) ? SZ_1M : \ + ((bytes) >= SZ_64K) ? SZ_64K : \ + ((bytes) >= SZ_4K) ? SZ_4K : 0) + +#define bytes_to_iopgsz(bytes) \ + (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \ + ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \ + ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \ + ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1) + +#define iopgsz_to_bytes(iopgsz) \ + (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \ + ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \ + ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \ + ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0) + +#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0) + +/* + * global functions + */ +extern u32 iommu_arch_version(void); + +extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e); +extern u32 iotlb_cr_to_virt(struct cr_regs *cr); + +extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e); +extern void flush_iotlb_page(struct iommu *obj, u32 da); +extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end); +extern void flush_iotlb_all(struct iommu *obj); + +extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e); +extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova); + +extern struct iommu *iommu_get(const char *name); +extern void iommu_put(struct iommu *obj); + +extern void iommu_save_ctx(struct iommu *obj); +extern void iommu_restore_ctx(struct iommu *obj); + +extern int install_iommu_arch(const struct iommu_functions *ops); +extern void uninstall_iommu_arch(const struct iommu_functions *ops); + +extern int foreach_iommu_device(void *data, + int (*fn)(struct device *, void *)); + +extern ssize_t iommu_dump_ctx(struct iommu *obj, char *buf); +extern size_t dump_tlb_entries(struct iommu *obj, char *buf); + +#endif /* __MACH_IOMMU_H */ diff --git a/arch/arm/plat-omap/include/mach/iommu2.h b/arch/arm/plat-omap/include/mach/iommu2.h new file mode 100644 index 00000000000..10ad05f410e --- /dev/null +++ b/arch/arm/plat-omap/include/mach/iommu2.h @@ -0,0 +1,96 @@ +/* + * omap iommu: omap2 architecture specific definitions + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_IOMMU2_H +#define __MACH_IOMMU2_H + +#include <linux/io.h> + +/* + * MMU Register offsets + */ +#define MMU_REVISION 0x00 +#define MMU_SYSCONFIG 0x10 +#define MMU_SYSSTATUS 0x14 +#define MMU_IRQSTATUS 0x18 +#define MMU_IRQENABLE 0x1c +#define MMU_WALKING_ST 0x40 +#define MMU_CNTL 0x44 +#define MMU_FAULT_AD 0x48 +#define MMU_TTB 0x4c +#define MMU_LOCK 0x50 +#define MMU_LD_TLB 0x54 +#define MMU_CAM 0x58 +#define MMU_RAM 0x5c +#define MMU_GFLUSH 0x60 +#define MMU_FLUSH_ENTRY 0x64 +#define MMU_READ_CAM 0x68 +#define MMU_READ_RAM 0x6c +#define MMU_EMU_FAULT_AD 0x70 + +#define MMU_REG_SIZE 256 + +/* + * MMU Register bit definitions + */ +#define MMU_LOCK_BASE_SHIFT 10 +#define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) +#define MMU_LOCK_BASE(x) \ + ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT) + +#define MMU_LOCK_VICT_SHIFT 4 +#define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) +#define MMU_LOCK_VICT(x) \ + ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT) + +#define MMU_CAM_VATAG_SHIFT 12 +#define MMU_CAM_VATAG_MASK \ + ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT) +#define MMU_CAM_P (1 << 3) +#define MMU_CAM_V (1 << 2) +#define MMU_CAM_PGSZ_MASK 3 +#define MMU_CAM_PGSZ_1M (0 << 0) +#define MMU_CAM_PGSZ_64K (1 << 0) +#define MMU_CAM_PGSZ_4K (2 << 0) +#define MMU_CAM_PGSZ_16M (3 << 0) + +#define MMU_RAM_PADDR_SHIFT 12 +#define MMU_RAM_PADDR_MASK \ + ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT) +#define MMU_RAM_ENDIAN_SHIFT 9 +#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT) +#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT) +#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT) +#define MMU_RAM_ELSZ_SHIFT 7 +#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT) +#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT) +#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT) +#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT) +#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT) +#define MMU_RAM_MIXED_SHIFT 6 +#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT) +#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK + +/* + * register accessors + */ +static inline u32 iommu_read_reg(struct iommu *obj, size_t offs) +{ + return __raw_readl(obj->regbase + offs); +} + +static inline void iommu_write_reg(struct iommu *obj, u32 val, size_t offs) +{ + __raw_writel(val, obj->regbase + offs); +} + +#endif /* __MACH_IOMMU2_H */ diff --git a/arch/arm/plat-omap/include/mach/iovmm.h b/arch/arm/plat-omap/include/mach/iovmm.h new file mode 100644 index 00000000000..bdc7ce5d7a4 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/iovmm.h @@ -0,0 +1,94 @@ +/* + * omap iommu: simple virtual address space management + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __IOMMU_MMAP_H +#define __IOMMU_MMAP_H + +struct iovm_struct { + struct iommu *iommu; /* iommu object which this belongs to */ + u32 da_start; /* area definition */ + u32 da_end; + u32 flags; /* IOVMF_: see below */ + struct list_head list; /* linked in ascending order */ + const struct sg_table *sgt; /* keep 'page' <-> 'da' mapping */ + void *va; /* mpu side mapped address */ +}; + +/* + * IOVMF_FLAGS: attribute for iommu virtual memory area(iovma) + * + * lower 16 bit is used for h/w and upper 16 bit is for s/w. + */ +#define IOVMF_SW_SHIFT 16 +#define IOVMF_HW_SIZE (1 << IOVMF_SW_SHIFT) +#define IOVMF_HW_MASK (IOVMF_HW_SIZE - 1) +#define IOVMF_SW_MASK (~IOVMF_HW_MASK)UL + +/* + * iovma: h/w flags derived from cam and ram attribute + */ +#define IOVMF_CAM_MASK (~((1 << 10) - 1)) +#define IOVMF_RAM_MASK (~IOVMF_CAM_MASK) + +#define IOVMF_PGSZ_MASK (3 << 0) +#define IOVMF_PGSZ_1M MMU_CAM_PGSZ_1M +#define IOVMF_PGSZ_64K MMU_CAM_PGSZ_64K +#define IOVMF_PGSZ_4K MMU_CAM_PGSZ_4K +#define IOVMF_PGSZ_16M MMU_CAM_PGSZ_16M + +#define IOVMF_ENDIAN_MASK (1 << 9) +#define IOVMF_ENDIAN_BIG MMU_RAM_ENDIAN_BIG +#define IOVMF_ENDIAN_LITTLE MMU_RAM_ENDIAN_LITTLE + +#define IOVMF_ELSZ_MASK (3 << 7) +#define IOVMF_ELSZ_8 MMU_RAM_ELSZ_8 +#define IOVMF_ELSZ_16 MMU_RAM_ELSZ_16 +#define IOVMF_ELSZ_32 MMU_RAM_ELSZ_32 +#define IOVMF_ELSZ_NONE MMU_RAM_ELSZ_NONE + +#define IOVMF_MIXED_MASK (1 << 6) +#define IOVMF_MIXED MMU_RAM_MIXED + +/* + * iovma: s/w flags, used for mapping and umapping internally. + */ +#define IOVMF_MMIO (1 << IOVMF_SW_SHIFT) +#define IOVMF_ALLOC (2 << IOVMF_SW_SHIFT) +#define IOVMF_ALLOC_MASK (3 << IOVMF_SW_SHIFT) + +/* "superpages" is supported just with physically linear pages */ +#define IOVMF_DISCONT (1 << (2 + IOVMF_SW_SHIFT)) +#define IOVMF_LINEAR (2 << (2 + IOVMF_SW_SHIFT)) +#define IOVMF_LINEAR_MASK (3 << (2 + IOVMF_SW_SHIFT)) + +#define IOVMF_DA_FIXED (1 << (4 + IOVMF_SW_SHIFT)) +#define IOVMF_DA_ANON (2 << (4 + IOVMF_SW_SHIFT)) +#define IOVMF_DA_MASK (3 << (4 + IOVMF_SW_SHIFT)) + + +extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da); +extern u32 iommu_vmap(struct iommu *obj, u32 da, + const struct sg_table *sgt, u32 flags); +extern struct sg_table *iommu_vunmap(struct iommu *obj, u32 da); +extern u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, + u32 flags); +extern void iommu_vfree(struct iommu *obj, const u32 da); +extern u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes, + u32 flags); +extern void iommu_kunmap(struct iommu *obj, u32 da); +extern u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, + u32 flags); +extern void iommu_kfree(struct iommu *obj, u32 da); + +extern void *da_to_va(struct iommu *obj, u32 da); + +#endif /* __IOMMU_MMAP_H */ diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c new file mode 100644 index 00000000000..4cf449fa2cb --- /dev/null +++ b/arch/arm/plat-omap/iommu.c @@ -0,0 +1,996 @@ +/* + * omap iommu: tlb and pagetable primitives + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, + * Paul Mundt and Toshihiro Kobayashi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/clk.h> +#include <linux/platform_device.h> + +#include <asm/cacheflush.h> + +#include <mach/iommu.h> + +#include "iopgtable.h" + +/* accommodate the difference between omap1 and omap2/3 */ +static const struct iommu_functions *arch_iommu; + +static struct platform_driver omap_iommu_driver; +static struct kmem_cache *iopte_cachep; + +/** + * install_iommu_arch - Install archtecure specific iommu functions + * @ops: a pointer to architecture specific iommu functions + * + * There are several kind of iommu algorithm(tlb, pagetable) among + * omap series. This interface installs such an iommu algorighm. + **/ +int install_iommu_arch(const struct iommu_functions *ops) +{ + if (arch_iommu) + return -EBUSY; + + arch_iommu = ops; + return 0; +} +EXPORT_SYMBOL_GPL(install_iommu_arch); + +/** + * uninstall_iommu_arch - Uninstall archtecure specific iommu functions + * @ops: a pointer to architecture specific iommu functions + * + * This interface uninstalls the iommu algorighm installed previously. + **/ +void uninstall_iommu_arch(const struct iommu_functions *ops) +{ + if (arch_iommu != ops) + pr_err("%s: not your arch\n", __func__); + + arch_iommu = NULL; +} +EXPORT_SYMBOL_GPL(uninstall_iommu_arch); + +/** + * iommu_save_ctx - Save registers for pm off-mode support + * @obj: target iommu + **/ +void iommu_save_ctx(struct iommu *obj) +{ + arch_iommu->save_ctx(obj); +} +EXPORT_SYMBOL_GPL(iommu_save_ctx); + +/** + * iommu_restore_ctx - Restore registers for pm off-mode support + * @obj: target iommu + **/ +void iommu_restore_ctx(struct iommu *obj) +{ + arch_iommu->restore_ctx(obj); +} +EXPORT_SYMBOL_GPL(iommu_restore_ctx); + +/** + * iommu_arch_version - Return running iommu arch version + **/ +u32 iommu_arch_version(void) +{ + return arch_iommu->version; +} +EXPORT_SYMBOL_GPL(iommu_arch_version); + +static int iommu_enable(struct iommu *obj) +{ + int err; + + if (!obj) + return -EINVAL; + + clk_enable(obj->clk); + + err = arch_iommu->enable(obj); + + clk_disable(obj->clk); + return err; +} + +static void iommu_disable(struct iommu *obj) +{ + if (!obj) + return; + + clk_enable(obj->clk); + + arch_iommu->disable(obj); + + clk_disable(obj->clk); +} + +/* + * TLB operations + */ +void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) +{ + BUG_ON(!cr || !e); + + arch_iommu->cr_to_e(cr, e); +} +EXPORT_SYMBOL_GPL(iotlb_cr_to_e); + +static inline int iotlb_cr_valid(struct cr_regs *cr) +{ + if (!cr) + return -EINVAL; + + return arch_iommu->cr_valid(cr); +} + +static inline struct cr_regs *iotlb_alloc_cr(struct iommu *obj, + struct iotlb_entry *e) +{ + if (!e) + return NULL; + + return arch_iommu->alloc_cr(obj, e); +} + +u32 iotlb_cr_to_virt(struct cr_regs *cr) +{ + return arch_iommu->cr_to_virt(cr); +} +EXPORT_SYMBOL_GPL(iotlb_cr_to_virt); + +static u32 get_iopte_attr(struct iotlb_entry *e) +{ + return arch_iommu->get_pte_attr(e); +} + +static u32 iommu_report_fault(struct iommu *obj, u32 *da) +{ + return arch_iommu->fault_isr(obj, da); +} + +static void iotlb_lock_get(struct iommu *obj, struct iotlb_lock *l) +{ + u32 val; + + val = iommu_read_reg(obj, MMU_LOCK); + + l->base = MMU_LOCK_BASE(val); + l->vict = MMU_LOCK_VICT(val); + + BUG_ON(l->base != 0); /* Currently no preservation is used */ +} + +static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l) +{ + u32 val; + + BUG_ON(l->base != 0); /* Currently no preservation is used */ + + val = (l->base << MMU_LOCK_BASE_SHIFT); + val |= (l->vict << MMU_LOCK_VICT_SHIFT); + + iommu_write_reg(obj, val, MMU_LOCK); +} + +static void iotlb_read_cr(struct iommu *obj, struct cr_regs *cr) +{ + arch_iommu->tlb_read_cr(obj, cr); +} + +static void iotlb_load_cr(struct iommu *obj, struct cr_regs *cr) +{ + arch_iommu->tlb_load_cr(obj, cr); + + iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); + iommu_write_reg(obj, 1, MMU_LD_TLB); +} + +/** + * iotlb_dump_cr - Dump an iommu tlb entry into buf + * @obj: target iommu + * @cr: contents of cam and ram register + * @buf: output buffer + **/ +static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr, + char *buf) +{ + BUG_ON(!cr || !buf); + + return arch_iommu->dump_cr(obj, cr, buf); +} + +/** + * load_iotlb_entry - Set an iommu tlb entry + * @obj: target iommu + * @e: an iommu tlb entry info + **/ +int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e) +{ + int i; + int err = 0; + struct iotlb_lock l; + struct cr_regs *cr; + + if (!obj || !obj->nr_tlb_entries || !e) + return -EINVAL; + + clk_enable(obj->clk); + + for (i = 0; i < obj->nr_tlb_entries; i++) { + struct cr_regs tmp; + + iotlb_lock_get(obj, &l); + l.vict = i; + iotlb_lock_set(obj, &l); + iotlb_read_cr(obj, &tmp); + if (!iotlb_cr_valid(&tmp)) + break; + } + + if (i == obj->nr_tlb_entries) { + dev_dbg(obj->dev, "%s: full: no entry\n", __func__); + err = -EBUSY; + goto out; + } + + cr = iotlb_alloc_cr(obj, e); + if (IS_ERR(cr)) { + clk_disable(obj->clk); + return PTR_ERR(cr); + } + + iotlb_load_cr(obj, cr); + kfree(cr); + + /* increment victim for next tlb load */ + if (++l.vict == obj->nr_tlb_entries) + l.vict = 0; + iotlb_lock_set(obj, &l); +out: + clk_disable(obj->clk); + return err; +} +EXPORT_SYMBOL_GPL(load_iotlb_entry); + +/** + * flush_iotlb_page - Clear an iommu tlb entry + * @obj: target iommu + * @da: iommu device virtual address + * + * Clear an iommu tlb entry which includes 'da' address. + **/ +void flush_iotlb_page(struct iommu *obj, u32 da) +{ + struct iotlb_lock l; + int i; + + clk_enable(obj->clk); + + for (i = 0; i < obj->nr_tlb_entries; i++) { + struct cr_regs cr; + u32 start; + size_t bytes; + + iotlb_lock_get(obj, &l); + l.vict = i; + iotlb_lock_set(obj, &l); + iotlb_read_cr(obj, &cr); + if (!iotlb_cr_valid(&cr)) + continue; + + start = iotlb_cr_to_virt(&cr); + bytes = iopgsz_to_bytes(cr.cam & 3); + + if ((start <= da) && (da < start + bytes)) { + dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", + __func__, start, da, bytes); + + iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); + } + } + clk_disable(obj->clk); + + if (i == obj->nr_tlb_entries) + dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); +} +EXPORT_SYMBOL_GPL(flush_iotlb_page); + +/** + * flush_iotlb_range - Clear an iommu tlb entries + * @obj: target iommu + * @start: iommu device virtual address(start) + * @end: iommu device virtual address(end) + * + * Clear an iommu tlb entry which includes 'da' address. + **/ +void flush_iotlb_range(struct iommu *obj, u32 start, u32 end) +{ + u32 da = start; + + while (da < end) { + flush_iotlb_page(obj, da); + /* FIXME: Optimize for multiple page size */ + da += IOPTE_SIZE; + } +} +EXPORT_SYMBOL_GPL(flush_iotlb_range); + +/** + * flush_iotlb_all - Clear all iommu tlb entries + * @obj: target iommu + **/ +void flush_iotlb_all(struct iommu *obj) +{ + struct iotlb_lock l; + + clk_enable(obj->clk); + + l.base = 0; + l.vict = 0; + iotlb_lock_set(obj, &l); + + iommu_write_reg(obj, 1, MMU_GFLUSH); + + clk_disable(obj->clk); +} +EXPORT_SYMBOL_GPL(flush_iotlb_all); + +#if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) + +ssize_t iommu_dump_ctx(struct iommu *obj, char *buf) +{ + ssize_t bytes; + + if (!obj || !buf) + return -EINVAL; + + clk_enable(obj->clk); + + bytes = arch_iommu->dump_ctx(obj, buf); + + clk_disable(obj->clk); + + return bytes; +} +EXPORT_SYMBOL_GPL(iommu_dump_ctx); + +static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs) +{ + int i; + struct iotlb_lock saved, l; + struct cr_regs *p = crs; + + clk_enable(obj->clk); + + iotlb_lock_get(obj, &saved); + memcpy(&l, &saved, sizeof(saved)); + + for (i = 0; i < obj->nr_tlb_entries; i++) { + struct cr_regs tmp; + + iotlb_lock_get(obj, &l); + l.vict = i; + iotlb_lock_set(obj, &l); + iotlb_read_cr(obj, &tmp); + if (!iotlb_cr_valid(&tmp)) + continue; + + *p++ = tmp; + } + iotlb_lock_set(obj, &saved); + clk_disable(obj->clk); + + return p - crs; +} + +/** + * dump_tlb_entries - dump cr arrays to given buffer + * @obj: target iommu + * @buf: output buffer + **/ +size_t dump_tlb_entries(struct iommu *obj, char *buf) +{ + int i, n; + struct cr_regs *cr; + char *p = buf; + + cr = kcalloc(obj->nr_tlb_entries, sizeof(*cr), GFP_KERNEL); + if (!cr) + return 0; + + n = __dump_tlb_entries(obj, cr); + for (i = 0; i < n; i++) + p += iotlb_dump_cr(obj, cr + i, p); + kfree(cr); + + return p - buf; +} +EXPORT_SYMBOL_GPL(dump_tlb_entries); + +int foreach_iommu_device(void *data, int (*fn)(struct device *, void *)) +{ + return driver_for_each_device(&omap_iommu_driver.driver, + NULL, data, fn); +} +EXPORT_SYMBOL_GPL(foreach_iommu_device); + +#endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */ + +/* + * H/W pagetable operations + */ +static void flush_iopgd_range(u32 *first, u32 *last) +{ + /* FIXME: L2 cache should be taken care of if it exists */ + do { + asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" + : : "r" (first)); + first += L1_CACHE_BYTES / sizeof(*first); + } while (first <= last); +} + +static void flush_iopte_range(u32 *first, u32 *last) +{ + /* FIXME: L2 cache should be taken care of if it exists */ + do { + asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" + : : "r" (first)); + first += L1_CACHE_BYTES / sizeof(*first); + } while (first <= last); +} + +static void iopte_free(u32 *iopte) +{ + /* Note: freed iopte's must be clean ready for re-use */ + kmem_cache_free(iopte_cachep, iopte); +} + +static u32 *iopte_alloc(struct iommu *obj, u32 *iopgd, u32 da) +{ + u32 *iopte; + + /* a table has already existed */ + if (*iopgd) + goto pte_ready; + + /* + * do the allocation outside the page table lock + */ + spin_unlock(&obj->page_table_lock); + iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); + spin_lock(&obj->page_table_lock); + + if (!*iopgd) { + if (!iopte) + return ERR_PTR(-ENOMEM); + + *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; + flush_iopgd_range(iopgd, iopgd); + + dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); + } else { + /* We raced, free the reduniovant table */ + iopte_free(iopte); + } + +pte_ready: + iopte = iopte_offset(iopgd, da); + + dev_vdbg(obj->dev, + "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", + __func__, da, iopgd, *iopgd, iopte, *iopte); + + return iopte; +} + +static int iopgd_alloc_section(struct iommu *obj, u32 da, u32 pa, u32 prot) +{ + u32 *iopgd = iopgd_offset(obj, da); + + *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; + flush_iopgd_range(iopgd, iopgd); + return 0; +} + +static int iopgd_alloc_super(struct iommu *obj, u32 da, u32 pa, u32 prot) +{ + u32 *iopgd = iopgd_offset(obj, da); + int i; + + for (i = 0; i < 16; i++) + *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; + flush_iopgd_range(iopgd, iopgd + 15); + return 0; +} + +static int iopte_alloc_page(struct iommu *obj, u32 da, u32 pa, u32 prot) +{ + u32 *iopgd = iopgd_offset(obj, da); + u32 *iopte = iopte_alloc(obj, iopgd, da); + + if (IS_ERR(iopte)) + return PTR_ERR(iopte); + + *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; + flush_iopte_range(iopte, iopte); + + dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", + __func__, da, pa, iopte, *iopte); + + return 0; +} + +static int iopte_alloc_large(struct iommu *obj, u32 da, u32 pa, u32 prot) +{ + u32 *iopgd = iopgd_offset(obj, da); + u32 *iopte = iopte_alloc(obj, iopgd, da); + int i; + + if (IS_ERR(iopte)) + return PTR_ERR(iopte); + + for (i = 0; i < 16; i++) + *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; + flush_iopte_range(iopte, iopte + 15); + return 0; +} + +static int iopgtable_store_entry_core(struct iommu *obj, struct iotlb_entry *e) +{ + int (*fn)(struct iommu *, u32, u32, u32); + u32 prot; + int err; + + if (!obj || !e) + return -EINVAL; + + switch (e->pgsz) { + case MMU_CAM_PGSZ_16M: + fn = iopgd_alloc_super; + break; + case MMU_CAM_PGSZ_1M: + fn = iopgd_alloc_section; + break; + case MMU_CAM_PGSZ_64K: + fn = iopte_alloc_large; + break; + case MMU_CAM_PGSZ_4K: + fn = iopte_alloc_page; + break; + default: + fn = NULL; + BUG(); + break; + } + + prot = get_iopte_attr(e); + + spin_lock(&obj->page_table_lock); + err = fn(obj, e->da, e->pa, prot); + spin_unlock(&obj->page_table_lock); + + return err; +} + +/** + * iopgtable_store_entry - Make an iommu pte entry + * @obj: target iommu + * @e: an iommu tlb entry info + **/ +int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e) +{ + int err; + + flush_iotlb_page(obj, e->da); + err = iopgtable_store_entry_core(obj, e); +#ifdef PREFETCH_IOTLB + if (!err) + load_iotlb_entry(obj, e); +#endif + return err; +} +EXPORT_SYMBOL_GPL(iopgtable_store_entry); + +/** + * iopgtable_lookup_entry - Lookup an iommu pte entry + * @obj: target iommu + * @da: iommu device virtual address + * @ppgd: iommu pgd entry pointer to be returned + * @ppte: iommu pte entry pointer to be returned + **/ +void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, u32 **ppte) +{ + u32 *iopgd, *iopte = NULL; + + iopgd = iopgd_offset(obj, da); + if (!*iopgd) + goto out; + + if (*iopgd & IOPGD_TABLE) + iopte = iopte_offset(iopgd, da); +out: + *ppgd = iopgd; + *ppte = iopte; +} +EXPORT_SYMBOL_GPL(iopgtable_lookup_entry); + +static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da) +{ + size_t bytes; + u32 *iopgd = iopgd_offset(obj, da); + int nent = 1; + + if (!*iopgd) + return 0; + + if (*iopgd & IOPGD_TABLE) { + int i; + u32 *iopte = iopte_offset(iopgd, da); + + bytes = IOPTE_SIZE; + if (*iopte & IOPTE_LARGE) { + nent *= 16; + /* rewind to the 1st entry */ + iopte = (u32 *)((u32)iopte & IOLARGE_MASK); + } + bytes *= nent; + memset(iopte, 0, nent * sizeof(*iopte)); + flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); + + /* + * do table walk to check if this table is necessary or not + */ + iopte = iopte_offset(iopgd, 0); + for (i = 0; i < PTRS_PER_IOPTE; i++) + if (iopte[i]) + goto out; + + iopte_free(iopte); + nent = 1; /* for the next L1 entry */ + } else { + bytes = IOPGD_SIZE; + if (*iopgd & IOPGD_SUPER) { + nent *= 16; + /* rewind to the 1st entry */ + iopgd = (u32 *)((u32)iopgd & IOSUPER_MASK); + } + bytes *= nent; + } + memset(iopgd, 0, nent * sizeof(*iopgd)); + flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); +out: + return bytes; +} + +/** + * iopgtable_clear_entry - Remove an iommu pte entry + * @obj: target iommu + * @da: iommu device virtual address + **/ +size_t iopgtable_clear_entry(struct iommu *obj, u32 da) +{ + size_t bytes; + + spin_lock(&obj->page_table_lock); + + bytes = iopgtable_clear_entry_core(obj, da); + flush_iotlb_page(obj, da); + + spin_unlock(&obj->page_table_lock); + + return bytes; +} +EXPORT_SYMBOL_GPL(iopgtable_clear_entry); + +static void iopgtable_clear_entry_all(struct iommu *obj) +{ + int i; + + spin_lock(&obj->page_table_lock); + + for (i = 0; i < PTRS_PER_IOPGD; i++) { + u32 da; + u32 *iopgd; + + da = i << IOPGD_SHIFT; + iopgd = iopgd_offset(obj, da); + + if (!*iopgd) + continue; + + if (*iopgd & IOPGD_TABLE) + iopte_free(iopte_offset(iopgd, 0)); + + *iopgd = 0; + flush_iopgd_range(iopgd, iopgd); + } + + flush_iotlb_all(obj); + + spin_unlock(&obj->page_table_lock); +} + +/* + * Device IOMMU generic operations + */ +static irqreturn_t iommu_fault_handler(int irq, void *data) +{ + u32 stat, da; + u32 *iopgd, *iopte; + int err = -EIO; + struct iommu *obj = data; + + if (!obj->refcount) + return IRQ_NONE; + + /* Dynamic loading TLB or PTE */ + if (obj->isr) + err = obj->isr(obj); + + if (!err) + return IRQ_HANDLED; + + clk_enable(obj->clk); + stat = iommu_report_fault(obj, &da); + clk_disable(obj->clk); + if (!stat) + return IRQ_HANDLED; + + iopgd = iopgd_offset(obj, da); + + if (!(*iopgd & IOPGD_TABLE)) { + dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__, + da, iopgd, *iopgd); + return IRQ_NONE; + } + + iopte = iopte_offset(iopgd, da); + + dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", + __func__, da, iopgd, *iopgd, iopte, *iopte); + + return IRQ_NONE; +} + +static int device_match_by_alias(struct device *dev, void *data) +{ + struct iommu *obj = to_iommu(dev); + const char *name = data; + + pr_debug("%s: %s %s\n", __func__, obj->name, name); + + return strcmp(obj->name, name) == 0; +} + +/** + * iommu_get - Get iommu handler + * @name: target iommu name + **/ +struct iommu *iommu_get(const char *name) +{ + int err = -ENOMEM; + struct device *dev; + struct iommu *obj; + + dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name, + device_match_by_alias); + if (!dev) + return ERR_PTR(-ENODEV); + + obj = to_iommu(dev); + + mutex_lock(&obj->iommu_lock); + + if (obj->refcount++ == 0) { + err = iommu_enable(obj); + if (err) + goto err_enable; + flush_iotlb_all(obj); + } + + if (!try_module_get(obj->owner)) + goto err_module; + + mutex_unlock(&obj->iommu_lock); + + dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); + return obj; + +err_module: + if (obj->refcount == 1) + iommu_disable(obj); +err_enable: + obj->refcount--; + mutex_unlock(&obj->iommu_lock); + return ERR_PTR(err); +} +EXPORT_SYMBOL_GPL(iommu_get); + +/** + * iommu_put - Put back iommu handler + * @obj: target iommu + **/ +void iommu_put(struct iommu *obj) +{ + if (!obj && IS_ERR(obj)) + return; + + mutex_lock(&obj->iommu_lock); + + if (--obj->refcount == 0) + iommu_disable(obj); + + module_put(obj->owner); + + mutex_unlock(&obj->iommu_lock); + + dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); +} +EXPORT_SYMBOL_GPL(iommu_put); + +/* + * OMAP Device MMU(IOMMU) detection + */ +static int __devinit omap_iommu_probe(struct platform_device *pdev) +{ + int err = -ENODEV; + void *p; + int irq; + struct iommu *obj; + struct resource *res; + struct iommu_platform_data *pdata = pdev->dev.platform_data; + + if (pdev->num_resources != 2) + return -EINVAL; + + obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); + if (!obj) + return -ENOMEM; + + obj->clk = clk_get(&pdev->dev, pdata->clk_name); + if (IS_ERR(obj->clk)) + goto err_clk; + + obj->nr_tlb_entries = pdata->nr_tlb_entries; + obj->name = pdata->name; + obj->dev = &pdev->dev; + obj->ctx = (void *)obj + sizeof(*obj); + + mutex_init(&obj->iommu_lock); + mutex_init(&obj->mmap_lock); + spin_lock_init(&obj->page_table_lock); + INIT_LIST_HEAD(&obj->mmap); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + err = -ENODEV; + goto err_mem; + } + obj->regbase = ioremap(res->start, resource_size(res)); + if (!obj->regbase) { + err = -ENOMEM; + goto err_mem; + } + + res = request_mem_region(res->start, resource_size(res), + dev_name(&pdev->dev)); + if (!res) { + err = -EIO; + goto err_mem; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + err = -ENODEV; + goto err_irq; + } + err = request_irq(irq, iommu_fault_handler, IRQF_SHARED, + dev_name(&pdev->dev), obj); + if (err < 0) + goto err_irq; + platform_set_drvdata(pdev, obj); + + p = (void *)__get_free_pages(GFP_KERNEL, get_order(IOPGD_TABLE_SIZE)); + if (!p) { + err = -ENOMEM; + goto err_pgd; + } + memset(p, 0, IOPGD_TABLE_SIZE); + clean_dcache_area(p, IOPGD_TABLE_SIZE); + obj->iopgd = p; + + BUG_ON(!IS_ALIGNED((unsigned long)obj->iopgd, IOPGD_TABLE_SIZE)); + + dev_info(&pdev->dev, "%s registered\n", obj->name); + return 0; + +err_pgd: + free_irq(irq, obj); +err_irq: + release_mem_region(res->start, resource_size(res)); + iounmap(obj->regbase); +err_mem: + clk_put(obj->clk); +err_clk: + kfree(obj); + return err; +} + +static int __devexit omap_iommu_remove(struct platform_device *pdev) +{ + int irq; + struct resource *res; + struct iommu *obj = platform_get_drvdata(pdev); + + platform_set_drvdata(pdev, NULL); + + iopgtable_clear_entry_all(obj); + free_pages((unsigned long)obj->iopgd, get_order(IOPGD_TABLE_SIZE)); + + irq = platform_get_irq(pdev, 0); + free_irq(irq, obj); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, resource_size(res)); + iounmap(obj->regbase); + + clk_put(obj->clk); + dev_info(&pdev->dev, "%s removed\n", obj->name); + kfree(obj); + return 0; +} + +static struct platform_driver omap_iommu_driver = { + .probe = omap_iommu_probe, + .remove = __devexit_p(omap_iommu_remove), + .driver = { + .name = "omap-iommu", + }, +}; + +static void iopte_cachep_ctor(void *iopte) +{ + clean_dcache_area(iopte, IOPTE_TABLE_SIZE); +} + +static int __init omap_iommu_init(void) +{ + struct kmem_cache *p; + const unsigned long flags = SLAB_HWCACHE_ALIGN; + size_t align = 1 << 10; /* L2 pagetable alignement */ + + p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, + iopte_cachep_ctor); + if (!p) + return -ENOMEM; + iopte_cachep = p; + + return platform_driver_register(&omap_iommu_driver); +} +module_init(omap_iommu_init); + +static void __exit omap_iommu_exit(void) +{ + kmem_cache_destroy(iopte_cachep); + + platform_driver_unregister(&omap_iommu_driver); +} +module_exit(omap_iommu_exit); + +MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives"); +MODULE_ALIAS("platform:omap-iommu"); +MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); +MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/plat-omap/iopgtable.h b/arch/arm/plat-omap/iopgtable.h new file mode 100644 index 00000000000..37dac434c7a --- /dev/null +++ b/arch/arm/plat-omap/iopgtable.h @@ -0,0 +1,72 @@ +/* + * omap iommu: pagetable definitions + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __PLAT_OMAP_IOMMU_H +#define __PLAT_OMAP_IOMMU_H + +#define IOPGD_SHIFT 20 +#define IOPGD_SIZE (1 << IOPGD_SHIFT) +#define IOPGD_MASK (~(IOPGD_SIZE - 1)) +#define IOSECTION_MASK IOPGD_MASK +#define PTRS_PER_IOPGD (1 << (32 - IOPGD_SHIFT)) +#define IOPGD_TABLE_SIZE (PTRS_PER_IOPGD * sizeof(u32)) + +#define IOSUPER_SIZE (IOPGD_SIZE << 4) +#define IOSUPER_MASK (~(IOSUPER_SIZE - 1)) + +#define IOPTE_SHIFT 12 +#define IOPTE_SIZE (1 << IOPTE_SHIFT) +#define IOPTE_MASK (~(IOPTE_SIZE - 1)) +#define IOPAGE_MASK IOPTE_MASK +#define PTRS_PER_IOPTE (1 << (IOPGD_SHIFT - IOPTE_SHIFT)) +#define IOPTE_TABLE_SIZE (PTRS_PER_IOPTE * sizeof(u32)) + +#define IOLARGE_SIZE (IOPTE_SIZE << 4) +#define IOLARGE_MASK (~(IOLARGE_SIZE - 1)) + +#define IOPGD_TABLE (1 << 0) +#define IOPGD_SECTION (2 << 0) +#define IOPGD_SUPER (1 << 18 | 2 << 0) + +#define IOPTE_SMALL (2 << 0) +#define IOPTE_LARGE (1 << 0) + +#define iopgd_index(da) (((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1)) +#define iopgd_offset(obj, da) ((obj)->iopgd + iopgd_index(da)) + +#define iopte_paddr(iopgd) (*iopgd & ~((1 << 10) - 1)) +#define iopte_vaddr(iopgd) ((u32 *)phys_to_virt(iopte_paddr(iopgd))) + +#define iopte_index(da) (((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1)) +#define iopte_offset(iopgd, da) (iopte_vaddr(iopgd) + iopte_index(da)) + +static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, + u32 flags) +{ + memset(e, 0, sizeof(*e)); + + e->da = da; + e->pa = pa; + e->valid = 1; + /* FIXME: add OMAP1 support */ + e->pgsz = flags & MMU_CAM_PGSZ_MASK; + e->endian = flags & MMU_RAM_ENDIAN_MASK; + e->elsz = flags & MMU_RAM_ELSZ_MASK; + e->mixed = flags & MMU_RAM_MIXED_MASK; + + return iopgsz_to_bytes(e->pgsz); +} + +#define to_iommu(dev) \ + (struct iommu *)platform_get_drvdata(to_platform_device(dev)) + +#endif /* __PLAT_OMAP_IOMMU_H */ diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c new file mode 100644 index 00000000000..2fce2c151a9 --- /dev/null +++ b/arch/arm/plat-omap/iovmm.c @@ -0,0 +1,896 @@ +/* + * omap iommu: simple virtual address space management + * + * Copyright (C) 2008-2009 Nokia Corporation + * + * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/vmalloc.h> +#include <linux/device.h> +#include <linux/scatterlist.h> + +#include <asm/cacheflush.h> +#include <asm/mach/map.h> + +#include <mach/iommu.h> +#include <mach/iovmm.h> + +#include "iopgtable.h" + +/* + * A device driver needs to create address mappings between: + * + * - iommu/device address + * - physical address + * - mpu virtual address + * + * There are 4 possible patterns for them: + * + * |iova/ mapping iommu_ page + * | da pa va (d)-(p)-(v) function type + * --------------------------------------------------------------------------- + * 1 | c c c 1 - 1 - 1 _kmap() / _kunmap() s + * 2 | c c,a c 1 - 1 - 1 _kmalloc()/ _kfree() s + * 3 | c d c 1 - n - 1 _vmap() / _vunmap() s + * 4 | c d,a c 1 - n - 1 _vmalloc()/ _vfree() n* + * + * + * 'iova': device iommu virtual address + * 'da': alias of 'iova' + * 'pa': physical address + * 'va': mpu virtual address + * + * 'c': contiguous memory area + * 'd': dicontiguous memory area + * 'a': anonymous memory allocation + * '()': optional feature + * + * 'n': a normal page(4KB) size is used. + * 's': multiple iommu superpage(16MB, 1MB, 64KB, 4KB) size is used. + * + * '*': not yet, but feasible. + */ + +static struct kmem_cache *iovm_area_cachep; + +/* return total bytes of sg buffers */ +static size_t sgtable_len(const struct sg_table *sgt) +{ + unsigned int i, total = 0; + struct scatterlist *sg; + + if (!sgt) + return 0; + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + size_t bytes; + + bytes = sg_dma_len(sg); + + if (!iopgsz_ok(bytes)) { + pr_err("%s: sg[%d] not iommu pagesize(%x)\n", + __func__, i, bytes); + return 0; + } + + total += bytes; + } + + return total; +} +#define sgtable_ok(x) (!!sgtable_len(x)) + +/* + * calculate the optimal number sg elements from total bytes based on + * iommu superpages + */ +static unsigned int sgtable_nents(size_t bytes) +{ + int i; + unsigned int nr_entries; + const unsigned long pagesize[] = { SZ_16M, SZ_1M, SZ_64K, SZ_4K, }; + + if (!IS_ALIGNED(bytes, PAGE_SIZE)) { + pr_err("%s: wrong size %08x\n", __func__, bytes); + return 0; + } + + nr_entries = 0; + for (i = 0; i < ARRAY_SIZE(pagesize); i++) { + if (bytes >= pagesize[i]) { + nr_entries += (bytes / pagesize[i]); + bytes %= pagesize[i]; + } + } + BUG_ON(bytes); + + return nr_entries; +} + +/* allocate and initialize sg_table header(a kind of 'superblock') */ +static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags) +{ + unsigned int nr_entries; + int err; + struct sg_table *sgt; + + if (!bytes) + return ERR_PTR(-EINVAL); + + if (!IS_ALIGNED(bytes, PAGE_SIZE)) + return ERR_PTR(-EINVAL); + + /* FIXME: IOVMF_DA_FIXED should support 'superpages' */ + if ((flags & IOVMF_LINEAR) && (flags & IOVMF_DA_ANON)) { + nr_entries = sgtable_nents(bytes); + if (!nr_entries) + return ERR_PTR(-EINVAL); + } else + nr_entries = bytes / PAGE_SIZE; + + sgt = kzalloc(sizeof(*sgt), GFP_KERNEL); + if (!sgt) + return ERR_PTR(-ENOMEM); + + err = sg_alloc_table(sgt, nr_entries, GFP_KERNEL); + if (err) + return ERR_PTR(err); + + pr_debug("%s: sgt:%p(%d entries)\n", __func__, sgt, nr_entries); + + return sgt; +} + +/* free sg_table header(a kind of superblock) */ +static void sgtable_free(struct sg_table *sgt) +{ + if (!sgt) + return; + + sg_free_table(sgt); + kfree(sgt); + + pr_debug("%s: sgt:%p\n", __func__, sgt); +} + +/* map 'sglist' to a contiguous mpu virtual area and return 'va' */ +static void *vmap_sg(const struct sg_table *sgt) +{ + u32 va; + size_t total; + unsigned int i; + struct scatterlist *sg; + struct vm_struct *new; + const struct mem_type *mtype; + + mtype = get_mem_type(MT_DEVICE); + if (!mtype) + return ERR_PTR(-EINVAL); + + total = sgtable_len(sgt); + if (!total) + return ERR_PTR(-EINVAL); + + new = __get_vm_area(total, VM_IOREMAP, VMALLOC_START, VMALLOC_END); + if (!new) + return ERR_PTR(-ENOMEM); + va = (u32)new->addr; + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + size_t bytes; + u32 pa; + int err; + + pa = sg_phys(sg); + bytes = sg_dma_len(sg); + + BUG_ON(bytes != PAGE_SIZE); + + err = ioremap_page(va, pa, mtype); + if (err) + goto err_out; + + va += bytes; + } + + flush_cache_vmap(new->addr, total); + return new->addr; + +err_out: + WARN_ON(1); /* FIXME: cleanup some mpu mappings */ + vunmap(new->addr); + return ERR_PTR(-EAGAIN); +} + +static inline void vunmap_sg(const void *va) +{ + vunmap(va); +} + +static struct iovm_struct *__find_iovm_area(struct iommu *obj, const u32 da) +{ + struct iovm_struct *tmp; + + list_for_each_entry(tmp, &obj->mmap, list) { + if ((da >= tmp->da_start) && (da < tmp->da_end)) { + size_t len; + + len = tmp->da_end - tmp->da_start; + + dev_dbg(obj->dev, "%s: %08x-%08x-%08x(%x) %08x\n", + __func__, tmp->da_start, da, tmp->da_end, len, + tmp->flags); + + return tmp; + } + } + + return NULL; +} + +/** + * find_iovm_area - find iovma which includes @da + * @da: iommu device virtual address + * + * Find the existing iovma starting at @da + */ +struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da) +{ + struct iovm_struct *area; + + mutex_lock(&obj->mmap_lock); + area = __find_iovm_area(obj, da); + mutex_unlock(&obj->mmap_lock); + + return area; +} +EXPORT_SYMBOL_GPL(find_iovm_area); + +/* + * This finds the hole(area) which fits the requested address and len + * in iovmas mmap, and returns the new allocated iovma. + */ +static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da, + size_t bytes, u32 flags) +{ + struct iovm_struct *new, *tmp; + u32 start, prev_end, alignement; + + if (!obj || !bytes) + return ERR_PTR(-EINVAL); + + start = da; + alignement = PAGE_SIZE; + + if (flags & IOVMF_DA_ANON) { + /* + * Reserve the first page for NULL + */ + start = PAGE_SIZE; + if (flags & IOVMF_LINEAR) + alignement = iopgsz_max(bytes); + start = roundup(start, alignement); + } + + tmp = NULL; + if (list_empty(&obj->mmap)) + goto found; + + prev_end = 0; + list_for_each_entry(tmp, &obj->mmap, list) { + + if ((prev_end <= start) && (start + bytes < tmp->da_start)) + goto found; + + if (flags & IOVMF_DA_ANON) + start = roundup(tmp->da_end, alignement); + + prev_end = tmp->da_end; + } + + if ((start >= prev_end) && (ULONG_MAX - start >= bytes)) + goto found; + + dev_dbg(obj->dev, "%s: no space to fit %08x(%x) flags: %08x\n", + __func__, da, bytes, flags); + + return ERR_PTR(-EINVAL); + +found: + new = kmem_cache_zalloc(iovm_area_cachep, GFP_KERNEL); + if (!new) + return ERR_PTR(-ENOMEM); + + new->iommu = obj; + new->da_start = start; + new->da_end = start + bytes; + new->flags = flags; + + /* + * keep ascending order of iovmas + */ + if (tmp) + list_add_tail(&new->list, &tmp->list); + else + list_add(&new->list, &obj->mmap); + + dev_dbg(obj->dev, "%s: found %08x-%08x-%08x(%x) %08x\n", + __func__, new->da_start, start, new->da_end, bytes, flags); + + return new; +} + +static void free_iovm_area(struct iommu *obj, struct iovm_struct *area) +{ + size_t bytes; + + BUG_ON(!obj || !area); + + bytes = area->da_end - area->da_start; + + dev_dbg(obj->dev, "%s: %08x-%08x(%x) %08x\n", + __func__, area->da_start, area->da_end, bytes, area->flags); + + list_del(&area->list); + kmem_cache_free(iovm_area_cachep, area); +} + +/** + * da_to_va - convert (d) to (v) + * @obj: objective iommu + * @da: iommu device virtual address + * @va: mpu virtual address + * + * Returns mpu virtual addr which corresponds to a given device virtual addr + */ +void *da_to_va(struct iommu *obj, u32 da) +{ + void *va = NULL; + struct iovm_struct *area; + + mutex_lock(&obj->mmap_lock); + + area = __find_iovm_area(obj, da); + if (!area) { + dev_dbg(obj->dev, "%s: no da area(%08x)\n", __func__, da); + goto out; + } + va = area->va; + mutex_unlock(&obj->mmap_lock); +out: + return va; +} +EXPORT_SYMBOL_GPL(da_to_va); + +static void sgtable_fill_vmalloc(struct sg_table *sgt, void *_va) +{ + unsigned int i; + struct scatterlist *sg; + void *va = _va; + void *va_end; + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + struct page *pg; + const size_t bytes = PAGE_SIZE; + + /* + * iommu 'superpage' isn't supported with 'iommu_vmalloc()' + */ + pg = vmalloc_to_page(va); + BUG_ON(!pg); + sg_set_page(sg, pg, bytes, 0); + + va += bytes; + } + + va_end = _va + PAGE_SIZE * i; + flush_cache_vmap(_va, va_end); +} + +static inline void sgtable_drain_vmalloc(struct sg_table *sgt) +{ + /* + * Actually this is not necessary at all, just exists for + * consistency of the code readibility. + */ + BUG_ON(!sgt); +} + +static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len) +{ + unsigned int i; + struct scatterlist *sg; + void *va; + + va = phys_to_virt(pa); + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + size_t bytes; + + bytes = iopgsz_max(len); + + BUG_ON(!iopgsz_ok(bytes)); + + sg_set_buf(sg, phys_to_virt(pa), bytes); + /* + * 'pa' is cotinuous(linear). + */ + pa += bytes; + len -= bytes; + } + BUG_ON(len); + + clean_dcache_area(va, len); +} + +static inline void sgtable_drain_kmalloc(struct sg_table *sgt) +{ + /* + * Actually this is not necessary at all, just exists for + * consistency of the code readibility + */ + BUG_ON(!sgt); +} + +/* create 'da' <-> 'pa' mapping from 'sgt' */ +static int map_iovm_area(struct iommu *obj, struct iovm_struct *new, + const struct sg_table *sgt, u32 flags) +{ + int err; + unsigned int i, j; + struct scatterlist *sg; + u32 da = new->da_start; + + if (!obj || !new || !sgt) + return -EINVAL; + + BUG_ON(!sgtable_ok(sgt)); + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + u32 pa; + int pgsz; + size_t bytes; + struct iotlb_entry e; + + pa = sg_phys(sg); + bytes = sg_dma_len(sg); + + flags &= ~IOVMF_PGSZ_MASK; + pgsz = bytes_to_iopgsz(bytes); + if (pgsz < 0) + goto err_out; + flags |= pgsz; + + pr_debug("%s: [%d] %08x %08x(%x)\n", __func__, + i, da, pa, bytes); + + iotlb_init_entry(&e, da, pa, flags); + err = iopgtable_store_entry(obj, &e); + if (err) + goto err_out; + + da += bytes; + } + return 0; + +err_out: + da = new->da_start; + + for_each_sg(sgt->sgl, sg, i, j) { + size_t bytes; + + bytes = iopgtable_clear_entry(obj, da); + + BUG_ON(!iopgsz_ok(bytes)); + + da += bytes; + } + return err; +} + +/* release 'da' <-> 'pa' mapping */ +static void unmap_iovm_area(struct iommu *obj, struct iovm_struct *area) +{ + u32 start; + size_t total = area->da_end - area->da_start; + + BUG_ON((!total) || !IS_ALIGNED(total, PAGE_SIZE)); + + start = area->da_start; + while (total > 0) { + size_t bytes; + + bytes = iopgtable_clear_entry(obj, start); + if (bytes == 0) + bytes = PAGE_SIZE; + else + dev_dbg(obj->dev, "%s: unmap %08x(%x) %08x\n", + __func__, start, bytes, area->flags); + + BUG_ON(!IS_ALIGNED(bytes, PAGE_SIZE)); + + total -= bytes; + start += bytes; + } + BUG_ON(total); +} + +/* template function for all unmapping */ +static struct sg_table *unmap_vm_area(struct iommu *obj, const u32 da, + void (*fn)(const void *), u32 flags) +{ + struct sg_table *sgt = NULL; + struct iovm_struct *area; + + if (!IS_ALIGNED(da, PAGE_SIZE)) { + dev_err(obj->dev, "%s: alignment err(%08x)\n", __func__, da); + return NULL; + } + + mutex_lock(&obj->mmap_lock); + + area = __find_iovm_area(obj, da); + if (!area) { + dev_dbg(obj->dev, "%s: no da area(%08x)\n", __func__, da); + goto out; + } + + if ((area->flags & flags) != flags) { + dev_err(obj->dev, "%s: wrong flags(%08x)\n", __func__, + area->flags); + goto out; + } + sgt = (struct sg_table *)area->sgt; + + unmap_iovm_area(obj, area); + + fn(area->va); + + dev_dbg(obj->dev, "%s: %08x-%08x-%08x(%x) %08x\n", __func__, + area->da_start, da, area->da_end, + area->da_end - area->da_start, area->flags); + + free_iovm_area(obj, area); +out: + mutex_unlock(&obj->mmap_lock); + + return sgt; +} + +static u32 map_iommu_region(struct iommu *obj, u32 da, + const struct sg_table *sgt, void *va, size_t bytes, u32 flags) +{ + int err = -ENOMEM; + struct iovm_struct *new; + + mutex_lock(&obj->mmap_lock); + + new = alloc_iovm_area(obj, da, bytes, flags); + if (IS_ERR(new)) { + err = PTR_ERR(new); + goto err_alloc_iovma; + } + new->va = va; + new->sgt = sgt; + + if (map_iovm_area(obj, new, sgt, new->flags)) + goto err_map; + + mutex_unlock(&obj->mmap_lock); + + dev_dbg(obj->dev, "%s: da:%08x(%x) flags:%08x va:%p\n", + __func__, new->da_start, bytes, new->flags, va); + + return new->da_start; + +err_map: + free_iovm_area(obj, new); +err_alloc_iovma: + mutex_unlock(&obj->mmap_lock); + return err; +} + +static inline u32 __iommu_vmap(struct iommu *obj, u32 da, + const struct sg_table *sgt, void *va, size_t bytes, u32 flags) +{ + return map_iommu_region(obj, da, sgt, va, bytes, flags); +} + +/** + * iommu_vmap - (d)-(p)-(v) address mapper + * @obj: objective iommu + * @sgt: address of scatter gather table + * @flags: iovma and page property + * + * Creates 1-n-1 mapping with given @sgt and returns @da. + * All @sgt element must be io page size aligned. + */ +u32 iommu_vmap(struct iommu *obj, u32 da, const struct sg_table *sgt, + u32 flags) +{ + size_t bytes; + void *va; + + if (!obj || !obj->dev || !sgt) + return -EINVAL; + + bytes = sgtable_len(sgt); + if (!bytes) + return -EINVAL; + bytes = PAGE_ALIGN(bytes); + + va = vmap_sg(sgt); + if (IS_ERR(va)) + return PTR_ERR(va); + + flags &= IOVMF_HW_MASK; + flags |= IOVMF_DISCONT; + flags |= IOVMF_MMIO; + flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); + + da = __iommu_vmap(obj, da, sgt, va, bytes, flags); + if (IS_ERR_VALUE(da)) + vunmap_sg(va); + + return da; +} +EXPORT_SYMBOL_GPL(iommu_vmap); + +/** + * iommu_vunmap - release virtual mapping obtained by 'iommu_vmap()' + * @obj: objective iommu + * @da: iommu device virtual address + * + * Free the iommu virtually contiguous memory area starting at + * @da, which was returned by 'iommu_vmap()'. + */ +struct sg_table *iommu_vunmap(struct iommu *obj, u32 da) +{ + struct sg_table *sgt; + /* + * 'sgt' is allocated before 'iommu_vmalloc()' is called. + * Just returns 'sgt' to the caller to free + */ + sgt = unmap_vm_area(obj, da, vunmap_sg, IOVMF_DISCONT | IOVMF_MMIO); + if (!sgt) + dev_dbg(obj->dev, "%s: No sgt\n", __func__); + return sgt; +} +EXPORT_SYMBOL_GPL(iommu_vunmap); + +/** + * iommu_vmalloc - (d)-(p)-(v) address allocator and mapper + * @obj: objective iommu + * @da: contiguous iommu virtual memory + * @bytes: allocation size + * @flags: iovma and page property + * + * Allocate @bytes linearly and creates 1-n-1 mapping and returns + * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set. + */ +u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags) +{ + void *va; + struct sg_table *sgt; + + if (!obj || !obj->dev || !bytes) + return -EINVAL; + + bytes = PAGE_ALIGN(bytes); + + va = vmalloc(bytes); + if (!va) + return -ENOMEM; + + sgt = sgtable_alloc(bytes, flags); + if (IS_ERR(sgt)) { + da = PTR_ERR(sgt); + goto err_sgt_alloc; + } + sgtable_fill_vmalloc(sgt, va); + + flags &= IOVMF_HW_MASK; + flags |= IOVMF_DISCONT; + flags |= IOVMF_ALLOC; + flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); + + da = __iommu_vmap(obj, da, sgt, va, bytes, flags); + if (IS_ERR_VALUE(da)) + goto err_iommu_vmap; + + return da; + +err_iommu_vmap: + sgtable_drain_vmalloc(sgt); + sgtable_free(sgt); +err_sgt_alloc: + vfree(va); + return da; +} +EXPORT_SYMBOL_GPL(iommu_vmalloc); + +/** + * iommu_vfree - release memory allocated by 'iommu_vmalloc()' + * @obj: objective iommu + * @da: iommu device virtual address + * + * Frees the iommu virtually continuous memory area starting at + * @da, as obtained from 'iommu_vmalloc()'. + */ +void iommu_vfree(struct iommu *obj, const u32 da) +{ + struct sg_table *sgt; + + sgt = unmap_vm_area(obj, da, vfree, IOVMF_DISCONT | IOVMF_ALLOC); + if (!sgt) + dev_dbg(obj->dev, "%s: No sgt\n", __func__); + sgtable_free(sgt); +} +EXPORT_SYMBOL_GPL(iommu_vfree); + +static u32 __iommu_kmap(struct iommu *obj, u32 da, u32 pa, void *va, + size_t bytes, u32 flags) +{ + struct sg_table *sgt; + + sgt = sgtable_alloc(bytes, flags); + if (IS_ERR(sgt)) + return PTR_ERR(sgt); + + sgtable_fill_kmalloc(sgt, pa, bytes); + + da = map_iommu_region(obj, da, sgt, va, bytes, flags); + if (IS_ERR_VALUE(da)) { + sgtable_drain_kmalloc(sgt); + sgtable_free(sgt); + } + + return da; +} + +/** + * iommu_kmap - (d)-(p)-(v) address mapper + * @obj: objective iommu + * @da: contiguous iommu virtual memory + * @pa: contiguous physical memory + * @flags: iovma and page property + * + * Creates 1-1-1 mapping and returns @da again, which can be + * adjusted if 'IOVMF_DA_ANON' is set. + */ +u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes, + u32 flags) +{ + void *va; + + if (!obj || !obj->dev || !bytes) + return -EINVAL; + + bytes = PAGE_ALIGN(bytes); + + va = ioremap(pa, bytes); + if (!va) + return -ENOMEM; + + flags &= IOVMF_HW_MASK; + flags |= IOVMF_LINEAR; + flags |= IOVMF_MMIO; + flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); + + da = __iommu_kmap(obj, da, pa, va, bytes, flags); + if (IS_ERR_VALUE(da)) + iounmap(va); + + return da; +} +EXPORT_SYMBOL_GPL(iommu_kmap); + +/** + * iommu_kunmap - release virtual mapping obtained by 'iommu_kmap()' + * @obj: objective iommu + * @da: iommu device virtual address + * + * Frees the iommu virtually contiguous memory area starting at + * @da, which was passed to and was returned by'iommu_kmap()'. + */ +void iommu_kunmap(struct iommu *obj, u32 da) +{ + struct sg_table *sgt; + typedef void (*func_t)(const void *); + + sgt = unmap_vm_area(obj, da, (func_t)__iounmap, + IOVMF_LINEAR | IOVMF_MMIO); + if (!sgt) + dev_dbg(obj->dev, "%s: No sgt\n", __func__); + sgtable_free(sgt); +} +EXPORT_SYMBOL_GPL(iommu_kunmap); + +/** + * iommu_kmalloc - (d)-(p)-(v) address allocator and mapper + * @obj: objective iommu + * @da: contiguous iommu virtual memory + * @bytes: bytes for allocation + * @flags: iovma and page property + * + * Allocate @bytes linearly and creates 1-1-1 mapping and returns + * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set. + */ +u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags) +{ + void *va; + u32 pa; + + if (!obj || !obj->dev || !bytes) + return -EINVAL; + + bytes = PAGE_ALIGN(bytes); + + va = kmalloc(bytes, GFP_KERNEL | GFP_DMA); + if (!va) + return -ENOMEM; + pa = virt_to_phys(va); + + flags &= IOVMF_HW_MASK; + flags |= IOVMF_LINEAR; + flags |= IOVMF_ALLOC; + flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); + + da = __iommu_kmap(obj, da, pa, va, bytes, flags); + if (IS_ERR_VALUE(da)) + kfree(va); + + return da; +} +EXPORT_SYMBOL_GPL(iommu_kmalloc); + +/** + * iommu_kfree - release virtual mapping obtained by 'iommu_kmalloc()' + * @obj: objective iommu + * @da: iommu device virtual address + * + * Frees the iommu virtually contiguous memory area starting at + * @da, which was passed to and was returned by'iommu_kmalloc()'. + */ +void iommu_kfree(struct iommu *obj, u32 da) +{ + struct sg_table *sgt; + + sgt = unmap_vm_area(obj, da, kfree, IOVMF_LINEAR | IOVMF_ALLOC); + if (!sgt) + dev_dbg(obj->dev, "%s: No sgt\n", __func__); + sgtable_free(sgt); +} +EXPORT_SYMBOL_GPL(iommu_kfree); + + +static int __init iovmm_init(void) +{ + const unsigned long flags = SLAB_HWCACHE_ALIGN; + struct kmem_cache *p; + + p = kmem_cache_create("iovm_area_cache", sizeof(struct iovm_struct), 0, + flags, NULL); + if (!p) + return -ENOMEM; + iovm_area_cachep = p; + + return 0; +} +module_init(iovmm_init); + +static void __exit iovmm_exit(void) +{ + kmem_cache_destroy(iovm_area_cachep); +} +module_exit(iovmm_exit); + +MODULE_DESCRIPTION("omap iommu: simple virtual address space management"); +MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>"); +MODULE_LICENSE("GPL v2"); |