diff options
Diffstat (limited to 'arch/arm')
69 files changed, 10282 insertions, 807 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b786e68914d..5bf60d5897d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -84,6 +84,11 @@ config STACKTRACE_SUPPORT bool default y +config HAVE_LATENCYTOP_SUPPORT + bool + depends on !SMP + default y + config LOCKDEP_SUPPORT bool default y @@ -347,6 +352,16 @@ config ARCH_L7200 If you have any questions or comments about the Linux kernel port to this board, send e-mail to <sjhill@cotw.com>. +config ARCH_KIRKWOOD + bool "Marvell Kirkwood" + select PCI + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select PLAT_ORION + help + Support for the following Marvell Kirkwood series SoCs: + 88F6180, 88F6192 and 88F6281. + config ARCH_KS8695 bool "Micrel/Kendin KS8695" select GENERIC_GPIO @@ -365,6 +380,24 @@ config ARCH_NS9XXX <http://www.digi.com/products/microprocessors/index.jsp> +config ARCH_LOKI + bool "Marvell Loki (88RC8480)" + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select PLAT_ORION + help + Support for the Marvell Loki (88RC8480) SoC. + +config ARCH_MV78XX0 + bool "Marvell MV78xx0" + select PCI + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select PLAT_ORION + help + Support for the following Marvell MV78xx0 series SoCs: + MV781x0, MV782x0. + config ARCH_MXC bool "Freescale MXC/iMX-based" select ARCH_MTD_XIP @@ -381,7 +414,8 @@ config ARCH_ORION5X select PLAT_ORION help Support for the following Marvell Orion 5x series SoCs: - Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.) + Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), + Orion-2 (5281). config ARCH_PNX4008 bool "Philips Nexperia PNX4008 Mobile" @@ -502,6 +536,10 @@ source "arch/arm/mach-ixp2000/Kconfig" source "arch/arm/mach-ixp23xx/Kconfig" +source "arch/arm/mach-loki/Kconfig" + +source "arch/arm/mach-mv78xx0/Kconfig" + source "arch/arm/mach-pxa/Kconfig" source "arch/arm/mach-sa1100/Kconfig" @@ -514,6 +552,8 @@ source "arch/arm/mach-omap2/Kconfig" source "arch/arm/mach-orion5x/Kconfig" +source "arch/arm/mach-kirkwood/Kconfig" + source "arch/arm/plat-s3c24xx/Kconfig" source "arch/arm/plat-s3c/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index e72db27e0ba..b53237bb6f1 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -135,11 +135,14 @@ endif machine-$(CONFIG_ARCH_NETX) := netx machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx machine-$(CONFIG_ARCH_DAVINCI) := davinci + machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood machine-$(CONFIG_ARCH_KS8695) := ks8695 incdir-$(CONFIG_ARCH_MXC) := mxc machine-$(CONFIG_ARCH_MX3) := mx3 machine-$(CONFIG_ARCH_ORION5X) := orion5x machine-$(CONFIG_ARCH_MSM7X00A) := msm + machine-$(CONFIG_ARCH_LOKI) := loki + machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 ifeq ($(CONFIG_ARCH_EBSA110),y) # This is what happens if you forget the IOCS16 line. diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 3c2c8f2a1dc..de41daeab5e 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -623,8 +623,8 @@ proc_types: b __armv4_mmu_cache_off b __armv4_mmu_cache_flush - .word 0x56055310 @ Feroceon - .word 0xfffffff0 + .word 0x56050000 @ Feroceon + .word 0xff0f0000 b __armv4_mmu_cache_on b __armv4_mmu_cache_off b __armv5tej_mmu_cache_flush diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig new file mode 100644 index 00000000000..e3357ba10f1 --- /dev/null +++ b/arch/arm/configs/kirkwood_defconfig @@ -0,0 +1,1426 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.26-rc5 +# Sun Jun 22 15:51:25 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +# CONFIG_MARKERS is not set +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_KRETPROBES=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HAVE_DMA_ATTRS is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +CONFIG_ARCH_KIRKWOOD=y +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM7X00A is not set + +# +# Marvell Kirkwood Implementations +# +CONFIG_MACH_DB88F6281_BP=y +CONFIG_MACH_RD88F6192_NAS=y +CONFIG_MACH_RD88F6281=y + +# +# Boot options +# + +# +# Power management +# +CONFIG_PLAT_ORION=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_FEROCEON=y +# CONFIG_CPU_FEROCEON_OLD_ID is not set +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_FEROCEON=y +CONFIG_CPU_TLB_FEROCEON=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_CACHE_FEROCEON_L2=y + +# +# Bus support +# +CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_NET_TCPPROBE is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x0 +CONFIG_MTD_PHYSMAP_LEN=0x0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=0 +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +CONFIG_M25PXX_USE_FAST_READ=y +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +CONFIG_MTD_NAND_ORION=y +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_SATA_PMP=y +# CONFIG_SATA_AHCI is not set +# CONFIG_SATA_SIL24 is not set +CONFIG_ATA_SFF=y +# CONFIG_SATA_SVW is not set +# CONFIG_ATA_PIIX is not set +CONFIG_SATA_MV=y +# CONFIG_SATA_NV is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_SCH is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_EEPRO100 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_R6040 is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +CONFIG_E1000=y +CONFIG_E1000_NAPI=y +# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_E1000E is not set +# CONFIG_E1000E_ENABLED is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +CONFIG_MV643XX_ETH=y +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set +# CONFIG_I2C_PCA_PLATFORM is not set +CONFIG_I2C_MV64XXX=y + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set +CONFIG_SPI_ORION=y + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_PASIC3 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Sound +# +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +CONFIG_USB_PRINTER=y +# CONFIG_USB_WDM is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +# CONFIG_USB_STORAGE_ISD200 is not set +CONFIG_USB_STORAGE_DPCM=y +# CONFIG_USB_STORAGE_USBAT is not set +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +CONFIG_NEW_LEDS=y +# CONFIG_LEDS_CLASS is not set + +# +# LED drivers +# + +# +# LED Triggers +# +# CONFIG_LEDS_TRIGGERS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +CONFIG_RTC_DRV_MV=y +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_DMADEVICES=y + +# +# DMA Devices +# +CONFIG_MV_XOR=y +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_KPROBES_SANITY_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SAMPLES is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_ASYNC_CORE=y +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_MANAGER=m +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/loki_defconfig b/arch/arm/configs/loki_defconfig new file mode 100644 index 00000000000..17da7c3b3d5 --- /dev/null +++ b/arch/arm/configs/loki_defconfig @@ -0,0 +1,1147 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.26-rc5 +# Fri Jun 13 03:07:49 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HAVE_DMA_ATTRS is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +CONFIG_ARCH_LOKI=y +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM7X00A is not set + +# +# Marvell Loki (88RC8480) Implementations +# +CONFIG_MACH_LB88RC8480=y + +# +# Boot options +# + +# +# Power management +# +CONFIG_PLAT_ORION=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_FEROCEON=y +# CONFIG_CPU_FEROCEON_OLD_ID is not set +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_FEROCEON=y +CONFIG_CPU_TLB_FEROCEON=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +CONFIG_FTL=y +CONFIG_NFTL=y +# CONFIG_NFTL_RW is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_I4=y +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x0 +CONFIG_MTD_PHYSMAP_LEN=0x0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=0 +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +CONFIG_M25PXX_USE_FAST_READ=y +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +CONFIG_MTD_NAND_ORION=y +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_SATA_PMP=y +CONFIG_ATA_SFF=y +CONFIG_SATA_MV=y +# CONFIG_PATA_PLATFORM is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +CONFIG_NETDEV_1000=y +# CONFIG_E1000E_ENABLED is not set +CONFIG_MV643XX_ETH=y +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_PCA_PLATFORM is not set +CONFIG_I2C_MV64XXX=y + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_PASIC3 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +CONFIG_USB_PRINTER=y +# CONFIG_USB_WDM is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +# CONFIG_USB_STORAGE_ISD200 is not set +CONFIG_USB_STORAGE_DPCM=y +# CONFIG_USB_STORAGE_USBAT is not set +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +CONFIG_NEW_LEDS=y +# CONFIG_LEDS_CLASS is not set + +# +# LED drivers +# + +# +# LED Triggers +# +# CONFIG_LEDS_TRIGGERS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_LDM_DEBUG=y +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_FRAME_POINTER=y +# CONFIG_LATENCYTOP is not set +# CONFIG_SAMPLES is not set +CONFIG_DEBUG_USER=y + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_MANAGER=m +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig new file mode 100644 index 00000000000..d38ebf8721a --- /dev/null +++ b/arch/arm/configs/mv78xx0_defconfig @@ -0,0 +1,1445 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.26-rc5 +# Fri Jun 13 02:57:32 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +# CONFIG_MARKERS is not set +CONFIG_OPROFILE=y +CONFIG_HAVE_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_KRETPROBES=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HAVE_DMA_ATTRS is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +CONFIG_ARCH_MV78XX0=y +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM7X00A is not set + +# +# Marvell MV78xx0 Implementations +# +CONFIG_MACH_DB78X00_BP=y + +# +# Boot options +# + +# +# Power management +# +CONFIG_PLAT_ORION=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_FEROCEON=y +CONFIG_CPU_FEROCEON_OLD_ID=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_FEROCEON=y +CONFIG_CPU_TLB_FEROCEON=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_CACHE_FEROCEON_L2=y + +# +# Bus support +# +CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +# CONFIG_NET_TCPPROBE is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x0 +CONFIG_MTD_PHYSMAP_LEN=0x0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=0 +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +CONFIG_MTD_NAND_ORION=y +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_SATA_PMP=y +# CONFIG_SATA_AHCI is not set +# CONFIG_SATA_SIL24 is not set +CONFIG_ATA_SFF=y +# CONFIG_SATA_SVW is not set +# CONFIG_ATA_PIIX is not set +CONFIG_SATA_MV=y +# CONFIG_SATA_NV is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_SCH is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_EEPRO100 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_R6040 is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_E1000E_ENABLED is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +CONFIG_MV643XX_ETH=y +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PROSAVAGE is not set +# CONFIG_I2C_SAVAGE4 is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VOODOO3 is not set +# CONFIG_I2C_PCA_PLATFORM is not set +CONFIG_I2C_MV64XXX=y + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_PASIC3 is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Sound +# +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +CONFIG_USB_PRINTER=y +# CONFIG_USB_WDM is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +# CONFIG_USB_STORAGE_ISD200 is not set +CONFIG_USB_STORAGE_DPCM=y +# CONFIG_USB_STORAGE_USBAT is not set +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +CONFIG_RTC_DRV_DS1307=y +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +CONFIG_RTC_DRV_RS5C372=y +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +CONFIG_RTC_DRV_M41T80=y +# CONFIG_RTC_DRV_M41T80_WDT is not set +# CONFIG_RTC_DRV_S35390A is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y +CONFIG_SCHEDSTATS=y +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_KPROBES_SANITY_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SAMPLES is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_MANAGER=m +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig index 52cd99bd52f..8a7cabfae57 100644 --- a/arch/arm/configs/orion5x_defconfig +++ b/arch/arm/configs/orion5x_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.24 -# Thu Feb 7 14:10:30 2008 +# Linux kernel version: 2.6.26-rc4 +# Mon Jun 2 23:54:48 2008 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -21,6 +21,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_AOUT=y CONFIG_ZONE_DMA=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -40,24 +41,24 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -# CONFIG_USER_NS is not set -# CONFIG_PID_NS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CGROUPS is not set -CONFIG_FAIR_GROUP_SCHED=y -CONFIG_FAIR_USER_SCHED=y -# CONFIG_FAIR_CGROUP_SCHED is not set +# CONFIG_GROUP_SCHED is not set CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set # CONFIG_BLK_DEV_INITRD is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_UID16=y CONFIG_SYSCTL_SYSCALL=y +CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y # CONFIG_KALLSYMS_EXTRA_PASS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y @@ -73,20 +74,25 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y # CONFIG_SLOB is not set -# CONFIG_PROFILING is not set +CONFIG_PROFILING=y # CONFIG_MARKERS is not set +CONFIG_OPROFILE=y CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set +CONFIG_KPROBES=y +CONFIG_KRETPROBES=y CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HAVE_DMA_ATTRS is not set CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set @@ -111,7 +117,6 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y -# CONFIG_PREEMPT_RCU is not set # # System Type @@ -160,6 +165,15 @@ CONFIG_MACH_RD88F5182=y CONFIG_MACH_KUROBOX_PRO=y CONFIG_MACH_DNS323=y CONFIG_MACH_TS209=y +CONFIG_MACH_LINKSTATION_PRO=y +CONFIG_MACH_TS409=y +CONFIG_MACH_WRT350N_V2=y +CONFIG_MACH_TS78XX=y +CONFIG_MACH_MV2120=y +CONFIG_MACH_MSS2=y +CONFIG_MACH_WNR854T=y +CONFIG_MACH_RD88F5181L_GE=y +CONFIG_MACH_RD88F5181L_FXO=y # # Boot options @@ -168,6 +182,7 @@ CONFIG_MACH_TS209=y # # Power management # +CONFIG_PLAT_ORION=y # # Processor Type @@ -177,8 +192,9 @@ CONFIG_CPU_FEROCEON=y CONFIG_CPU_FEROCEON_OLD_ID=y CONFIG_CPU_32v5=y CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_PABRT_NOIFAR=y CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_COPY_FEROCEON=y CONFIG_CPU_TLB_V4WBI=y CONFIG_CPU_CP15=y CONFIG_CPU_CP15_MMU=y @@ -189,7 +205,6 @@ CONFIG_CPU_CP15_MMU=y CONFIG_ARM_THUMB=y # CONFIG_CPU_ICACHE_DISABLE is not set # CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set # CONFIG_OUTER_CACHE is not set # @@ -199,6 +214,7 @@ CONFIG_PCI=y CONFIG_PCI_SYSCALL=y # CONFIG_ARCH_SUPPORTS_MSI is not set CONFIG_PCI_LEGACY=y +# CONFIG_PCI_DEBUG is not set # CONFIG_PCCARD is not set # @@ -221,6 +237,7 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4096 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 @@ -238,7 +255,6 @@ CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="" # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set -# CONFIG_ATAGS_PROC is not set # # Floating point emulation @@ -311,8 +327,6 @@ CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set @@ -335,6 +349,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # Network testing # CONFIG_NET_PKTGEN=m +# CONFIG_NET_TCPPROBE is not set # CONFIG_HAMRADIO is not set # CONFIG_CAN is not set # CONFIG_IRDA is not set @@ -362,6 +377,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set CONFIG_MTD=y @@ -371,6 +388,7 @@ CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set CONFIG_MTD_CMDLINE_PARTS=y # CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers @@ -378,9 +396,8 @@ CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y -CONFIG_FTL=y -CONFIG_NFTL=y -# CONFIG_NFTL_RW is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set @@ -405,12 +422,12 @@ CONFIG_MTD_MAP_BANK_WIDTH_4=y # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y -CONFIG_MTD_CFI_I4=y +# CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set # CONFIG_MTD_OTP is not set CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_STAA=y +# CONFIG_MTD_CFI_STAA is not set CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set @@ -481,6 +498,9 @@ CONFIG_MISC_DEVICES=y # CONFIG_EEPROM_93CX6 is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set # # SCSI device support @@ -542,6 +562,7 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_MVSAS is not set # CONFIG_SCSI_STEX is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_IPR is not set @@ -556,7 +577,10 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_SRP is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set +CONFIG_SATA_PMP=y # CONFIG_SATA_AHCI is not set +# CONFIG_SATA_SIL24 is not set +CONFIG_ATA_SFF=y # CONFIG_SATA_SVW is not set # CONFIG_ATA_PIIX is not set CONFIG_SATA_MV=y @@ -566,7 +590,6 @@ CONFIG_SATA_MV=y # CONFIG_SATA_PROMISE is not set # CONFIG_SATA_SX4 is not set # CONFIG_SATA_SIL is not set -# CONFIG_SATA_SIL24 is not set # CONFIG_SATA_SIS is not set # CONFIG_SATA_ULI is not set # CONFIG_SATA_VIA is not set @@ -611,6 +634,7 @@ CONFIG_SATA_MV=y # CONFIG_PATA_VIA is not set # CONFIG_PATA_WINBOND is not set # CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_SCH is not set # CONFIG_MD is not set # CONFIG_FUSION is not set @@ -652,7 +676,7 @@ CONFIG_NET_PCI=y # CONFIG_B44 is not set # CONFIG_FORCEDETH is not set # CONFIG_EEPRO100 is not set -CONFIG_E100=y +# CONFIG_E100 is not set # CONFIG_FEALNX is not set # CONFIG_NATSEMI is not set # CONFIG_NE2K_PCI is not set @@ -668,9 +692,7 @@ CONFIG_E100=y CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set -CONFIG_E1000=y -CONFIG_E1000_NAPI=y -# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_E1000 is not set # CONFIG_E1000E is not set # CONFIG_E1000E_ENABLED is not set # CONFIG_IP1000 is not set @@ -680,27 +702,15 @@ CONFIG_E1000_NAPI=y # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set # CONFIG_SIS190 is not set -CONFIG_SKGE=y -CONFIG_SKY2=y -# CONFIG_SK98LIN is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set # CONFIG_VIA_VELOCITY is not set -CONFIG_TIGON3=y +# CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set CONFIG_MV643XX_ETH=y # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set -CONFIG_NETDEV_10000=y -# CONFIG_CHELSIO_T1 is not set -# CONFIG_CHELSIO_T3 is not set -# CONFIG_IXGBE is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set -# CONFIG_NETXEN_NIC is not set -# CONFIG_NIU is not set -# CONFIG_MLX4_CORE is not set -# CONFIG_TEHUTI is not set -# CONFIG_BNX2X is not set +# CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set # @@ -708,6 +718,7 @@ CONFIG_NETDEV_10000=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set # # USB Network Adapters @@ -738,12 +749,9 @@ CONFIG_INPUT=y # # Userland interfaces # -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set +CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set # @@ -765,10 +773,8 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # # Character devices # -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_VT is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_NOZOMI is not set @@ -777,7 +783,7 @@ CONFIG_HW_CONSOLE=y # CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y +# CONFIG_SERIAL_8250_PCI is not set CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=2 # CONFIG_SERIAL_8250_EXTENDED is not set @@ -792,7 +798,7 @@ CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=16 # CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM is not set # CONFIG_NVRAM is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set @@ -804,13 +810,6 @@ CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y # -# I2C Algorithms -# -# CONFIG_I2C_ALGOBIT is not set -# CONFIG_I2C_ALGOPCF is not set -# CONFIG_I2C_ALGOPCA is not set - -# # I2C Hardware Bus support # # CONFIG_I2C_ALI1535 is not set @@ -837,6 +836,7 @@ CONFIG_I2C_CHARDEV=y # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set # CONFIG_I2C_VOODOO3 is not set +# CONFIG_I2C_PCA_PLATFORM is not set CONFIG_I2C_MV64XXX=y # @@ -847,19 +847,13 @@ CONFIG_I2C_MV64XXX=y # CONFIG_SENSORS_PCF8574 is not set # CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCF8591 is not set -# CONFIG_TPS65010 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set - -# -# SPI support -# # CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y @@ -872,6 +866,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set @@ -901,6 +896,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VT1211 is not set @@ -910,6 +906,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_W83792D is not set # CONFIG_SENSORS_W83793 is not set # CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set @@ -925,14 +922,24 @@ CONFIG_SSB_POSSIBLE=y # Multifunction device drivers # # CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_PASIC3 is not set # # Multimedia devices # + +# +# Multimedia core support +# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set -CONFIG_DAB=y -# CONFIG_USB_DABUSB is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set # # Graphics support @@ -949,12 +956,6 @@ CONFIG_DAB=y # CONFIG_DISPLAY_SUPPORT is not set # -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y - -# # Sound # # CONFIG_SOUND is not set @@ -985,14 +986,18 @@ CONFIG_USB_DEVICEFS=y CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set # # USB Host Controller Drivers # +# CONFIG_USB_C67X00_HCD is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y # CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set # CONFIG_USB_OHCI_HCD is not set # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set @@ -1003,6 +1008,7 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y # # CONFIG_USB_ACM is not set CONFIG_USB_PRINTER=y +# CONFIG_USB_WDM is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1022,7 +1028,9 @@ CONFIG_USB_STORAGE_SDDR09=y CONFIG_USB_STORAGE_SDDR55=y CONFIG_USB_STORAGE_JUMPSHOT=y # CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set # @@ -1060,6 +1068,7 @@ CONFIG_USB_STORAGE_JUMPSHOT=y # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_GADGET is not set # CONFIG_MMC is not set CONFIG_NEW_LEDS=y @@ -1076,6 +1085,7 @@ CONFIG_LEDS_CLASS=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y CONFIG_RTC_HCTOSYS=y @@ -1105,6 +1115,7 @@ CONFIG_RTC_DRV_RS5C372=y # CONFIG_RTC_DRV_PCF8583 is not set CONFIG_RTC_DRV_M41T80=y # CONFIG_RTC_DRV_M41T80_WDT is not set +# CONFIG_RTC_DRV_S35390A is not set # # SPI RTC drivers @@ -1125,6 +1136,7 @@ CONFIG_RTC_DRV_M41T80=y # # on-CPU RTC drivers # +# CONFIG_UIO is not set # # File systems @@ -1140,14 +1152,11 @@ CONFIG_JBD=y # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set @@ -1155,8 +1164,8 @@ CONFIG_DNOTIFY=y # # CD-ROM/DVD Filesystems # -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y # CONFIG_ZISOFS is not set CONFIG_UDF_FS=m CONFIG_UDF_NLS=y @@ -1205,8 +1214,10 @@ CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set CONFIG_CRAMFS=y # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y @@ -1214,7 +1225,6 @@ CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y @@ -1241,14 +1251,13 @@ CONFIG_PARTITION_ADVANCED=y # CONFIG_MAC_PARTITION is not set CONFIG_MSDOS_PARTITION=y CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_UNIXWARE_DISKLABEL=y -CONFIG_LDM_PARTITION=y -CONFIG_LDM_DEBUG=y +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set # CONFIG_SGI_PARTITION is not set # CONFIG_ULTRIX_PARTITION is not set -CONFIG_SUN_PARTITION=y +# CONFIG_SUN_PARTITION is not set # CONFIG_KARMA_PARTITION is not set # CONFIG_EFI_PARTITION is not set # CONFIG_SYSV68_PARTITION is not set @@ -1300,15 +1309,48 @@ CONFIG_NLS_ISO8859_2=y # CONFIG_PRINTK_TIME is not set CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_MAGIC_SYSRQ is not set +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y +CONFIG_SCHEDSTATS=y +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set # CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_KPROBES_SANITY_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set # CONFIG_SAMPLES is not set CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set # # Security options @@ -1317,50 +1359,79 @@ CONFIG_DEBUG_USER=y # CONFIG_SECURITY is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y + +# +# Crypto core or helper +# CONFIG_CRYPTO_ALGAPI=m CONFIG_CRYPTO_BLKCIPHER=m -# CONFIG_CRYPTO_SEQIV is not set CONFIG_CRYPTO_MANAGER=m +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# # CONFIG_CRYPTO_HMAC is not set # CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_NULL is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_MD4 is not set # CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set # CONFIG_CRYPTO_SHA1 is not set # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_WP512 is not set # CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_GF128MUL is not set -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_XTS is not set -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# # CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# # CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_TEST is not set -# CONFIG_CRYPTO_AUTHENC is not set # CONFIG_CRYPTO_LZO is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set @@ -1369,12 +1440,14 @@ CONFIG_CRYPTO_HW=y # Library routines # CONFIG_BITREVERSE=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -# CONFIG_CRC_ITU_T is not set +# CONFIG_GENERIC_FIND_FIRST_BIT is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +CONFIG_CRC_ITU_T=m CONFIG_CRC32=y # CONFIG_CRC7 is not set -CONFIG_LIBCRC32C=y +# CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y CONFIG_PLIST=y diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c index ae31deb2d06..90e0c35ae60 100644 --- a/arch/arm/kernel/stacktrace.c +++ b/arch/arm/kernel/stacktrace.c @@ -36,6 +36,7 @@ EXPORT_SYMBOL(walk_stackframe); #ifdef CONFIG_STACKTRACE struct stack_trace_data { struct stack_trace *trace; + unsigned int no_sched_functions; unsigned int skip; }; @@ -43,27 +44,52 @@ static int save_trace(struct stackframe *frame, void *d) { struct stack_trace_data *data = d; struct stack_trace *trace = data->trace; + unsigned long addr = frame->lr; + if (data->no_sched_functions && in_sched_functions(addr)) + return 0; if (data->skip) { data->skip--; return 0; } - trace->entries[trace->nr_entries++] = frame->lr; + trace->entries[trace->nr_entries++] = addr; return trace->nr_entries >= trace->max_entries; } -void save_stack_trace(struct stack_trace *trace) +void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) { struct stack_trace_data data; unsigned long fp, base; data.trace = trace; data.skip = trace->skip; - base = (unsigned long)task_stack_page(current); - asm("mov %0, fp" : "=r" (fp)); + base = (unsigned long)task_stack_page(tsk); + + if (tsk != current) { +#ifdef CONFIG_SMP + /* + * What guarantees do we have here that 'tsk' + * is not running on another CPU? + */ + BUG(); +#else + data.no_sched_functions = 1; + fp = thread_saved_fp(tsk); +#endif + } else { + data.no_sched_functions = 0; + asm("mov %0, fp" : "=r" (fp)); + } walk_stackframe(fp, base, base + THREAD_SIZE, save_trace, &data); + if (trace->nr_entries < trace->max_entries) + trace->entries[trace->nr_entries++] = ULONG_MAX; +} + +void save_stack_trace(struct stack_trace *trace) +{ + save_stack_trace_tsk(current, trace); } #endif diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S index cab355c0c1f..139cce64605 100644 --- a/arch/arm/lib/copy_template.S +++ b/arch/arm/lib/copy_template.S @@ -13,14 +13,6 @@ */ /* - * This can be used to enable code to cacheline align the source pointer. - * Experiments on tested architectures (StrongARM and XScale) didn't show - * this a worthwhile thing to do. That might be different in the future. - */ -//#define CALGN(code...) code -#define CALGN(code...) - -/* * Theory of operation * ------------------- * @@ -82,7 +74,7 @@ stmfd sp!, {r5 - r8} blt 5f - CALGN( ands ip, r1, #31 ) + CALGN( ands ip, r0, #31 ) CALGN( rsb r3, ip, #32 ) CALGN( sbcnes r4, r3, r2 ) @ C is always set here CALGN( bcs 2f ) @@ -168,7 +160,7 @@ subs r2, r2, #28 blt 14f - CALGN( ands ip, r1, #31 ) + CALGN( ands ip, r0, #31 ) CALGN( rsb ip, ip, #32 ) CALGN( sbcnes r4, ip, r2 ) @ C is always set here CALGN( subcc r2, r2, ip ) diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S index ef7fddc14ac..2e301b7bd8f 100644 --- a/arch/arm/lib/memmove.S +++ b/arch/arm/lib/memmove.S @@ -13,14 +13,6 @@ #include <linux/linkage.h> #include <asm/assembler.h> -/* - * This can be used to enable code to cacheline align the source pointer. - * Experiments on tested architectures (StrongARM and XScale) didn't show - * this a worthwhile thing to do. That might be different in the future. - */ -//#define CALGN(code...) code -#define CALGN(code...) - .text /* @@ -55,11 +47,12 @@ ENTRY(memmove) stmfd sp!, {r5 - r8} blt 5f - CALGN( ands ip, r1, #31 ) + CALGN( ands ip, r0, #31 ) CALGN( sbcnes r4, ip, r2 ) @ C is always set here CALGN( bcs 2f ) CALGN( adr r4, 6f ) CALGN( subs r2, r2, ip ) @ C is set here + CALGN( rsb ip, ip, #32 ) CALGN( add pc, r4, ip ) PLD( pld [r1, #-4] ) @@ -138,8 +131,7 @@ ENTRY(memmove) subs r2, r2, #28 blt 14f - CALGN( ands ip, r1, #31 ) - CALGN( rsb ip, ip, #32 ) + CALGN( ands ip, r0, #31 ) CALGN( sbcnes r4, ip, r2 ) @ C is always set here CALGN( subcc r2, r2, ip ) CALGN( bcc 15f ) diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index 95b110b07a8..b477d4ac88e 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -39,6 +39,9 @@ ENTRY(memset) mov r3, r1 cmp r2, #16 blt 4f + +#if ! CALGN(1)+0 + /* * We need an extra register for this loop - save the return address and * use the LR @@ -64,6 +67,49 @@ ENTRY(memset) stmneia r0!, {r1, r3, ip, lr} ldr lr, [sp], #4 +#else + +/* + * This version aligns the destination pointer in order to write + * whole cache lines at once. + */ + + stmfd sp!, {r4-r7, lr} + mov r4, r1 + mov r5, r1 + mov r6, r1 + mov r7, r1 + mov ip, r1 + mov lr, r1 + + cmp r2, #96 + tstgt r0, #31 + ble 3f + + and ip, r0, #31 + rsb ip, ip, #32 + sub r2, r2, ip + movs ip, ip, lsl #(32 - 4) + stmcsia r0!, {r4, r5, r6, r7} + stmmiia r0!, {r4, r5} + tst ip, #(1 << 30) + mov ip, r1 + strne r1, [r0], #4 + +3: subs r2, r2, #64 + stmgeia r0!, {r1, r3-r7, ip, lr} + stmgeia r0!, {r1, r3-r7, ip, lr} + bgt 3b + ldmeqfd sp!, {r4-r7, pc} + + tst r2, #32 + stmneia r0!, {r1, r3-r7, ip, lr} + tst r2, #16 + stmneia r0!, {r4-r7} + ldmfd sp!, {r4-r7, lr} + +#endif + 4: tst r2, #8 stmneia r0!, {r1, r3} tst r2, #4 diff --git a/arch/arm/lib/memzero.S b/arch/arm/lib/memzero.S index abf2508e822..b8f79d80ee9 100644 --- a/arch/arm/lib/memzero.S +++ b/arch/arm/lib/memzero.S @@ -39,6 +39,9 @@ ENTRY(__memzero) */ cmp r1, #16 @ 1 we can skip this chunk if we blt 4f @ 1 have < 16 bytes + +#if ! CALGN(1)+0 + /* * We need an extra register for this loop - save the return address and * use the LR @@ -64,6 +67,47 @@ ENTRY(__memzero) stmneia r0!, {r2, r3, ip, lr} @ 4 ldr lr, [sp], #4 @ 1 +#else + +/* + * This version aligns the destination pointer in order to write + * whole cache lines at once. + */ + + stmfd sp!, {r4-r7, lr} + mov r4, r2 + mov r5, r2 + mov r6, r2 + mov r7, r2 + mov ip, r2 + mov lr, r2 + + cmp r1, #96 + andgts ip, r0, #31 + ble 3f + + rsb ip, ip, #32 + sub r1, r1, ip + movs ip, ip, lsl #(32 - 4) + stmcsia r0!, {r4, r5, r6, r7} + stmmiia r0!, {r4, r5} + movs ip, ip, lsl #2 + strcs r2, [r0], #4 + +3: subs r1, r1, #64 + stmgeia r0!, {r2-r7, ip, lr} + stmgeia r0!, {r2-r7, ip, lr} + bgt 3b + ldmeqfd sp!, {r4-r7, pc} + + tst r1, #32 + stmneia r0!, {r2-r7, ip, lr} + tst r1, #16 + stmneia r0!, {r4-r7} + ldmfd sp!, {r4-r7, lr} + +#endif + 4: tst r1, #8 @ 1 8 bytes or more? stmneia r0!, {r2, r3} @ 2 tst r1, #4 @ 1 4 bytes or more? diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig new file mode 100644 index 00000000000..3600cd9f051 --- /dev/null +++ b/arch/arm/mach-kirkwood/Kconfig @@ -0,0 +1,25 @@ +if ARCH_KIRKWOOD + +menu "Marvell Kirkwood Implementations" + +config MACH_DB88F6281_BP + bool "Marvell DB-88F6281-BP Development Board" + help + Say 'Y' here if you want your kernel to support the + Marvell DB-88F6281-BP Development Board. + +config MACH_RD88F6192_NAS + bool "Marvell RD-88F6192-NAS Reference Board" + help + Say 'Y' here if you want your kernel to support the + Marvell RD-88F6192-NAS Reference Board. + +config MACH_RD88F6281 + bool "Marvell RD-88F6281 Reference Board" + help + Say 'Y' here if you want your kernel to support the + Marvell RD-88F6281 Reference Board. + +endmenu + +endif diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile new file mode 100644 index 00000000000..e14bf40bfb0 --- /dev/null +++ b/arch/arm/mach-kirkwood/Makefile @@ -0,0 +1,5 @@ +obj-y += common.o addr-map.o irq.o pcie.o + +obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o +obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o +obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6281-setup.o diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot new file mode 100644 index 00000000000..67039c3e0c4 --- /dev/null +++ b/arch/arm/mach-kirkwood/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c new file mode 100644 index 00000000000..a39f0f3c473 --- /dev/null +++ b/arch/arm/mach-kirkwood/addr-map.c @@ -0,0 +1,139 @@ +/* + * arch/arm/mach-kirkwood/addr-map.c + * + * Address map functions for Marvell Kirkwood SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mbus.h> +#include <linux/io.h> +#include <asm/hardware.h> +#include "common.h" + +/* + * Generic Address Decode Windows bit settings + */ +#define TARGET_DDR 0 +#define TARGET_DEV_BUS 1 +#define TARGET_PCIE 4 +#define ATTR_DEV_SPI_ROM 0x1e +#define ATTR_DEV_BOOT 0x1d +#define ATTR_DEV_NAND 0x2f +#define ATTR_DEV_CS3 0x37 +#define ATTR_DEV_CS2 0x3b +#define ATTR_DEV_CS1 0x3d +#define ATTR_DEV_CS0 0x3e +#define ATTR_PCIE_IO 0xe0 +#define ATTR_PCIE_MEM 0xe8 + +/* + * Helpers to get DDR bank info + */ +#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) +#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) + +/* + * CPU Address Decode Windows registers + */ +#define WIN_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) +#define WIN_CTRL_OFF 0x0000 +#define WIN_BASE_OFF 0x0004 +#define WIN_REMAP_LO_OFF 0x0008 +#define WIN_REMAP_HI_OFF 0x000c + + +struct mbus_dram_target_info kirkwood_mbus_dram_info; + +static int __init cpu_win_can_remap(int win) +{ + if (win < 4) + return 1; + + return 0; +} + +static void __init setup_cpu_win(int win, u32 base, u32 size, + u8 target, u8 attr, int remap) +{ + void __iomem *addr = (void __iomem *)WIN_OFF(win); + u32 ctrl; + + base &= 0xffff0000; + ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; + + writel(base, addr + WIN_BASE_OFF); + writel(ctrl, addr + WIN_CTRL_OFF); + if (cpu_win_can_remap(win)) { + if (remap < 0) + remap = base; + + writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF); + writel(0, addr + WIN_REMAP_HI_OFF); + } +} + +void __init kirkwood_setup_cpu_mbus(void) +{ + void __iomem *addr; + int i; + int cs; + + /* + * First, disable and clear windows. + */ + for (i = 0; i < 8; i++) { + addr = (void __iomem *)WIN_OFF(i); + + writel(0, addr + WIN_BASE_OFF); + writel(0, addr + WIN_CTRL_OFF); + if (cpu_win_can_remap(i)) { + writel(0, addr + WIN_REMAP_LO_OFF); + writel(0, addr + WIN_REMAP_HI_OFF); + } + } + + /* + * Setup windows for PCIe IO+MEM space. + */ + setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE, + TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE); + setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, + TARGET_PCIE, ATTR_PCIE_MEM, -1); + + /* + * Setup window for NAND controller. + */ + setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, + TARGET_DEV_BUS, ATTR_DEV_NAND, -1); + + /* + * Setup MBUS dram target info. + */ + kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + + addr = (void __iomem *)DDR_WINDOW_CPU_BASE; + + for (i = 0, cs = 0; i < 4; i++) { + u32 base = readl(addr + DDR_BASE_CS_OFF(i)); + u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); + + /* + * Chip select enabled? + */ + if (size & 1) { + struct mbus_dram_window *w; + + w = &kirkwood_mbus_dram_info.cs[cs++]; + w->cs_index = i; + w->mbus_attr = 0xf & ~(1 << i); + w->base = base & 0xffff0000; + w->size = (size | 0x0000ffff) + 1; + } + } + kirkwood_mbus_dram_info.num_cs = cs; +} diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c new file mode 100644 index 00000000000..5938a3b33cd --- /dev/null +++ b/arch/arm/mach-kirkwood/common.c @@ -0,0 +1,331 @@ +/* + * arch/arm/mach-kirkwood/common.c + * + * Core functions for Marvell Kirkwood SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/mbus.h> +#include <linux/mv643xx_eth.h> +#include <linux/ata_platform.h> +#include <asm/page.h> +#include <asm/timex.h> +#include <asm/mach/map.h> +#include <asm/mach/time.h> +#include <asm/arch/kirkwood.h> +#include <asm/plat-orion/cache-feroceon-l2.h> +#include <asm/plat-orion/ehci-orion.h> +#include <asm/plat-orion/orion_nand.h> +#include <asm/plat-orion/time.h> +#include "common.h" + +/***************************************************************************** + * I/O Address Mapping + ****************************************************************************/ +static struct map_desc kirkwood_io_desc[] __initdata = { + { + .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE, + .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE), + .length = KIRKWOOD_PCIE_IO_SIZE, + .type = MT_DEVICE, + }, { + .virtual = KIRKWOOD_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), + .length = KIRKWOOD_REGS_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init kirkwood_map_io(void) +{ + iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc)); +} + + +/***************************************************************************** + * EHCI + ****************************************************************************/ +static struct orion_ehci_data kirkwood_ehci_data = { + .dram = &kirkwood_mbus_dram_info, +}; + +static u64 ehci_dmamask = 0xffffffffUL; + + +/***************************************************************************** + * EHCI0 + ****************************************************************************/ +static struct resource kirkwood_ehci_resources[] = { + { + .start = USB_PHYS_BASE, + .end = USB_PHYS_BASE + 0x0fff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_KIRKWOOD_USB, + .end = IRQ_KIRKWOOD_USB, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device kirkwood_ehci = { + .name = "orion-ehci", + .id = 0, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &kirkwood_ehci_data, + }, + .resource = kirkwood_ehci_resources, + .num_resources = ARRAY_SIZE(kirkwood_ehci_resources), +}; + +void __init kirkwood_ehci_init(void) +{ + platform_device_register(&kirkwood_ehci); +} + + +/***************************************************************************** + * GE00 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = { + .t_clk = KIRKWOOD_TCLK, + .dram = &kirkwood_mbus_dram_info, +}; + +static struct resource kirkwood_ge00_shared_resources[] = { + { + .name = "ge00 base", + .start = GE00_PHYS_BASE + 0x2000, + .end = GE00_PHYS_BASE + 0x3fff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device kirkwood_ge00_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 0, + .dev = { + .platform_data = &kirkwood_ge00_shared_data, + }, + .num_resources = 1, + .resource = kirkwood_ge00_shared_resources, +}; + +static struct resource kirkwood_ge00_resources[] = { + { + .name = "ge00 irq", + .start = IRQ_KIRKWOOD_GE00_SUM, + .end = IRQ_KIRKWOOD_GE00_SUM, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device kirkwood_ge00 = { + .name = MV643XX_ETH_NAME, + .id = 0, + .num_resources = 1, + .resource = kirkwood_ge00_resources, +}; + +void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) +{ + eth_data->shared = &kirkwood_ge00_shared; + kirkwood_ge00.dev.platform_data = eth_data; + + platform_device_register(&kirkwood_ge00_shared); + platform_device_register(&kirkwood_ge00); +} + + +/***************************************************************************** + * SoC RTC + ****************************************************************************/ +static struct resource kirkwood_rtc_resource = { + .start = RTC_PHYS_BASE, + .end = RTC_PHYS_BASE + SZ_16 - 1, + .flags = IORESOURCE_MEM, +}; + +void __init kirkwood_rtc_init(void) +{ + platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1); +} + + +/***************************************************************************** + * SATA + ****************************************************************************/ +static struct resource kirkwood_sata_resources[] = { + { + .name = "sata base", + .start = SATA_PHYS_BASE, + .end = SATA_PHYS_BASE + 0x5000 - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "sata irq", + .start = IRQ_KIRKWOOD_SATA, + .end = IRQ_KIRKWOOD_SATA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device kirkwood_sata = { + .name = "sata_mv", + .id = 0, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(kirkwood_sata_resources), + .resource = kirkwood_sata_resources, +}; + +void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) +{ + sata_data->dram = &kirkwood_mbus_dram_info; + kirkwood_sata.dev.platform_data = sata_data; + platform_device_register(&kirkwood_sata); +} + + +/***************************************************************************** + * UART0 + ****************************************************************************/ +static struct plat_serial8250_port kirkwood_uart0_data[] = { + { + .mapbase = UART0_PHYS_BASE, + .membase = (char *)UART0_VIRT_BASE, + .irq = IRQ_KIRKWOOD_UART_0, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = KIRKWOOD_TCLK, + }, { + }, +}; + +static struct resource kirkwood_uart0_resources[] = { + { + .start = UART0_PHYS_BASE, + .end = UART0_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_KIRKWOOD_UART_0, + .end = IRQ_KIRKWOOD_UART_0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device kirkwood_uart0 = { + .name = "serial8250", + .id = 0, + .dev = { + .platform_data = kirkwood_uart0_data, + }, + .resource = kirkwood_uart0_resources, + .num_resources = ARRAY_SIZE(kirkwood_uart0_resources), +}; + +void __init kirkwood_uart0_init(void) +{ + platform_device_register(&kirkwood_uart0); +} + + +/***************************************************************************** + * UART1 + ****************************************************************************/ +static struct plat_serial8250_port kirkwood_uart1_data[] = { + { + .mapbase = UART1_PHYS_BASE, + .membase = (char *)UART1_VIRT_BASE, + .irq = IRQ_KIRKWOOD_UART_1, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = KIRKWOOD_TCLK, + }, { + }, +}; + +static struct resource kirkwood_uart1_resources[] = { + { + .start = UART1_PHYS_BASE, + .end = UART1_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_KIRKWOOD_UART_1, + .end = IRQ_KIRKWOOD_UART_1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device kirkwood_uart1 = { + .name = "serial8250", + .id = 1, + .dev = { + .platform_data = kirkwood_uart1_data, + }, + .resource = kirkwood_uart1_resources, + .num_resources = ARRAY_SIZE(kirkwood_uart1_resources), +}; + +void __init kirkwood_uart1_init(void) +{ + platform_device_register(&kirkwood_uart1); +} + + +/***************************************************************************** + * Time handling + ****************************************************************************/ +static void kirkwood_timer_init(void) +{ + orion_time_init(IRQ_KIRKWOOD_BRIDGE, KIRKWOOD_TCLK); +} + +struct sys_timer kirkwood_timer = { + .init = kirkwood_timer_init, +}; + + +/***************************************************************************** + * General + ****************************************************************************/ +static char * __init kirkwood_id(void) +{ + switch (readl(DEVICE_ID) & 0x3) { + case 0: + return "88F6180"; + case 1: + return "88F6192"; + case 2: + return "88F6281"; + } + + return "unknown 88F6000 variant"; +} + +static int __init is_l2_writethrough(void) +{ + return !!(readl(L2_CONFIG_REG) & L2_WRITETHROUGH); +} + +void __init kirkwood_init(void) +{ + printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n", + kirkwood_id(), KIRKWOOD_TCLK); + + kirkwood_setup_cpu_mbus(); + +#ifdef CONFIG_CACHE_FEROCEON_L2 + feroceon_l2_init(is_l2_writethrough()); +#endif +} diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h new file mode 100644 index 00000000000..5dee2f6b40a --- /dev/null +++ b/arch/arm/mach-kirkwood/common.h @@ -0,0 +1,42 @@ +/* + * arch/arm/mach-kirkwood/common.h + * + * Core functions for Marvell Kirkwood SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ARCH_KIRKWOOD_COMMON_H +#define __ARCH_KIRKWOOD_COMMON_H + +struct mv643xx_eth_platform_data; +struct mv_sata_platform_data; + +/* + * Basic Kirkwood init functions used early by machine-setup. + */ +void kirkwood_map_io(void); +void kirkwood_init(void); +void kirkwood_init_irq(void); + +extern struct mbus_dram_target_info kirkwood_mbus_dram_info; +void kirkwood_setup_cpu_mbus(void); +void kirkwood_setup_pcie_io_win(int window, u32 base, u32 size, + int maj, int min); +void kirkwood_setup_pcie_mem_win(int window, u32 base, u32 size, + int maj, int min); + +void kirkwood_ehci_init(void); +void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data); +void kirkwood_pcie_init(void); +void kirkwood_rtc_init(void); +void kirkwood_sata_init(struct mv_sata_platform_data *sata_data); +void kirkwood_uart0_init(void); +void kirkwood_uart1_init(void); + +extern struct sys_timer kirkwood_timer; + + +#endif diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c new file mode 100644 index 00000000000..d5c482c628e --- /dev/null +++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c @@ -0,0 +1,68 @@ +/* + * arch/arm/mach-kirkwood/db88f6281-bp-setup.c + * + * Marvell DB-88F6281-BP Development Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pci.h> +#include <linux/irq.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/nand.h> +#include <linux/timer.h> +#include <linux/ata_platform.h> +#include <linux/mv643xx_eth.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/pci.h> +#include <asm/arch/kirkwood.h> +#include "common.h" + +static struct mv643xx_eth_platform_data db88f6281_ge00_data = { + .phy_addr = 8, +}; + +static struct mv_sata_platform_data db88f6281_sata_data = { + .n_ports = 2, +}; + +static void __init db88f6281_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_init(); + + kirkwood_ehci_init(); + kirkwood_ge00_init(&db88f6281_ge00_data); + kirkwood_rtc_init(); + kirkwood_sata_init(&db88f6281_sata_data); + kirkwood_uart0_init(); + kirkwood_uart1_init(); +} + +static int __init db88f6281_pci_init(void) +{ + if (machine_is_db88f6281_bp()) + kirkwood_pcie_init(); + + return 0; +} +subsys_initcall(db88f6281_pci_init); + +MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board") + /* Maintainer: Saeed Bishara <saeed@marvell.com> */ + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = db88f6281_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c new file mode 100644 index 00000000000..302bb2cf666 --- /dev/null +++ b/arch/arm/mach-kirkwood/irq.c @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-kirkwood/irq.c + * + * Kirkwood IRQ handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <asm/plat-orion/irq.h> +#include "common.h" + +void __init kirkwood_init_irq(void) +{ + orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); + orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); +} diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c new file mode 100644 index 00000000000..8282d0ff84b --- /dev/null +++ b/arch/arm/mach-kirkwood/pcie.c @@ -0,0 +1,180 @@ +/* + * arch/arm/mach-kirkwood/pcie.c + * + * PCIe functions for Marvell Kirkwood SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/mbus.h> +#include <asm/mach/pci.h> +#include <asm/plat-orion/pcie.h> +#include "common.h" + + +#define PCIE_BASE ((void __iomem *)PCIE_VIRT_BASE) + +static int pcie_valid_config(int bus, int dev) +{ + /* + * Don't go out when trying to access -- + * 1. nonexisting device on local bus + * 2. where there's no device connected (no link) + */ + if (bus == 0 && dev == 0) + return 1; + + if (!orion_pcie_link_up(PCIE_BASE)) + return 0; + + if (bus == 0 && dev != 1) + return 0; + + return 1; +} + + +/* + * PCIe config cycles are done by programming the PCIE_CONF_ADDR register + * and then reading the PCIE_CONF_DATA register. Need to make sure these + * transactions are atomic. + */ +static DEFINE_SPINLOCK(kirkwood_pcie_lock); + +static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) +{ + unsigned long flags; + int ret; + + if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + spin_lock_irqsave(&kirkwood_pcie_lock, flags); + ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val); + spin_unlock_irqrestore(&kirkwood_pcie_lock, flags); + + return ret; +} + +static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 val) +{ + unsigned long flags; + int ret; + + if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + spin_lock_irqsave(&kirkwood_pcie_lock, flags); + ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val); + spin_unlock_irqrestore(&kirkwood_pcie_lock, flags); + + return ret; +} + +static struct pci_ops pcie_ops = { + .read = pcie_rd_conf, + .write = pcie_wr_conf, +}; + + +static int kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) +{ + struct resource *res; + + /* + * Generic PCIe unit setup. + */ + orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info); + + /* + * Request resources. + */ + res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); + if (!res) + panic("pcie_setup unable to alloc resources"); + + /* + * IORESOURCE_IO + */ + res[0].name = "PCIe I/O Space"; + res[0].flags = IORESOURCE_IO; + res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE; + res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1; + if (request_resource(&ioport_resource, &res[0])) + panic("Request PCIe IO resource failed\n"); + sys->resource[0] = &res[0]; + + /* + * IORESOURCE_MEM + */ + res[1].name = "PCIe Memory Space"; + res[1].flags = IORESOURCE_MEM; + res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE; + res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; + if (request_resource(&iomem_resource, &res[1])) + panic("Request PCIe Memory resource failed\n"); + sys->resource[1] = &res[1]; + + sys->resource[2] = NULL; + sys->io_offset = 0; + + return 1; +} + +static void __devinit rc_pci_fixup(struct pci_dev *dev) +{ + /* + * Prevent enumeration of root complex. + */ + if (dev->bus->parent == NULL && dev->devfn == 0) { + int i; + + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { + dev->resource[i].start = 0; + dev->resource[i].end = 0; + dev->resource[i].flags = 0; + } + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); + +static struct pci_bus __init * +kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys) +{ + struct pci_bus *bus; + + if (nr == 0) { + bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); + } else { + bus = NULL; + BUG(); + } + + return bus; +} + +static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + return IRQ_KIRKWOOD_PCIE; +} + +static struct hw_pci kirkwood_pci __initdata = { + .nr_controllers = 1, + .swizzle = pci_std_swizzle, + .setup = kirkwood_pcie_setup, + .scan = kirkwood_pcie_scan_bus, + .map_irq = kirkwood_pcie_map_irq, +}; + +void __init kirkwood_pcie_init(void) +{ + pci_common_init(&kirkwood_pci); +} diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c new file mode 100644 index 00000000000..6cf642c504d --- /dev/null +++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c @@ -0,0 +1,69 @@ +/* + * arch/arm/mach-kirkwood/rd88f6192-nas-setup.c + * + * Marvell RD-88F6192-NAS Reference Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pci.h> +#include <linux/irq.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/nand.h> +#include <linux/timer.h> +#include <linux/ata_platform.h> +#include <linux/mv643xx_eth.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/pci.h> +#include <asm/arch/kirkwood.h> +#include "common.h" + +#define RD88F6192_GPIO_USB_VBUS 10 + +static struct mv643xx_eth_platform_data rd88f6192_ge00_data = { + .phy_addr = 8, +}; + +static struct mv_sata_platform_data rd88f6192_sata_data = { + .n_ports = 2, +}; + +static void __init rd88f6192_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_init(); + + kirkwood_ehci_init(); + kirkwood_ge00_init(&rd88f6192_ge00_data); + kirkwood_rtc_init(); + kirkwood_sata_init(&rd88f6192_sata_data); + kirkwood_uart0_init(); +} + +static int __init rd88f6192_pci_init(void) +{ + if (machine_is_rd88f6192_nas()) + kirkwood_pcie_init(); + + return 0; +} +subsys_initcall(rd88f6192_pci_init); + +MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board") + /* Maintainer: Saeed Bishara <saeed@marvell.com> */ + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = rd88f6192_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c new file mode 100644 index 00000000000..e1f8de2c74a --- /dev/null +++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c @@ -0,0 +1,113 @@ +/* + * arch/arm/mach-kirkwood/rd88f6281-setup.c + * + * Marvell RD-88F6281 Reference Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pci.h> +#include <linux/irq.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/nand.h> +#include <linux/timer.h> +#include <linux/ata_platform.h> +#include <linux/mv643xx_eth.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/pci.h> +#include <asm/arch/kirkwood.h> +#include <asm/plat-orion/orion_nand.h> +#include "common.h" + +static struct mtd_partition rd88f6281_nand_parts[] = { + { + .name = "u-boot", + .offset = 0, + .size = SZ_1M + }, { + .name = "uImage", + .offset = MTDPART_OFS_NXTBLK, + .size = SZ_2M + }, { + .name = "root", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL + }, +}; + +static struct resource rd88f6281_nand_resource = { + .flags = IORESOURCE_MEM, + .start = KIRKWOOD_NAND_MEM_PHYS_BASE, + .end = KIRKWOOD_NAND_MEM_PHYS_BASE + + KIRKWOOD_NAND_MEM_SIZE - 1, +}; + +static struct orion_nand_data rd88f6281_nand_data = { + .parts = rd88f6281_nand_parts, + .nr_parts = ARRAY_SIZE(rd88f6281_nand_parts), + .cle = 0, + .ale = 1, + .width = 8, + .chip_delay = 25, +}; + +static struct platform_device rd88f6281_nand_flash = { + .name = "orion_nand", + .id = -1, + .dev = { + .platform_data = &rd88f6281_nand_data, + }, + .resource = &rd88f6281_nand_resource, + .num_resources = 1, +}; + +static struct mv643xx_eth_platform_data rd88f6281_ge00_data = { + .phy_addr = -1, +}; + +static struct mv_sata_platform_data rd88f6281_sata_data = { + .n_ports = 2, +}; + +static void __init rd88f6281_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_init(); + + kirkwood_ehci_init(); + kirkwood_ge00_init(&rd88f6281_ge00_data); + kirkwood_rtc_init(); + kirkwood_sata_init(&rd88f6281_sata_data); + kirkwood_uart0_init(); + kirkwood_uart1_init(); + + platform_device_register(&rd88f6281_nand_flash); +} + +static int __init rd88f6281_pci_init(void) +{ + if (machine_is_rd88f6281()) + kirkwood_pcie_init(); + + return 0; +} +subsys_initcall(rd88f6281_pci_init); + +MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board") + /* Maintainer: Saeed Bishara <saeed@marvell.com> */ + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = rd88f6281_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END diff --git a/arch/arm/mach-loki/Kconfig b/arch/arm/mach-loki/Kconfig new file mode 100644 index 00000000000..0045bdd761c --- /dev/null +++ b/arch/arm/mach-loki/Kconfig @@ -0,0 +1,13 @@ +if ARCH_LOKI + +menu "Marvell Loki (88RC8480) Implementations" + +config MACH_LB88RC8480 + bool "Marvell LB88RC8480 Development Board" + help + Say 'Y' here if you want your kernel to support the + Marvell LB88RC8480 Development Board. + +endmenu + +endif diff --git a/arch/arm/mach-loki/Makefile b/arch/arm/mach-loki/Makefile new file mode 100644 index 00000000000..d43233ee590 --- /dev/null +++ b/arch/arm/mach-loki/Makefile @@ -0,0 +1,3 @@ +obj-y += common.o addr-map.o irq.o + +obj-$(CONFIG_MACH_LB88RC8480) += lb88rc8480-setup.o diff --git a/arch/arm/mach-loki/Makefile.boot b/arch/arm/mach-loki/Makefile.boot new file mode 100644 index 00000000000..67039c3e0c4 --- /dev/null +++ b/arch/arm/mach-loki/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-loki/addr-map.c b/arch/arm/mach-loki/addr-map.c new file mode 100644 index 00000000000..ba25e56ade5 --- /dev/null +++ b/arch/arm/mach-loki/addr-map.c @@ -0,0 +1,121 @@ +/* + * arch/arm/mach-loki/addr-map.c + * + * Address map functions for Marvell Loki (88RC8480) SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mbus.h> +#include <asm/hardware.h> +#include <asm/io.h> +#include "common.h" + +/* + * Generic Address Decode Windows bit settings + */ +#define TARGET_DDR 0 +#define TARGET_DEV_BUS 1 +#define TARGET_PCIE0 3 +#define TARGET_PCIE1 4 +#define ATTR_DEV_BOOT 0x0f +#define ATTR_DEV_CS2 0x1b +#define ATTR_DEV_CS1 0x1d +#define ATTR_DEV_CS0 0x1e +#define ATTR_PCIE_IO 0x51 +#define ATTR_PCIE_MEM 0x59 + +/* + * Helpers to get DDR bank info + */ +#define DDR_SIZE_CS(n) DDR_REG(0x1500 + ((n) << 3)) +#define DDR_BASE_CS(n) DDR_REG(0x1504 + ((n) << 3)) + +/* + * CPU Address Decode Windows registers + */ +#define CPU_WIN_CTRL(n) BRIDGE_REG(0x000 | ((n) << 4)) +#define CPU_WIN_BASE(n) BRIDGE_REG(0x004 | ((n) << 4)) +#define CPU_WIN_REMAP_LO(n) BRIDGE_REG(0x008 | ((n) << 4)) +#define CPU_WIN_REMAP_HI(n) BRIDGE_REG(0x00c | ((n) << 4)) + + +struct mbus_dram_target_info loki_mbus_dram_info; + +static void __init setup_cpu_win(int win, u32 base, u32 size, + u8 target, u8 attr, int remap) +{ + u32 ctrl; + + base &= 0xffff0000; + ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (1 << 5) | target; + + writel(base, CPU_WIN_BASE(win)); + writel(ctrl, CPU_WIN_CTRL(win)); + if (win < 2) { + if (remap < 0) + remap = base; + + writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win)); + writel(0, CPU_WIN_REMAP_HI(win)); + } +} + +void __init loki_setup_cpu_mbus(void) +{ + int i; + int cs; + + /* + * First, disable and clear windows. + */ + for (i = 0; i < 8; i++) { + writel(0, CPU_WIN_BASE(i)); + writel(0, CPU_WIN_CTRL(i)); + if (i < 2) { + writel(0, CPU_WIN_REMAP_LO(i)); + writel(0, CPU_WIN_REMAP_HI(i)); + } + } + + /* + * Setup windows for PCIe IO+MEM space. + */ + setup_cpu_win(2, LOKI_PCIE0_MEM_PHYS_BASE, LOKI_PCIE0_MEM_SIZE, + TARGET_PCIE0, ATTR_PCIE_MEM, -1); + setup_cpu_win(3, LOKI_PCIE1_MEM_PHYS_BASE, LOKI_PCIE1_MEM_SIZE, + TARGET_PCIE1, ATTR_PCIE_MEM, -1); + + /* + * Setup MBUS dram target info. + */ + loki_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + + for (i = 0, cs = 0; i < 4; i++) { + u32 base = readl(DDR_BASE_CS(i)); + u32 size = readl(DDR_SIZE_CS(i)); + + /* + * Chip select enabled? + */ + if (size & 1) { + struct mbus_dram_window *w; + + w = &loki_mbus_dram_info.cs[cs++]; + w->cs_index = i; + w->mbus_attr = 0xf & ~(1 << i); + w->base = base & 0xffff0000; + w->size = (size | 0x0000ffff) + 1; + } + } + loki_mbus_dram_info.num_cs = cs; +} + +void __init loki_setup_dev_boot_win(u32 base, u32 size) +{ + setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); +} diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c new file mode 100644 index 00000000000..410f50399dd --- /dev/null +++ b/arch/arm/mach-loki/common.c @@ -0,0 +1,305 @@ +/* + * arch/arm/mach-loki/common.c + * + * Core functions for Marvell Loki (88RC8480) SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/mbus.h> +#include <linux/mv643xx_eth.h> +#include <asm/page.h> +#include <asm/timex.h> +#include <asm/mach/map.h> +#include <asm/mach/time.h> +#include <asm/arch/loki.h> +#include <asm/plat-orion/orion_nand.h> +#include <asm/plat-orion/time.h> +#include "common.h" + +/***************************************************************************** + * I/O Address Mapping + ****************************************************************************/ +static struct map_desc loki_io_desc[] __initdata = { + { + .virtual = LOKI_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(LOKI_REGS_PHYS_BASE), + .length = LOKI_REGS_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init loki_map_io(void) +{ + iotable_init(loki_io_desc, ARRAY_SIZE(loki_io_desc)); +} + + +/***************************************************************************** + * GE0 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data loki_ge0_shared_data = { + .t_clk = LOKI_TCLK, + .dram = &loki_mbus_dram_info, +}; + +static struct resource loki_ge0_shared_resources[] = { + { + .name = "ge0 base", + .start = GE0_PHYS_BASE + 0x2000, + .end = GE0_PHYS_BASE + 0x3fff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device loki_ge0_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 0, + .dev = { + .platform_data = &loki_ge0_shared_data, + }, + .num_resources = 1, + .resource = loki_ge0_shared_resources, +}; + +static struct resource loki_ge0_resources[] = { + { + .name = "ge0 irq", + .start = IRQ_LOKI_GBE_A_INT, + .end = IRQ_LOKI_GBE_A_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device loki_ge0 = { + .name = MV643XX_ETH_NAME, + .id = 0, + .num_resources = 1, + .resource = loki_ge0_resources, +}; + +void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data) +{ + eth_data->shared = &loki_ge0_shared; + loki_ge0.dev.platform_data = eth_data; + + writel(0x00079220, GE0_VIRT_BASE + 0x20b0); + platform_device_register(&loki_ge0_shared); + platform_device_register(&loki_ge0); +} + + +/***************************************************************************** + * GE1 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data loki_ge1_shared_data = { + .t_clk = LOKI_TCLK, + .dram = &loki_mbus_dram_info, +}; + +static struct resource loki_ge1_shared_resources[] = { + { + .name = "ge1 base", + .start = GE1_PHYS_BASE + 0x2000, + .end = GE1_PHYS_BASE + 0x3fff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device loki_ge1_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 1, + .dev = { + .platform_data = &loki_ge1_shared_data, + }, + .num_resources = 1, + .resource = loki_ge1_shared_resources, +}; + +static struct resource loki_ge1_resources[] = { + { + .name = "ge1 irq", + .start = IRQ_LOKI_GBE_B_INT, + .end = IRQ_LOKI_GBE_B_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device loki_ge1 = { + .name = MV643XX_ETH_NAME, + .id = 1, + .num_resources = 1, + .resource = loki_ge1_resources, +}; + +void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data) +{ + eth_data->shared = &loki_ge1_shared; + loki_ge1.dev.platform_data = eth_data; + + writel(0x00079220, GE1_VIRT_BASE + 0x20b0); + platform_device_register(&loki_ge1_shared); + platform_device_register(&loki_ge1); +} + + +/***************************************************************************** + * SAS/SATA + ****************************************************************************/ +static struct resource loki_sas_resources[] = { + { + .name = "mvsas0 mem", + .start = SAS0_PHYS_BASE, + .end = SAS0_PHYS_BASE + 0x01ff, + .flags = IORESOURCE_MEM, + }, { + .name = "mvsas0 irq", + .start = IRQ_LOKI_SAS_A, + .end = IRQ_LOKI_SAS_A, + .flags = IORESOURCE_IRQ, + }, { + .name = "mvsas1 mem", + .start = SAS1_PHYS_BASE, + .end = SAS1_PHYS_BASE + 0x01ff, + .flags = IORESOURCE_MEM, + }, { + .name = "mvsas1 irq", + .start = IRQ_LOKI_SAS_B, + .end = IRQ_LOKI_SAS_B, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device loki_sas = { + .name = "mvsas", + .id = 0, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(loki_sas_resources), + .resource = loki_sas_resources, +}; + +void __init loki_sas_init(void) +{ + writel(0x8300f707, DDR_REG(0x1424)); + platform_device_register(&loki_sas); +} + + +/***************************************************************************** + * UART0 + ****************************************************************************/ +static struct plat_serial8250_port loki_uart0_data[] = { + { + .mapbase = UART0_PHYS_BASE, + .membase = (char *)UART0_VIRT_BASE, + .irq = IRQ_LOKI_UART0, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = LOKI_TCLK, + }, { + }, +}; + +static struct resource loki_uart0_resources[] = { + { + .start = UART0_PHYS_BASE, + .end = UART0_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_LOKI_UART0, + .end = IRQ_LOKI_UART0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device loki_uart0 = { + .name = "serial8250", + .id = 0, + .dev = { + .platform_data = loki_uart0_data, + }, + .resource = loki_uart0_resources, + .num_resources = ARRAY_SIZE(loki_uart0_resources), +}; + +void __init loki_uart0_init(void) +{ + platform_device_register(&loki_uart0); +} + + +/***************************************************************************** + * UART1 + ****************************************************************************/ +static struct plat_serial8250_port loki_uart1_data[] = { + { + .mapbase = UART1_PHYS_BASE, + .membase = (char *)UART1_VIRT_BASE, + .irq = IRQ_LOKI_UART1, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = LOKI_TCLK, + }, { + }, +}; + +static struct resource loki_uart1_resources[] = { + { + .start = UART1_PHYS_BASE, + .end = UART1_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_LOKI_UART1, + .end = IRQ_LOKI_UART1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device loki_uart1 = { + .name = "serial8250", + .id = 1, + .dev = { + .platform_data = loki_uart1_data, + }, + .resource = loki_uart1_resources, + .num_resources = ARRAY_SIZE(loki_uart1_resources), +}; + +void __init loki_uart1_init(void) +{ + platform_device_register(&loki_uart1); +} + + +/***************************************************************************** + * Time handling + ****************************************************************************/ +static void loki_timer_init(void) +{ + orion_time_init(IRQ_LOKI_BRIDGE, LOKI_TCLK); +} + +struct sys_timer loki_timer = { + .init = loki_timer_init, +}; + + +/***************************************************************************** + * General + ****************************************************************************/ +void __init loki_init(void) +{ + printk(KERN_INFO "Loki ID: 88RC8480. TCLK=%d.\n", LOKI_TCLK); + + loki_setup_cpu_mbus(); +} diff --git a/arch/arm/mach-loki/common.h b/arch/arm/mach-loki/common.h new file mode 100644 index 00000000000..26054fd0f05 --- /dev/null +++ b/arch/arm/mach-loki/common.h @@ -0,0 +1,36 @@ +/* + * arch/arm/mach-loki/common.h + * + * Core functions for Marvell Loki (88RC8480) SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ARCH_LOKI_COMMON_H +#define __ARCH_LOKI_COMMON_H + +struct mv643xx_eth_platform_data; + +/* + * Basic Loki init functions used early by machine-setup. + */ +void loki_map_io(void); +void loki_init(void); +void loki_init_irq(void); + +extern struct mbus_dram_target_info loki_mbus_dram_info; +void loki_setup_cpu_mbus(void); +void loki_setup_dev_boot_win(u32 base, u32 size); + +void loki_ge0_init(struct mv643xx_eth_platform_data *eth_data); +void loki_ge1_init(struct mv643xx_eth_platform_data *eth_data); +void loki_sas_init(void); +void loki_uart0_init(void); +void loki_uart1_init(void); + +extern struct sys_timer loki_timer; + + +#endif diff --git a/arch/arm/mach-loki/irq.c b/arch/arm/mach-loki/irq.c new file mode 100644 index 00000000000..d839af91fe0 --- /dev/null +++ b/arch/arm/mach-loki/irq.c @@ -0,0 +1,21 @@ +/* + * arch/arm/mach-loki/irq.c + * + * Marvell Loki (88RC8480) IRQ handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <asm/io.h> +#include <asm/plat-orion/irq.h> +#include "common.h" + +void __init loki_init_irq(void) +{ + orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_OFF)); +} diff --git a/arch/arm/mach-loki/lb88rc8480-setup.c b/arch/arm/mach-loki/lb88rc8480-setup.c new file mode 100644 index 00000000000..d1b9e6e6253 --- /dev/null +++ b/arch/arm/mach-loki/lb88rc8480-setup.c @@ -0,0 +1,100 @@ +/* + * arch/arm/mach-loki/lb88rc8480-setup.c + * + * Marvell LB88RC8480 Development Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/irq.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/nand.h> +#include <linux/timer.h> +#include <linux/ata_platform.h> +#include <linux/mv643xx_eth.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/arch/loki.h> +#include "common.h" + +#define LB88RC8480_FLASH_BOOT_CS_BASE 0xf8000000 +#define LB88RC8480_FLASH_BOOT_CS_SIZE SZ_128M + +#define LB88RC8480_NOR_BOOT_BASE 0xff000000 +#define LB88RC8480_NOR_BOOT_SIZE SZ_16M + +static struct mtd_partition lb88rc8480_boot_flash_parts[] = { + { + .name = "kernel", + .offset = 0, + .size = SZ_2M, + }, { + .name = "root-fs", + .offset = SZ_2M, + .size = (SZ_8M + SZ_4M + SZ_1M), + }, { + .name = "u-boot", + .offset = (SZ_8M + SZ_4M + SZ_2M + SZ_1M), + .size = SZ_1M, + }, +}; + +static struct physmap_flash_data lb88rc8480_boot_flash_data = { + .parts = lb88rc8480_boot_flash_parts, + .nr_parts = ARRAY_SIZE(lb88rc8480_boot_flash_parts), + .width = 1, /* 8 bit bus width */ +}; + +static struct resource lb88rc8480_boot_flash_resource = { + .flags = IORESOURCE_MEM, + .start = LB88RC8480_NOR_BOOT_BASE, + .end = LB88RC8480_NOR_BOOT_BASE + LB88RC8480_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device lb88rc8480_boot_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &lb88rc8480_boot_flash_data, + }, + .num_resources = 1, + .resource = &lb88rc8480_boot_flash_resource, +}; + +static struct mv643xx_eth_platform_data lb88rc8480_ge0_data = { + .phy_addr = 1, + .mac_addr = { 0x00, 0x50, 0x43, 0x11, 0x22, 0x33 }, +}; + +static void __init lb88rc8480_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + loki_init(); + + loki_ge0_init(&lb88rc8480_ge0_data); + loki_sas_init(); + loki_uart0_init(); + loki_uart1_init(); + + loki_setup_dev_boot_win(LB88RC8480_FLASH_BOOT_CS_BASE, + LB88RC8480_FLASH_BOOT_CS_SIZE); + platform_device_register(&lb88rc8480_boot_flash); +} + +MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board") + /* Maintainer: Ke Wei <kewei@marvell.com> */ + .phys_io = LOKI_REGS_PHYS_BASE, + .io_pg_offst = ((LOKI_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = lb88rc8480_init, + .map_io = loki_map_io, + .init_irq = loki_init_irq, + .timer = &loki_timer, +MACHINE_END diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig new file mode 100644 index 00000000000..d83cb86837d --- /dev/null +++ b/arch/arm/mach-mv78xx0/Kconfig @@ -0,0 +1,13 @@ +if ARCH_MV78XX0 + +menu "Marvell MV78xx0 Implementations" + +config MACH_DB78X00_BP + bool "Marvell DB-78x00-BP Development Board" + help + Say 'Y' here if you want your kernel to support the + Marvell DB-78x00-BP Development Board. + +endmenu + +endif diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile new file mode 100644 index 00000000000..ec16c05c3b1 --- /dev/null +++ b/arch/arm/mach-mv78xx0/Makefile @@ -0,0 +1,2 @@ +obj-y += common.o addr-map.o irq.o pcie.o +obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o diff --git a/arch/arm/mach-mv78xx0/Makefile.boot b/arch/arm/mach-mv78xx0/Makefile.boot new file mode 100644 index 00000000000..67039c3e0c4 --- /dev/null +++ b/arch/arm/mach-mv78xx0/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c new file mode 100644 index 00000000000..4004b672a2e --- /dev/null +++ b/arch/arm/mach-mv78xx0/addr-map.c @@ -0,0 +1,156 @@ +/* + * arch/arm/mach-mv78xx0/addr-map.c + * + * Address map functions for Marvell MV78xx0 SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mbus.h> +#include <asm/io.h> +#include "common.h" + +/* + * Generic Address Decode Windows bit settings + */ +#define TARGET_DDR 0 +#define TARGET_DEV_BUS 1 +#define TARGET_PCIE0 4 +#define TARGET_PCIE1 8 +#define TARGET_PCIE(i) ((i) ? TARGET_PCIE1 : TARGET_PCIE0) +#define ATTR_DEV_SPI_ROM 0x1f +#define ATTR_DEV_BOOT 0x2f +#define ATTR_DEV_CS3 0x37 +#define ATTR_DEV_CS2 0x3b +#define ATTR_DEV_CS1 0x3d +#define ATTR_DEV_CS0 0x3e +#define ATTR_PCIE_IO(l) (0xf0 & ~(0x10 << (l))) +#define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l))) + +/* + * Helpers to get DDR bank info + */ +#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) +#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) + +/* + * CPU Address Decode Windows registers + */ +#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) +#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4)) +#define WIN_CTRL_OFF 0x0000 +#define WIN_BASE_OFF 0x0004 +#define WIN_REMAP_LO_OFF 0x0008 +#define WIN_REMAP_HI_OFF 0x000c + + +struct mbus_dram_target_info mv78xx0_mbus_dram_info; + +static void __init __iomem *win_cfg_base(int win) +{ + /* + * Find the control register base address for this window. + * + * BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's) + * MBUS bridge depending on which CPU core we're running on, + * so we don't need to take that into account here. + */ + + return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win)); +} + +static int __init cpu_win_can_remap(int win) +{ + if (win < 8) + return 1; + + return 0; +} + +static void __init setup_cpu_win(int win, u32 base, u32 size, + u8 target, u8 attr, int remap) +{ + void __iomem *addr = win_cfg_base(win); + u32 ctrl; + + base &= 0xffff0000; + ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; + + writel(base, addr + WIN_BASE_OFF); + writel(ctrl, addr + WIN_CTRL_OFF); + if (cpu_win_can_remap(win)) { + if (remap < 0) + remap = base; + + writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF); + writel(0, addr + WIN_REMAP_HI_OFF); + } +} + +void __init mv78xx0_setup_cpu_mbus(void) +{ + void __iomem *addr; + int i; + int cs; + + /* + * First, disable and clear windows. + */ + for (i = 0; i < 14; i++) { + addr = win_cfg_base(i); + + writel(0, addr + WIN_BASE_OFF); + writel(0, addr + WIN_CTRL_OFF); + if (cpu_win_can_remap(i)) { + writel(0, addr + WIN_REMAP_LO_OFF); + writel(0, addr + WIN_REMAP_HI_OFF); + } + } + + /* + * Setup MBUS dram target info. + */ + mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + + if (mv78xx0_core_index() == 0) + addr = (void __iomem *)DDR_WINDOW_CPU0_BASE; + else + addr = (void __iomem *)DDR_WINDOW_CPU1_BASE; + + for (i = 0, cs = 0; i < 4; i++) { + u32 base = readl(addr + DDR_BASE_CS_OFF(i)); + u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); + + /* + * Chip select enabled? + */ + if (size & 1) { + struct mbus_dram_window *w; + + w = &mv78xx0_mbus_dram_info.cs[cs++]; + w->cs_index = i; + w->mbus_attr = 0xf & ~(1 << i); + w->base = base & 0xffff0000; + w->size = (size | 0x0000ffff) + 1; + } + } + mv78xx0_mbus_dram_info.num_cs = cs; +} + +void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, + int maj, int min) +{ + setup_cpu_win(window, base, size, TARGET_PCIE(maj), + ATTR_PCIE_IO(min), -1); +} + +void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, + int maj, int min) +{ + setup_cpu_win(window, base, size, TARGET_PCIE(maj), + ATTR_PCIE_MEM(min), -1); +} diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c new file mode 100644 index 00000000000..d27b83b7bf6 --- /dev/null +++ b/arch/arm/mach-mv78xx0/common.c @@ -0,0 +1,754 @@ +/* + * arch/arm/mach-mv78xx0/common.c + * + * Core functions for Marvell MV78xx0 SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/mbus.h> +#include <linux/mv643xx_eth.h> +#include <linux/ata_platform.h> +#include <asm/mach/map.h> +#include <asm/mach/time.h> +#include <asm/arch/mv78xx0.h> +#include <asm/plat-orion/cache-feroceon-l2.h> +#include <asm/plat-orion/ehci-orion.h> +#include <asm/plat-orion/orion_nand.h> +#include <asm/plat-orion/time.h> +#include "common.h" + + +/***************************************************************************** + * Common bits + ****************************************************************************/ +int mv78xx0_core_index(void) +{ + u32 extra; + + /* + * Read Extra Features register. + */ + __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra)); + + return !!(extra & 0x00004000); +} + +static int get_hclk(void) +{ + int hclk; + + /* + * HCLK tick rate is configured by DEV_D[7:5] pins. + */ + switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) { + case 0: + hclk = 166666667; + break; + case 1: + hclk = 200000000; + break; + case 2: + hclk = 266666667; + break; + case 3: + hclk = 333333333; + break; + case 4: + hclk = 400000000; + break; + default: + panic("unknown HCLK PLL setting: %.8x\n", + readl(SAMPLE_AT_RESET_LOW)); + } + + return hclk; +} + +static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk) +{ + u32 cfg; + + /* + * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1 + * PCLK/L2CLK by bits [19:14]. + */ + if (core_index == 0) { + cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f; + } else { + cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f; + } + + /* + * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK + * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6). + */ + *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1; + + /* + * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK + * ratio (1, 2, 3). + */ + *l2clk = *pclk / (((cfg >> 4) & 3) + 1); +} + +static int get_tclk(void) +{ + int tclk; + + /* + * TCLK tick rate is configured by DEV_A[2:0] strap pins. + */ + switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) { + case 1: + tclk = 166666667; + break; + case 3: + tclk = 200000000; + break; + default: + panic("unknown TCLK PLL setting: %.8x\n", + readl(SAMPLE_AT_RESET_HIGH)); + } + + return tclk; +} + + +/***************************************************************************** + * I/O Address Mapping + ****************************************************************************/ +static struct map_desc mv78xx0_io_desc[] __initdata = { + { + .virtual = MV78XX0_CORE_REGS_VIRT_BASE, + .pfn = 0, + .length = MV78XX0_CORE_REGS_SIZE, + .type = MT_DEVICE, + }, { + .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), + .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), + .length = MV78XX0_PCIE_IO_SIZE * 8, + .type = MT_DEVICE, + }, { + .virtual = MV78XX0_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), + .length = MV78XX0_REGS_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init mv78xx0_map_io(void) +{ + unsigned long phys; + + /* + * Map the right set of per-core registers depending on + * which core we are running on. + */ + if (mv78xx0_core_index() == 0) { + phys = MV78XX0_CORE0_REGS_PHYS_BASE; + } else { + phys = MV78XX0_CORE1_REGS_PHYS_BASE; + } + mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys); + + iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc)); +} + + +/***************************************************************************** + * EHCI + ****************************************************************************/ +static struct orion_ehci_data mv78xx0_ehci_data = { + .dram = &mv78xx0_mbus_dram_info, +}; + +static u64 ehci_dmamask = 0xffffffffUL; + + +/***************************************************************************** + * EHCI0 + ****************************************************************************/ +static struct resource mv78xx0_ehci0_resources[] = { + { + .start = USB0_PHYS_BASE, + .end = USB0_PHYS_BASE + 0x0fff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_MV78XX0_USB_0, + .end = IRQ_MV78XX0_USB_0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mv78xx0_ehci0 = { + .name = "orion-ehci", + .id = 0, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &mv78xx0_ehci_data, + }, + .resource = mv78xx0_ehci0_resources, + .num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources), +}; + +void __init mv78xx0_ehci0_init(void) +{ + platform_device_register(&mv78xx0_ehci0); +} + + +/***************************************************************************** + * EHCI1 + ****************************************************************************/ +static struct resource mv78xx0_ehci1_resources[] = { + { + .start = USB1_PHYS_BASE, + .end = USB1_PHYS_BASE + 0x0fff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_MV78XX0_USB_1, + .end = IRQ_MV78XX0_USB_1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mv78xx0_ehci1 = { + .name = "orion-ehci", + .id = 1, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &mv78xx0_ehci_data, + }, + .resource = mv78xx0_ehci1_resources, + .num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources), +}; + +void __init mv78xx0_ehci1_init(void) +{ + platform_device_register(&mv78xx0_ehci1); +} + + +/***************************************************************************** + * EHCI2 + ****************************************************************************/ +static struct resource mv78xx0_ehci2_resources[] = { + { + .start = USB2_PHYS_BASE, + .end = USB2_PHYS_BASE + 0x0fff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_MV78XX0_USB_2, + .end = IRQ_MV78XX0_USB_2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mv78xx0_ehci2 = { + .name = "orion-ehci", + .id = 2, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &mv78xx0_ehci_data, + }, + .resource = mv78xx0_ehci2_resources, + .num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources), +}; + +void __init mv78xx0_ehci2_init(void) +{ + platform_device_register(&mv78xx0_ehci2); +} + + +/***************************************************************************** + * GE00 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = { + .t_clk = 0, + .dram = &mv78xx0_mbus_dram_info, +}; + +static struct resource mv78xx0_ge00_shared_resources[] = { + { + .name = "ge00 base", + .start = GE00_PHYS_BASE + 0x2000, + .end = GE00_PHYS_BASE + 0x3fff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mv78xx0_ge00_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 0, + .dev = { + .platform_data = &mv78xx0_ge00_shared_data, + }, + .num_resources = 1, + .resource = mv78xx0_ge00_shared_resources, +}; + +static struct resource mv78xx0_ge00_resources[] = { + { + .name = "ge00 irq", + .start = IRQ_MV78XX0_GE00_SUM, + .end = IRQ_MV78XX0_GE00_SUM, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mv78xx0_ge00 = { + .name = MV643XX_ETH_NAME, + .id = 0, + .num_resources = 1, + .resource = mv78xx0_ge00_resources, +}; + +void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) +{ + eth_data->shared = &mv78xx0_ge00_shared; + mv78xx0_ge00.dev.platform_data = eth_data; + + platform_device_register(&mv78xx0_ge00_shared); + platform_device_register(&mv78xx0_ge00); +} + + +/***************************************************************************** + * GE01 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = { + .t_clk = 0, + .dram = &mv78xx0_mbus_dram_info, +}; + +static struct resource mv78xx0_ge01_shared_resources[] = { + { + .name = "ge01 base", + .start = GE01_PHYS_BASE + 0x2000, + .end = GE01_PHYS_BASE + 0x3fff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mv78xx0_ge01_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 1, + .dev = { + .platform_data = &mv78xx0_ge01_shared_data, + }, + .num_resources = 1, + .resource = mv78xx0_ge01_shared_resources, +}; + +static struct resource mv78xx0_ge01_resources[] = { + { + .name = "ge01 irq", + .start = IRQ_MV78XX0_GE01_SUM, + .end = IRQ_MV78XX0_GE01_SUM, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mv78xx0_ge01 = { + .name = MV643XX_ETH_NAME, + .id = 1, + .num_resources = 1, + .resource = mv78xx0_ge01_resources, +}; + +void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) +{ + eth_data->shared = &mv78xx0_ge01_shared; + eth_data->shared_smi = &mv78xx0_ge00_shared; + mv78xx0_ge01.dev.platform_data = eth_data; + + platform_device_register(&mv78xx0_ge01_shared); + platform_device_register(&mv78xx0_ge01); +} + + +/***************************************************************************** + * GE10 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = { + .t_clk = 0, + .dram = &mv78xx0_mbus_dram_info, +}; + +static struct resource mv78xx0_ge10_shared_resources[] = { + { + .name = "ge10 base", + .start = GE10_PHYS_BASE + 0x2000, + .end = GE10_PHYS_BASE + 0x3fff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mv78xx0_ge10_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 2, + .dev = { + .platform_data = &mv78xx0_ge10_shared_data, + }, + .num_resources = 1, + .resource = mv78xx0_ge10_shared_resources, +}; + +static struct resource mv78xx0_ge10_resources[] = { + { + .name = "ge10 irq", + .start = IRQ_MV78XX0_GE10_SUM, + .end = IRQ_MV78XX0_GE10_SUM, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mv78xx0_ge10 = { + .name = MV643XX_ETH_NAME, + .id = 2, + .num_resources = 1, + .resource = mv78xx0_ge10_resources, +}; + +void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) +{ + eth_data->shared = &mv78xx0_ge10_shared; + eth_data->shared_smi = &mv78xx0_ge00_shared; + mv78xx0_ge10.dev.platform_data = eth_data; + + platform_device_register(&mv78xx0_ge10_shared); + platform_device_register(&mv78xx0_ge10); +} + + +/***************************************************************************** + * GE11 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = { + .t_clk = 0, + .dram = &mv78xx0_mbus_dram_info, +}; + +static struct resource mv78xx0_ge11_shared_resources[] = { + { + .name = "ge11 base", + .start = GE11_PHYS_BASE + 0x2000, + .end = GE11_PHYS_BASE + 0x3fff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mv78xx0_ge11_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 3, + .dev = { + .platform_data = &mv78xx0_ge11_shared_data, + }, + .num_resources = 1, + .resource = mv78xx0_ge11_shared_resources, +}; + +static struct resource mv78xx0_ge11_resources[] = { + { + .name = "ge11 irq", + .start = IRQ_MV78XX0_GE11_SUM, + .end = IRQ_MV78XX0_GE11_SUM, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mv78xx0_ge11 = { + .name = MV643XX_ETH_NAME, + .id = 3, + .num_resources = 1, + .resource = mv78xx0_ge11_resources, +}; + +void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) +{ + eth_data->shared = &mv78xx0_ge11_shared; + eth_data->shared_smi = &mv78xx0_ge00_shared; + mv78xx0_ge11.dev.platform_data = eth_data; + + platform_device_register(&mv78xx0_ge11_shared); + platform_device_register(&mv78xx0_ge11); +} + + +/***************************************************************************** + * SATA + ****************************************************************************/ +static struct resource mv78xx0_sata_resources[] = { + { + .name = "sata base", + .start = SATA_PHYS_BASE, + .end = SATA_PHYS_BASE + 0x5000 - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "sata irq", + .start = IRQ_MV78XX0_SATA, + .end = IRQ_MV78XX0_SATA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mv78xx0_sata = { + .name = "sata_mv", + .id = 0, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(mv78xx0_sata_resources), + .resource = mv78xx0_sata_resources, +}; + +void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) +{ + sata_data->dram = &mv78xx0_mbus_dram_info; + mv78xx0_sata.dev.platform_data = sata_data; + platform_device_register(&mv78xx0_sata); +} + + +/***************************************************************************** + * UART0 + ****************************************************************************/ +static struct plat_serial8250_port mv78xx0_uart0_data[] = { + { + .mapbase = UART0_PHYS_BASE, + .membase = (char *)UART0_VIRT_BASE, + .irq = IRQ_MV78XX0_UART_0, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 0, + }, { + }, +}; + +static struct resource mv78xx0_uart0_resources[] = { + { + .start = UART0_PHYS_BASE, + .end = UART0_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_MV78XX0_UART_0, + .end = IRQ_MV78XX0_UART_0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mv78xx0_uart0 = { + .name = "serial8250", + .id = 0, + .dev = { + .platform_data = mv78xx0_uart0_data, + }, + .resource = mv78xx0_uart0_resources, + .num_resources = ARRAY_SIZE(mv78xx0_uart0_resources), +}; + +void __init mv78xx0_uart0_init(void) +{ + platform_device_register(&mv78xx0_uart0); +} + + +/***************************************************************************** + * UART1 + ****************************************************************************/ +static struct plat_serial8250_port mv78xx0_uart1_data[] = { + { + .mapbase = UART1_PHYS_BASE, + .membase = (char *)UART1_VIRT_BASE, + .irq = IRQ_MV78XX0_UART_1, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 0, + }, { + }, +}; + +static struct resource mv78xx0_uart1_resources[] = { + { + .start = UART1_PHYS_BASE, + .end = UART1_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_MV78XX0_UART_1, + .end = IRQ_MV78XX0_UART_1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mv78xx0_uart1 = { + .name = "serial8250", + .id = 1, + .dev = { + .platform_data = mv78xx0_uart1_data, + }, + .resource = mv78xx0_uart1_resources, + .num_resources = ARRAY_SIZE(mv78xx0_uart1_resources), +}; + +void __init mv78xx0_uart1_init(void) +{ + platform_device_register(&mv78xx0_uart1); +} + + +/***************************************************************************** + * UART2 + ****************************************************************************/ +static struct plat_serial8250_port mv78xx0_uart2_data[] = { + { + .mapbase = UART2_PHYS_BASE, + .membase = (char *)UART2_VIRT_BASE, + .irq = IRQ_MV78XX0_UART_2, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 0, + }, { + }, +}; + +static struct resource mv78xx0_uart2_resources[] = { + { + .start = UART2_PHYS_BASE, + .end = UART2_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_MV78XX0_UART_2, + .end = IRQ_MV78XX0_UART_2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mv78xx0_uart2 = { + .name = "serial8250", + .id = 2, + .dev = { + .platform_data = mv78xx0_uart2_data, + }, + .resource = mv78xx0_uart2_resources, + .num_resources = ARRAY_SIZE(mv78xx0_uart2_resources), +}; + +void __init mv78xx0_uart2_init(void) +{ + platform_device_register(&mv78xx0_uart2); +} + + +/***************************************************************************** + * UART3 + ****************************************************************************/ +static struct plat_serial8250_port mv78xx0_uart3_data[] = { + { + .mapbase = UART3_PHYS_BASE, + .membase = (char *)UART3_VIRT_BASE, + .irq = IRQ_MV78XX0_UART_3, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 0, + }, { + }, +}; + +static struct resource mv78xx0_uart3_resources[] = { + { + .start = UART3_PHYS_BASE, + .end = UART3_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_MV78XX0_UART_3, + .end = IRQ_MV78XX0_UART_3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device mv78xx0_uart3 = { + .name = "serial8250", + .id = 3, + .dev = { + .platform_data = mv78xx0_uart3_data, + }, + .resource = mv78xx0_uart3_resources, + .num_resources = ARRAY_SIZE(mv78xx0_uart3_resources), +}; + +void __init mv78xx0_uart3_init(void) +{ + platform_device_register(&mv78xx0_uart3); +} + + +/***************************************************************************** + * Time handling + ****************************************************************************/ +static void mv78xx0_timer_init(void) +{ + orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk()); +} + +struct sys_timer mv78xx0_timer = { + .init = mv78xx0_timer_init, +}; + + +/***************************************************************************** + * General + ****************************************************************************/ +static int __init is_l2_writethrough(void) +{ + return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH); +} + +void __init mv78xx0_init(void) +{ + int core_index; + int hclk; + int pclk; + int l2clk; + int tclk; + + core_index = mv78xx0_core_index(); + hclk = get_hclk(); + get_pclk_l2clk(hclk, core_index, &pclk, &l2clk); + tclk = get_tclk(); + + printk(KERN_INFO "MV78xx0 core #%d, ", core_index); + printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000); + printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000); + printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); + printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000); + + mv78xx0_setup_cpu_mbus(); + +#ifdef CONFIG_CACHE_FEROCEON_L2 + feroceon_l2_init(is_l2_writethrough()); +#endif + + mv78xx0_ge00_shared_data.t_clk = tclk; + mv78xx0_ge01_shared_data.t_clk = tclk; + mv78xx0_ge10_shared_data.t_clk = tclk; + mv78xx0_ge11_shared_data.t_clk = tclk; + mv78xx0_uart0_data[0].uartclk = tclk; + mv78xx0_uart1_data[0].uartclk = tclk; + mv78xx0_uart2_data[0].uartclk = tclk; + mv78xx0_uart3_data[0].uartclk = tclk; +} diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h new file mode 100644 index 00000000000..78af5de319d --- /dev/null +++ b/arch/arm/mach-mv78xx0/common.h @@ -0,0 +1,49 @@ +/* + * arch/arm/mach-mv78xx0/common.h + * + * Core functions for Marvell MV78xx0 SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ARCH_MV78XX0_COMMON_H +#define __ARCH_MV78XX0_COMMON_H + +struct mv643xx_eth_platform_data; +struct mv_sata_platform_data; + +/* + * Basic MV78xx0 init functions used early by machine-setup. + */ +int mv78xx0_core_index(void); +void mv78xx0_map_io(void); +void mv78xx0_init(void); +void mv78xx0_init_irq(void); + +extern struct mbus_dram_target_info mv78xx0_mbus_dram_info; +void mv78xx0_setup_cpu_mbus(void); +void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, + int maj, int min); +void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, + int maj, int min); + +void mv78xx0_ehci0_init(void); +void mv78xx0_ehci1_init(void); +void mv78xx0_ehci2_init(void); +void mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data); +void mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data); +void mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data); +void mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data); +void mv78xx0_pcie_init(int init_port0, int init_port1); +void mv78xx0_sata_init(struct mv_sata_platform_data *sata_data); +void mv78xx0_uart0_init(void); +void mv78xx0_uart1_init(void); +void mv78xx0_uart2_init(void); +void mv78xx0_uart3_init(void); + +extern struct sys_timer mv78xx0_timer; + + +#endif diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c new file mode 100644 index 00000000000..0c93d19193d --- /dev/null +++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c @@ -0,0 +1,94 @@ +/* + * arch/arm/mach-mv78xx0/db78x00-bp-setup.c + * + * Marvell DB-78x00-BP Development Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/ata_platform.h> +#include <linux/mv643xx_eth.h> +#include <asm/arch/mv78xx0.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include "common.h" + +static struct mv643xx_eth_platform_data db78x00_ge00_data = { + .phy_addr = 8, +}; + +static struct mv643xx_eth_platform_data db78x00_ge01_data = { + .phy_addr = 9, +}; + +static struct mv643xx_eth_platform_data db78x00_ge10_data = { + .phy_addr = -1, +}; + +static struct mv643xx_eth_platform_data db78x00_ge11_data = { + .phy_addr = -1, +}; + +static struct mv_sata_platform_data db78x00_sata_data = { + .n_ports = 2, +}; + +static void __init db78x00_init(void) +{ + /* + * Basic MV78xx0 setup. Needs to be called early. + */ + mv78xx0_init(); + + /* + * Partition on-chip peripherals between the two CPU cores. + */ + if (mv78xx0_core_index() == 0) { + mv78xx0_ehci0_init(); + mv78xx0_ehci1_init(); + mv78xx0_ehci2_init(); + mv78xx0_ge00_init(&db78x00_ge00_data); + mv78xx0_ge01_init(&db78x00_ge01_data); + mv78xx0_ge10_init(&db78x00_ge10_data); + mv78xx0_ge11_init(&db78x00_ge11_data); + mv78xx0_sata_init(&db78x00_sata_data); + mv78xx0_uart0_init(); + mv78xx0_uart2_init(); + } else { + mv78xx0_uart1_init(); + mv78xx0_uart3_init(); + } +} + +static int __init db78x00_pci_init(void) +{ + if (machine_is_db78x00_bp()) { + /* + * Assign the x16 PCIe slot on the board to CPU core + * #0, and let CPU core #1 have the four x1 slots. + */ + if (mv78xx0_core_index() == 0) + mv78xx0_pcie_init(0, 1); + else + mv78xx0_pcie_init(1, 0); + } + + return 0; +} +subsys_initcall(db78x00_pci_init); + +MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board") + /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ + .phys_io = MV78XX0_REGS_PHYS_BASE, + .io_pg_offst = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = db78x00_init, + .map_io = mv78xx0_map_io, + .init_irq = mv78xx0_init_irq, + .timer = &mv78xx0_timer, +MACHINE_END diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c new file mode 100644 index 00000000000..60f4ee4d453 --- /dev/null +++ b/arch/arm/mach-mv78xx0/irq.c @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-mv78xx0/irq.c + * + * MV78xx0 IRQ handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/pci.h> +#include <asm/arch/mv78xx0.h> +#include <asm/plat-orion/irq.h> +#include "common.h" + +void __init mv78xx0_init_irq(void) +{ + orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); + orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); +} diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c new file mode 100644 index 00000000000..b78e1443159 --- /dev/null +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -0,0 +1,312 @@ +/* + * arch/arm/mach-mv78xx0/pcie.c + * + * PCIe functions for Marvell MV78xx0 SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/mbus.h> +#include <asm/mach/pci.h> +#include <asm/plat-orion/pcie.h> +#include "common.h" + +struct pcie_port { + u8 maj; + u8 min; + u8 root_bus_nr; + void __iomem *base; + spinlock_t conf_lock; + char io_space_name[16]; + char mem_space_name[16]; + struct resource res[2]; +}; + +static struct pcie_port pcie_port[8]; +static int num_pcie_ports; +static struct resource pcie_io_space; +static struct resource pcie_mem_space; + + +static void __init mv78xx0_pcie_preinit(void) +{ + int i; + u32 size_each; + u32 start; + int win; + + pcie_io_space.name = "PCIe I/O Space"; + pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0); + pcie_io_space.end = + MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1; + pcie_io_space.flags = IORESOURCE_IO; + if (request_resource(&iomem_resource, &pcie_io_space)) + panic("can't allocate PCIe I/O space"); + + pcie_mem_space.name = "PCIe MEM Space"; + pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE; + pcie_mem_space.end = + MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1; + pcie_mem_space.flags = IORESOURCE_MEM; + if (request_resource(&iomem_resource, &pcie_mem_space)) + panic("can't allocate PCIe MEM space"); + + for (i = 0; i < num_pcie_ports; i++) { + struct pcie_port *pp = pcie_port + i; + + snprintf(pp->io_space_name, sizeof(pp->io_space_name), + "PCIe %d.%d I/O", pp->maj, pp->min); + pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; + pp->res[0].name = pp->io_space_name; + pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i); + pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1; + pp->res[0].flags = IORESOURCE_IO; + + snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), + "PCIe %d.%d MEM", pp->maj, pp->min); + pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; + pp->res[1].name = pp->mem_space_name; + pp->res[1].flags = IORESOURCE_MEM; + } + + switch (num_pcie_ports) { + case 0: + size_each = 0; + break; + + case 1: + size_each = 0x30000000; + break; + + case 2 ... 3: + size_each = 0x10000000; + break; + + case 4 ... 6: + size_each = 0x08000000; + break; + + case 7: + size_each = 0x04000000; + break; + + default: + panic("invalid number of PCIe ports"); + } + + start = MV78XX0_PCIE_MEM_PHYS_BASE; + for (i = 0; i < num_pcie_ports; i++) { + struct pcie_port *pp = pcie_port + i; + + pp->res[1].start = start; + pp->res[1].end = start + size_each - 1; + start += size_each; + } + + for (i = 0; i < num_pcie_ports; i++) { + struct pcie_port *pp = pcie_port + i; + + if (request_resource(&pcie_io_space, &pp->res[0])) + panic("can't allocate PCIe I/O sub-space"); + + if (request_resource(&pcie_mem_space, &pp->res[1])) + panic("can't allocate PCIe MEM sub-space"); + } + + win = 0; + for (i = 0; i < num_pcie_ports; i++) { + struct pcie_port *pp = pcie_port + i; + + mv78xx0_setup_pcie_io_win(win++, pp->res[0].start, + pp->res[0].end - pp->res[0].start + 1, + pp->maj, pp->min); + + mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start, + pp->res[1].end - pp->res[1].start + 1, + pp->maj, pp->min); + } +} + +static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) +{ + struct pcie_port *pp; + + if (nr >= num_pcie_ports) + return 0; + + pp = &pcie_port[nr]; + pp->root_bus_nr = sys->busnr; + + /* + * Generic PCIe unit setup. + */ + orion_pcie_set_local_bus_nr(pp->base, sys->busnr); + orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info); + + sys->resource[0] = &pp->res[0]; + sys->resource[1] = &pp->res[1]; + sys->resource[2] = NULL; + + return 1; +} + +static struct pcie_port *bus_to_port(int bus) +{ + int i; + + for (i = num_pcie_ports - 1; i >= 0; i--) { + int rbus = pcie_port[i].root_bus_nr; + if (rbus != -1 && rbus <= bus) + break; + } + + return i >= 0 ? pcie_port + i : NULL; +} + +static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) +{ + /* + * Don't go out when trying to access nonexisting devices + * on the local bus. + */ + if (bus == pp->root_bus_nr && dev > 1) + return 0; + + return 1; +} + +static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) +{ + struct pcie_port *pp = bus_to_port(bus->number); + unsigned long flags; + int ret; + + if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + spin_lock_irqsave(&pp->conf_lock, flags); + ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val); + spin_unlock_irqrestore(&pp->conf_lock, flags); + + return ret; +} + +static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 val) +{ + struct pcie_port *pp = bus_to_port(bus->number); + unsigned long flags; + int ret; + + if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + spin_lock_irqsave(&pp->conf_lock, flags); + ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val); + spin_unlock_irqrestore(&pp->conf_lock, flags); + + return ret; +} + +static struct pci_ops pcie_ops = { + .read = pcie_rd_conf, + .write = pcie_wr_conf, +}; + +static void __devinit rc_pci_fixup(struct pci_dev *dev) +{ + /* + * Prevent enumeration of root complex. + */ + if (dev->bus->parent == NULL && dev->devfn == 0) { + int i; + + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { + dev->resource[i].start = 0; + dev->resource[i].end = 0; + dev->resource[i].flags = 0; + } + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); + +static struct pci_bus __init * +mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys) +{ + struct pci_bus *bus; + + if (nr < num_pcie_ports) { + bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); + } else { + bus = NULL; + BUG(); + } + + return bus; +} + +static int __init mv78xx0_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + struct pcie_port *pp = bus_to_port(dev->bus->number); + + return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min; +} + +static struct hw_pci mv78xx0_pci __initdata = { + .nr_controllers = 8, + .preinit = mv78xx0_pcie_preinit, + .swizzle = pci_std_swizzle, + .setup = mv78xx0_pcie_setup, + .scan = mv78xx0_pcie_scan_bus, + .map_irq = mv78xx0_pcie_map_irq, +}; + +static void __init add_pcie_port(int maj, int min, unsigned long base) +{ + printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min); + + if (orion_pcie_link_up((void __iomem *)base)) { + struct pcie_port *pp = &pcie_port[num_pcie_ports++]; + + printk("link up\n"); + + pp->maj = maj; + pp->min = min; + pp->root_bus_nr = -1; + pp->base = (void __iomem *)base; + spin_lock_init(&pp->conf_lock); + memset(pp->res, 0, sizeof(pp->res)); + } else { + printk("link down, ignoring\n"); + } +} + +void __init mv78xx0_pcie_init(int init_port0, int init_port1) +{ + if (init_port0) { + add_pcie_port(0, 0, PCIE00_VIRT_BASE); + if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) { + add_pcie_port(0, 1, PCIE01_VIRT_BASE); + add_pcie_port(0, 2, PCIE02_VIRT_BASE); + add_pcie_port(0, 3, PCIE03_VIRT_BASE); + } + } + + if (init_port1) { + add_pcie_port(1, 0, PCIE10_VIRT_BASE); + if (!orion_pcie_x4_mode((void __iomem *)PCIE10_VIRT_BASE)) { + add_pcie_port(1, 1, PCIE11_VIRT_BASE); + add_pcie_port(1, 2, PCIE12_VIRT_BASE); + add_pcie_port(1, 3, PCIE13_VIRT_BASE); + } + } + + pci_common_init(&mv78xx0_pci); +} diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 93debf33615..f8b91ea3eb7 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -44,6 +44,36 @@ config MACH_LINKSTATION_PRO Buffalo Linkstation Pro/Live platform. Both v1 and v2 devices are supported. +config MACH_TS409 + bool "QNAP TS-409" + help + Say 'Y' here if you want your kernel to support the + QNAP TS-409 platform. + +config MACH_WRT350N_V2 + bool "Linksys WRT350N v2" + help + Say 'Y' here if you want your kernel to support the + Linksys WRT350N v2 platform. + +config MACH_TS78XX + bool "Technologic Systems TS-78xx" + help + Say 'Y' here if you want your kernel to support the + Technologic Systems TS-78xx platform. + +config MACH_MV2120 + bool "HP Media Vault mv2120" + help + Say 'Y' here if you want your kernel to support the + HP Media Vault mv2120 or mv5100. + +config MACH_MSS2 + bool "Maxtor Shared Storage II" + help + Say 'Y' here if you want your kernel to support the + Maxtor Shared Storage II platform. + endmenu endif diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 9301bf55910..65b2fc6a355 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -1,7 +1,12 @@ -obj-y += common.o addr-map.o pci.o gpio.o irq.o +obj-y += common.o addr-map.o pci.o gpio.o irq.o mpp.o obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o obj-$(CONFIG_MACH_DNS323) += dns323-setup.o -obj-$(CONFIG_MACH_TS209) += ts209-setup.o +obj-$(CONFIG_MACH_TS209) += ts209-setup.o tsx09-common.o +obj-$(CONFIG_MACH_TS409) += ts409-setup.o tsx09-common.o +obj-$(CONFIG_MACH_WRT350N_V2) += wrt350n-v2-setup.o +obj-$(CONFIG_MACH_TS78XX) += ts78xx-setup.o +obj-$(CONFIG_MACH_MV2120) += mv2120-setup.o +obj-$(CONFIG_MACH_MSS2) += mss2-setup.o diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index e63fb05dc89..6f0dbda6c44 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -70,6 +70,7 @@ struct mbus_dram_target_info orion5x_mbus_dram_info; +static int __initdata win_alloc_count; static int __init orion5x_cpu_win_can_remap(int win) { @@ -87,16 +88,22 @@ static int __init orion5x_cpu_win_can_remap(int win) static void __init setup_cpu_win(int win, u32 base, u32 size, u8 target, u8 attr, int remap) { - orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000); - orion5x_write(CPU_WIN_CTRL(win), - ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1); + if (win >= 8) { + printk(KERN_ERR "setup_cpu_win: trying to allocate " + "window %d\n", win); + return; + } + + writel(base & 0xffff0000, CPU_WIN_BASE(win)); + writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1, + CPU_WIN_CTRL(win)); if (orion5x_cpu_win_can_remap(win)) { if (remap < 0) remap = base; - orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); - orion5x_write(CPU_WIN_REMAP_HI(win), 0); + writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win)); + writel(0, CPU_WIN_REMAP_HI(win)); } } @@ -109,11 +116,11 @@ void __init orion5x_setup_cpu_mbus_bridge(void) * First, disable and clear windows. */ for (i = 0; i < 8; i++) { - orion5x_write(CPU_WIN_BASE(i), 0); - orion5x_write(CPU_WIN_CTRL(i), 0); + writel(0, CPU_WIN_BASE(i)); + writel(0, CPU_WIN_CTRL(i)); if (orion5x_cpu_win_can_remap(i)) { - orion5x_write(CPU_WIN_REMAP_LO(i), 0); - orion5x_write(CPU_WIN_REMAP_HI(i), 0); + writel(0, CPU_WIN_REMAP_LO(i)); + writel(0, CPU_WIN_REMAP_HI(i)); } } @@ -128,6 +135,7 @@ void __init orion5x_setup_cpu_mbus_bridge(void) TARGET_PCIE, ATTR_PCIE_MEM, -1); setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, TARGET_PCI, ATTR_PCI_MEM, -1); + win_alloc_count = 4; /* * Setup MBUS dram target info. @@ -147,8 +155,8 @@ void __init orion5x_setup_cpu_mbus_bridge(void) w = &orion5x_mbus_dram_info.cs[cs++]; w->cs_index = i; w->mbus_attr = 0xf & ~(1 << i); - w->base = base & 0xff000000; - w->size = (size | 0x00ffffff) + 1; + w->base = base & 0xffff0000; + w->size = (size | 0x0000ffff) + 1; } } orion5x_mbus_dram_info.num_cs = cs; @@ -156,25 +164,30 @@ void __init orion5x_setup_cpu_mbus_bridge(void) void __init orion5x_setup_dev_boot_win(u32 base, u32 size) { - setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); + setup_cpu_win(win_alloc_count++, base, size, + TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); } void __init orion5x_setup_dev0_win(u32 base, u32 size) { - setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1); + setup_cpu_win(win_alloc_count++, base, size, + TARGET_DEV_BUS, ATTR_DEV_CS0, -1); } void __init orion5x_setup_dev1_win(u32 base, u32 size) { - setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1); + setup_cpu_win(win_alloc_count++, base, size, + TARGET_DEV_BUS, ATTR_DEV_CS1, -1); } void __init orion5x_setup_dev2_win(u32 base, u32 size) { - setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); + setup_cpu_win(win_alloc_count++, base, size, + TARGET_DEV_BUS, ATTR_DEV_CS2, -1); } void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) { - setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); + setup_cpu_win(win_alloc_count++, base, size, + TARGET_PCIE, ATTR_PCIE_WA, -1); } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 4f13fd037f0..faf4e321191 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -39,25 +39,22 @@ static struct map_desc orion5x_io_desc[] __initdata = { .virtual = ORION5X_REGS_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), .length = ORION5X_REGS_SIZE, - .type = MT_DEVICE - }, - { + .type = MT_DEVICE, + }, { .virtual = ORION5X_PCIE_IO_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), .length = ORION5X_PCIE_IO_SIZE, - .type = MT_DEVICE - }, - { + .type = MT_DEVICE, + }, { .virtual = ORION5X_PCI_IO_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), .length = ORION5X_PCI_IO_SIZE, - .type = MT_DEVICE - }, - { + .type = MT_DEVICE, + }, { .virtual = ORION5X_PCIE_WA_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), .length = ORION5X_PCIE_WA_SIZE, - .type = MT_DEVICE + .type = MT_DEVICE, }, }; @@ -66,101 +63,32 @@ void __init orion5x_map_io(void) iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); } + /***************************************************************************** - * UART + * EHCI ****************************************************************************/ - -static struct resource orion5x_uart_resources[] = { - { - .start = UART0_PHYS_BASE, - .end = UART0_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_ORION5X_UART0, - .end = IRQ_ORION5X_UART0, - .flags = IORESOURCE_IRQ, - }, - { - .start = UART1_PHYS_BASE, - .end = UART1_PHYS_BASE + 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_ORION5X_UART1, - .end = IRQ_ORION5X_UART1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct plat_serial8250_port orion5x_uart_data[] = { - { - .mapbase = UART0_PHYS_BASE, - .membase = (char *)UART0_VIRT_BASE, - .irq = IRQ_ORION5X_UART0, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = ORION5X_TCLK, - }, - { - .mapbase = UART1_PHYS_BASE, - .membase = (char *)UART1_VIRT_BASE, - .irq = IRQ_ORION5X_UART1, - .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = ORION5X_TCLK, - }, - { }, +static struct orion_ehci_data orion5x_ehci_data = { + .dram = &orion5x_mbus_dram_info, }; -static struct platform_device orion5x_uart = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = orion5x_uart_data, - }, - .resource = orion5x_uart_resources, - .num_resources = ARRAY_SIZE(orion5x_uart_resources), -}; +static u64 ehci_dmamask = 0xffffffffUL; -/******************************************************************************* - * USB Controller - 2 interfaces - ******************************************************************************/ +/***************************************************************************** + * EHCI0 + ****************************************************************************/ static struct resource orion5x_ehci0_resources[] = { { .start = ORION5X_USB0_PHYS_BASE, .end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, - }, - { + }, { .start = IRQ_ORION5X_USB0_CTRL, .end = IRQ_ORION5X_USB0_CTRL, .flags = IORESOURCE_IRQ, }, }; -static struct resource orion5x_ehci1_resources[] = { - { - .start = ORION5X_USB1_PHYS_BASE, - .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_ORION5X_USB1_CTRL, - .end = IRQ_ORION5X_USB1_CTRL, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct orion_ehci_data orion5x_ehci_data = { - .dram = &orion5x_mbus_dram_info, -}; - -static u64 ehci_dmamask = 0xffffffffUL; - static struct platform_device orion5x_ehci0 = { .name = "orion-ehci", .id = 0, @@ -173,6 +101,27 @@ static struct platform_device orion5x_ehci0 = { .num_resources = ARRAY_SIZE(orion5x_ehci0_resources), }; +void __init orion5x_ehci0_init(void) +{ + platform_device_register(&orion5x_ehci0); +} + + +/***************************************************************************** + * EHCI1 + ****************************************************************************/ +static struct resource orion5x_ehci1_resources[] = { + { + .start = ORION5X_USB1_PHYS_BASE, + .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_ORION5X_USB1_CTRL, + .end = IRQ_ORION5X_USB1_CTRL, + .flags = IORESOURCE_IRQ, + }, +}; + static struct platform_device orion5x_ehci1 = { .name = "orion-ehci", .id = 1, @@ -185,11 +134,15 @@ static struct platform_device orion5x_ehci1 = { .num_resources = ARRAY_SIZE(orion5x_ehci1_resources), }; +void __init orion5x_ehci1_init(void) +{ + platform_device_register(&orion5x_ehci1); +} + + /***************************************************************************** - * Gigabit Ethernet port - * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) + * GigE ****************************************************************************/ - struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = { .dram = &orion5x_mbus_dram_info, .t_clk = ORION5X_TCLK, @@ -219,7 +172,7 @@ static struct resource orion5x_eth_resources[] = { .start = IRQ_ORION5X_ETH_SUM, .end = IRQ_ORION5X_ETH_SUM, .flags = IORESOURCE_IRQ, - } + }, }; static struct platform_device orion5x_eth = { @@ -238,11 +191,10 @@ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) platform_device_register(&orion5x_eth); } + /***************************************************************************** - * I2C controller - * (The Orion and Discovery (MV643xx) families share the same I2C controller) + * I2C ****************************************************************************/ - static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { .freq_m = 8, /* assumes 166 MHz TCLK */ .freq_n = 3, @@ -251,16 +203,15 @@ static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { static struct resource orion5x_i2c_resources[] = { { - .name = "i2c base", - .start = I2C_PHYS_BASE, - .end = I2C_PHYS_BASE + 0x20 -1, - .flags = IORESOURCE_MEM, - }, - { - .name = "i2c irq", - .start = IRQ_ORION5X_I2C, - .end = IRQ_ORION5X_I2C, - .flags = IORESOURCE_IRQ, + .name = "i2c base", + .start = I2C_PHYS_BASE, + .end = I2C_PHYS_BASE + 0x1f, + .flags = IORESOURCE_MEM, + }, { + .name = "i2c irq", + .start = IRQ_ORION5X_I2C, + .end = IRQ_ORION5X_I2C, + .flags = IORESOURCE_IRQ, }, }; @@ -270,36 +221,41 @@ static struct platform_device orion5x_i2c = { .num_resources = ARRAY_SIZE(orion5x_i2c_resources), .resource = orion5x_i2c_resources, .dev = { - .platform_data = &orion5x_i2c_pdata, + .platform_data = &orion5x_i2c_pdata, }, }; +void __init orion5x_i2c_init(void) +{ + platform_device_register(&orion5x_i2c); +} + + /***************************************************************************** - * Sata port + * SATA ****************************************************************************/ static struct resource orion5x_sata_resources[] = { - { - .name = "sata base", - .start = ORION5X_SATA_PHYS_BASE, - .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1, - .flags = IORESOURCE_MEM, - }, { - .name = "sata irq", - .start = IRQ_ORION5X_SATA, - .end = IRQ_ORION5X_SATA, - .flags = IORESOURCE_IRQ, - }, + .name = "sata base", + .start = ORION5X_SATA_PHYS_BASE, + .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "sata irq", + .start = IRQ_ORION5X_SATA, + .end = IRQ_ORION5X_SATA, + .flags = IORESOURCE_IRQ, + }, }; static struct platform_device orion5x_sata = { - .name = "sata_mv", - .id = 0, + .name = "sata_mv", + .id = 0, .dev = { .coherent_dma_mask = 0xffffffff, }, - .num_resources = ARRAY_SIZE(orion5x_sata_resources), - .resource = orion5x_sata_resources, + .num_resources = ARRAY_SIZE(orion5x_sata_resources), + .resource = orion5x_sata_resources, }; void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) @@ -309,23 +265,111 @@ void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) platform_device_register(&orion5x_sata); } + /***************************************************************************** - * Time handling + * UART0 + ****************************************************************************/ +static struct plat_serial8250_port orion5x_uart0_data[] = { + { + .mapbase = UART0_PHYS_BASE, + .membase = (char *)UART0_VIRT_BASE, + .irq = IRQ_ORION5X_UART0, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = ORION5X_TCLK, + }, { + }, +}; + +static struct resource orion5x_uart0_resources[] = { + { + .start = UART0_PHYS_BASE, + .end = UART0_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_ORION5X_UART0, + .end = IRQ_ORION5X_UART0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device orion5x_uart0 = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = orion5x_uart0_data, + }, + .resource = orion5x_uart0_resources, + .num_resources = ARRAY_SIZE(orion5x_uart0_resources), +}; + +void __init orion5x_uart0_init(void) +{ + platform_device_register(&orion5x_uart0); +} + + +/***************************************************************************** + * UART1 ****************************************************************************/ +static struct plat_serial8250_port orion5x_uart1_data[] = { + { + .mapbase = UART1_PHYS_BASE, + .membase = (char *)UART1_VIRT_BASE, + .irq = IRQ_ORION5X_UART1, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = ORION5X_TCLK, + }, { + }, +}; + +static struct resource orion5x_uart1_resources[] = { + { + .start = UART1_PHYS_BASE, + .end = UART1_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_ORION5X_UART1, + .end = IRQ_ORION5X_UART1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device orion5x_uart1 = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev = { + .platform_data = orion5x_uart1_data, + }, + .resource = orion5x_uart1_resources, + .num_resources = ARRAY_SIZE(orion5x_uart1_resources), +}; + +void __init orion5x_uart1_init(void) +{ + platform_device_register(&orion5x_uart1); +} + +/***************************************************************************** + * Time handling + ****************************************************************************/ static void orion5x_timer_init(void) { orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK); } struct sys_timer orion5x_timer = { - .init = orion5x_timer_init, + .init = orion5x_timer_init, }; + /***************************************************************************** * General ****************************************************************************/ - /* * Identify device ID and rev from PCIe configuration header space '0'. */ @@ -350,8 +394,10 @@ static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name) } else if (*dev == MV88F5181_DEV_ID) { if (*rev == MV88F5181_REV_B1) { *dev_name = "MV88F5181-Rev-B1"; + } else if (*rev == MV88F5181L_REV_A1) { + *dev_name = "MV88F5181L-Rev-A1"; } else { - *dev_name = "MV88F5181-Rev-Unsupported"; + *dev_name = "MV88F5181(L)-Rev-Unsupported"; } } else { *dev_name = "Device-Unknown"; @@ -370,15 +416,6 @@ void __init orion5x_init(void) * Setup Orion address map */ orion5x_setup_cpu_mbus_bridge(); - - /* - * Register devices. - */ - platform_device_register(&orion5x_uart); - platform_device_register(&orion5x_ehci0); - if (dev == MV88F5182_DEV_ID) - platform_device_register(&orion5x_ehci1); - platform_device_register(&orion5x_i2c); } /* diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index bd0f05de6e1..f72cf0e7754 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -1,10 +1,12 @@ #ifndef __ARCH_ORION5X_COMMON_H #define __ARCH_ORION5X_COMMON_H +struct mv643xx_eth_platform_data; +struct mv_sata_platform_data; + /* * Basic Orion init functions used early by machine-setup. */ - void orion5x_map_io(void); void orion5x_init_irq(void); void orion5x_init(void); @@ -23,15 +25,22 @@ void orion5x_setup_dev1_win(u32 base, u32 size); void orion5x_setup_dev2_win(u32 base, u32 size); void orion5x_setup_pcie_wa_win(u32 base, u32 size); +void orion5x_ehci0_init(void); +void orion5x_ehci1_init(void); +void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data); +void orion5x_i2c_init(void); +void orion5x_sata_init(struct mv_sata_platform_data *sata_data); +void orion5x_uart0_init(void); +void orion5x_uart1_init(void); + /* - * Shared code used internally by other Orion core functions. - * (/mach-orion/pci.c) + * PCIe/PCI functions. */ - -struct pci_sys_data; struct pci_bus; +struct pci_sys_data; void orion5x_pcie_id(u32 *dev, u32 *rev); +void orion5x_pci_set_cardbus_mode(void); int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); @@ -40,26 +49,9 @@ int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); * Valid GPIO pins according to MPP setup, used by machine-setup. * (/mach-orion/gpio.c). */ - -void orion5x_gpio_set_valid_pins(u32 pins); +void orion5x_gpio_set_valid(unsigned pin, int valid); void gpio_display(void); /* debug */ -/* - * Pull in Orion Ethernet platform_data, used by machine-setup - */ - -struct mv643xx_eth_platform_data; - -void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data); - -/* - * Orion Sata platform_data, used by machine-setup - */ - -struct mv_sata_platform_data; - -void orion5x_sata_init(struct mv_sata_platform_data *sata_data); - struct machine_desc; struct meminfo; struct tag; diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index 44c64342dac..88405e74e5e 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -27,6 +27,7 @@ #include <asm/arch/orion5x.h> #include <asm/plat-orion/orion_nand.h> #include "common.h" +#include "mpp.h" /***************************************************************************** * DB-88F5281 on board devices @@ -86,7 +87,7 @@ static struct platform_device db88f5281_boot_flash = { .name = "physmap-flash", .id = 0, .dev = { - .platform_data = &db88f5281_boot_flash_data, + .platform_data = &db88f5281_boot_flash_data, }, .num_resources = 1, .resource = &db88f5281_boot_flash_resource, @@ -110,7 +111,7 @@ static struct platform_device db88f5281_nor_flash = { .name = "physmap-flash", .id = 1, .dev = { - .platform_data = &db88f5281_nor_flash_data, + .platform_data = &db88f5281_nor_flash_data, }, .num_resources = 1, .resource = &db88f5281_nor_flash_resource, @@ -125,18 +126,15 @@ static struct mtd_partition db88f5281_nand_parts[] = { .name = "kernel", .offset = 0, .size = SZ_2M, - }, - { + }, { .name = "root", .offset = SZ_2M, .size = (SZ_16M - SZ_2M), - }, - { + }, { .name = "user", .offset = SZ_16M, .size = SZ_8M, - }, - { + }, { .name = "recovery", .offset = (SZ_16M + SZ_8M), .size = SZ_8M, @@ -288,7 +286,6 @@ subsys_initcall(db88f5281_pci_init); ****************************************************************************/ static struct mv643xx_eth_platform_data db88f5281_eth_data = { .phy_addr = 8, - .force_phy_addr = 1, }; /***************************************************************************** @@ -301,11 +298,28 @@ static struct i2c_board_info __initdata db88f5281_i2c_rtc = { /***************************************************************************** * General Setup ****************************************************************************/ - -static struct platform_device *db88f5281_devs[] __initdata = { - &db88f5281_boot_flash, - &db88f5281_nor_flash, - &db88f5281_nand_flash, +static struct orion5x_mpp_mode db88f5281_mpp_modes[] __initdata = { + { 0, MPP_GPIO }, /* USB Over Current */ + { 1, MPP_GPIO }, /* USB Vbat input */ + { 2, MPP_PCI_ARB }, /* PCI_REQn[2] */ + { 3, MPP_PCI_ARB }, /* PCI_GNTn[2] */ + { 4, MPP_PCI_ARB }, /* PCI_REQn[3] */ + { 5, MPP_PCI_ARB }, /* PCI_GNTn[3] */ + { 6, MPP_GPIO }, /* JP0, CON17.2 */ + { 7, MPP_GPIO }, /* JP1, CON17.1 */ + { 8, MPP_GPIO }, /* JP2, CON11.2 */ + { 9, MPP_GPIO }, /* JP3, CON11.3 */ + { 10, MPP_GPIO }, /* RTC int */ + { 11, MPP_GPIO }, /* Baud Rate Generator */ + { 12, MPP_GPIO }, /* PCI int 1 */ + { 13, MPP_GPIO }, /* PCI int 2 */ + { 14, MPP_NAND }, /* NAND_REn[2] */ + { 15, MPP_NAND }, /* NAND_WEn[2] */ + { 16, MPP_UART }, /* UART1_RX */ + { 17, MPP_UART }, /* UART1_TX */ + { 18, MPP_UART }, /* UART1_CTSn */ + { 19, MPP_UART }, /* UART1_RTSn */ + { -1 }, }; static void __init db88f5281_init(void) @@ -315,39 +329,31 @@ static void __init db88f5281_init(void) */ orion5x_init(); + orion5x_mpp_conf(db88f5281_mpp_modes); + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ + /* - * Setup the CPU address decode windows for our on-board devices + * Configure peripherals. */ + orion5x_ehci0_init(); + orion5x_eth_init(&db88f5281_eth_data); + orion5x_i2c_init(); + orion5x_uart0_init(); + orion5x_uart1_init(); + orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, DB88F5281_NOR_BOOT_SIZE); + platform_device_register(&db88f5281_boot_flash); + orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); - orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); - orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); - /* - * Setup Multiplexing Pins: - * MPP0: GPIO (USB Over Current) MPP1: GPIO (USB Vbat input) - * MPP2: PCI_REQn[2] MPP3: PCI_GNTn[2] - * MPP4: PCI_REQn[3] MPP5: PCI_GNTn[3] - * MPP6: GPIO (JP0, CON17.2) MPP7: GPIO (JP1, CON17.1) - * MPP8: GPIO (JP2, CON11.2) MPP9: GPIO (JP3, CON11.3) - * MPP10: GPIO (RTC int) MPP11: GPIO (Baud Rate Generator) - * MPP12: GPIO (PCI int 1) MPP13: GPIO (PCI int 2) - * MPP14: NAND_REn[2] MPP15: NAND_WEn[2] - * MPP16: UART1_RX MPP17: UART1_TX - * MPP18: UART1_CTS MPP19: UART1_RTS - * MPP-DEV: DEV_D[16:31] - */ - orion5x_write(MPP_0_7_CTRL, 0x00222203); - orion5x_write(MPP_8_15_CTRL, 0x44000000); - orion5x_write(MPP_16_19_CTRL, 0); - orion5x_write(MPP_DEV_CTRL, 0); + orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE); + platform_device_register(&db88f5281_nor_flash); - orion5x_gpio_set_valid_pins(0x00003fc3); + orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE); + platform_device_register(&db88f5281_nand_flash); - platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs)); i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); - orion5x_eth_init(&db88f5281_eth_data); } MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 27ce967ab9e..3791ca6f001 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -27,6 +27,7 @@ #include <asm/mach/pci.h> #include <asm/arch/orion5x.h> #include "common.h" +#include "mpp.h" #define DNS323_GPIO_LED_RIGHT_AMBER 1 #define DNS323_GPIO_LED_LEFT_AMBER 2 @@ -52,8 +53,6 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) if (irq != -1) return irq; - pr_err("%s: requested mapping for unknown device\n", __func__); - return -1; } @@ -81,7 +80,6 @@ subsys_initcall(dns323_pci_init); static struct mv643xx_eth_platform_data dns323_eth_data = { .phy_addr = 8, - .force_phy_addr = 1, }; /**************************************************************************** @@ -119,7 +117,7 @@ static struct mtd_partition dns323_partitions[] = { .name = "u-boot", .size = 0x00030000, .offset = 0x007d0000, - } + }, }; static struct physmap_flash_data dns323_nor_flash_data = { @@ -137,7 +135,9 @@ static struct resource dns323_nor_flash_resource = { static struct platform_device dns323_nor_flash = { .name = "physmap-flash", .id = 0, - .dev = { .platform_data = &dns323_nor_flash_data, }, + .dev = { + .platform_data = &dns323_nor_flash_data, + }, .resource = &dns323_nor_flash_resource, .num_resources = 1, }; @@ -170,7 +170,9 @@ static struct gpio_led_platform_data dns323_led_data = { static struct platform_device dns323_gpio_leds = { .name = "leds-gpio", .id = -1, - .dev = { .platform_data = &dns323_led_data, }, + .dev = { + .platform_data = &dns323_led_data, + }, }; /**************************************************************************** @@ -183,35 +185,53 @@ static struct gpio_keys_button dns323_buttons[] = { .gpio = DNS323_GPIO_KEY_RESET, .desc = "Reset Button", .active_low = 1, - }, - { + }, { .code = KEY_POWER, .gpio = DNS323_GPIO_KEY_POWER, .desc = "Power Button", .active_low = 1, - } + }, }; static struct gpio_keys_platform_data dns323_button_data = { .buttons = dns323_buttons, - .nbuttons = ARRAY_SIZE(dns323_buttons), + .nbuttons = ARRAY_SIZE(dns323_buttons), }; static struct platform_device dns323_button_device = { .name = "gpio-keys", .id = -1, .num_resources = 0, - .dev = { .platform_data = &dns323_button_data, }, + .dev = { + .platform_data = &dns323_button_data, + }, }; /**************************************************************************** * General Setup */ - -static struct platform_device *dns323_plat_devices[] __initdata = { - &dns323_nor_flash, - &dns323_gpio_leds, - &dns323_button_device, +static struct orion5x_mpp_mode dns323_mpp_modes[] __initdata = { + { 0, MPP_PCIE_RST_OUTn }, + { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ + { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ + { 3, MPP_UNUSED }, + { 4, MPP_GPIO }, /* power button LED */ + { 5, MPP_GPIO }, /* power button LED */ + { 6, MPP_GPIO }, /* GMT G751-2f overtemp */ + { 7, MPP_GPIO }, /* M41T80 nIRQ/OUT/SQW */ + { 8, MPP_GPIO }, /* triggers power off */ + { 9, MPP_GPIO }, /* power button switch */ + { 10, MPP_GPIO }, /* reset button switch */ + { 11, MPP_UNUSED }, + { 12, MPP_UNUSED }, + { 13, MPP_UNUSED }, + { 14, MPP_UNUSED }, + { 15, MPP_UNUSED }, + { 16, MPP_UNUSED }, + { 17, MPP_UNUSED }, + { 18, MPP_UNUSED }, + { 19, MPP_UNUSED }, + { -1 }, }; /* @@ -225,17 +245,15 @@ static struct platform_device *dns323_plat_devices[] __initdata = { static struct i2c_board_info __initdata dns323_i2c_devices[] = { { I2C_BOARD_INFO("g760a", 0x3e), - }, #if 0 /* this entry requires the new-style driver model lm75 driver, * for the meantime "insmod lm75.ko force_lm75=0,0x48" is needed */ - { + }, { I2C_BOARD_INFO("g751", 0x48), - }, #endif - { + }, { I2C_BOARD_INFO("m41t80", 0x68), - } + }, }; /* DNS-323 specific power off method */ @@ -250,62 +268,35 @@ static void __init dns323_init(void) /* Setup basic Orion functions. Need to be called early. */ orion5x_init(); + orion5x_mpp_conf(dns323_mpp_modes); + writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ + + /* + * Configure peripherals. + */ + orion5x_ehci0_init(); + orion5x_eth_init(&dns323_eth_data); + orion5x_i2c_init(); + orion5x_uart0_init(); + /* setup flash mapping * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 */ orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); + platform_device_register(&dns323_nor_flash); - /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIe - * - * Open a special address decode windows for the PCIe WA. - */ - orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, - ORION5X_PCIE_WA_SIZE); - - /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */ - orion5x_write(MPP_0_7_CTRL, 0); - orion5x_write(MPP_8_15_CTRL, 0); - orion5x_write(MPP_16_19_CTRL, 0); - orion5x_write(MPP_DEV_CTRL, 0); - - /* Define used GPIO pins - - GPIO Map: - - | 0 | | PEX_RST_OUT (not controlled by GPIO) - | 1 | Out | right amber LED (= sata ch0 LED) (low-active) - | 2 | Out | left amber LED (= sata ch1 LED) (low-active) - | 3 | Out | //unknown// - | 4 | Out | power button LED (low-active, together with pin #5) - | 5 | Out | power button LED (low-active, together with pin #4) - | 6 | In | GMT G751-2f overtemp. shutdown signal (low-active) - | 7 | In | M41T80 nIRQ/OUT/SQW signal - | 8 | Out | triggers power off (high-active) - | 9 | In | power button switch (low-active) - | 10 | In | reset button switch (low-active) - | 11 | Out | //unknown// - | 12 | Out | //unknown// - | 13 | Out | //unknown// - | 14 | Out | //unknown// - | 15 | Out | //unknown// - */ - orion5x_gpio_set_valid_pins(0x07f6); - - /* register dns323 specific power-off method */ - if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0) - || (gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)) - pr_err("DNS323: failed to setup power-off GPIO\n"); - - pm_power_off = dns323_power_off; + platform_device_register(&dns323_gpio_leds); - /* register flash and other platform devices */ - platform_add_devices(dns323_plat_devices, - ARRAY_SIZE(dns323_plat_devices)); + platform_device_register(&dns323_button_device); i2c_register_board_info(0, dns323_i2c_devices, ARRAY_SIZE(dns323_i2c_devices)); - orion5x_eth_init(&dns323_eth_data); + /* register dns323 specific power-off method */ + if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 || + gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0) + pr_err("DNS323: failed to setup power-off GPIO\n"); + pm_power_off = dns323_power_off; } /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ diff --git a/arch/arm/mach-orion5x/gpio.c b/arch/arm/mach-orion5x/gpio.c index 8108c316c42..d09797990f4 100644 --- a/arch/arm/mach-orion5x/gpio.c +++ b/arch/arm/mach-orion5x/gpio.c @@ -24,9 +24,12 @@ static DEFINE_SPINLOCK(gpio_lock); static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ -void __init orion5x_gpio_set_valid_pins(u32 pins) +void __init orion5x_gpio_set_valid(unsigned pin, int valid) { - gpio_valid[0] = pins; + if (valid) + __set_bit(pin, gpio_valid); + else + __clear_bit(pin, gpio_valid); } /* @@ -93,10 +96,10 @@ int gpio_get_value(unsigned pin) { int val, mask = 1 << pin; - if (orion5x_read(GPIO_IO_CONF) & mask) - val = orion5x_read(GPIO_DATA_IN) ^ orion5x_read(GPIO_IN_POL); + if (readl(GPIO_IO_CONF) & mask) + val = readl(GPIO_DATA_IN) ^ readl(GPIO_IN_POL); else - val = orion5x_read(GPIO_OUT); + val = readl(GPIO_OUT); return val & mask; } @@ -188,39 +191,39 @@ void gpio_display(void) printk("GPIO, free\n"); } else { printk("GPIO, used by %s, ", gpio_label[i]); - if (orion5x_read(GPIO_IO_CONF) & (1 << i)) { + if (readl(GPIO_IO_CONF) & (1 << i)) { printk("input, active %s, level %s, edge %s\n", - ((orion5x_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", - ((orion5x_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", - ((orion5x_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); + ((readl(GPIO_IN_POL) >> i) & 1) ? "low" : "high", + ((readl(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", + ((readl(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); } else { - printk("output, val=%d\n", (orion5x_read(GPIO_OUT) >> i) & 1); + printk("output, val=%d\n", (readl(GPIO_OUT) >> i) & 1); } } } printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n", - MPP_0_7_CTRL, orion5x_read(MPP_0_7_CTRL)); + MPP_0_7_CTRL, readl(MPP_0_7_CTRL)); printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n", - MPP_8_15_CTRL, orion5x_read(MPP_8_15_CTRL)); + MPP_8_15_CTRL, readl(MPP_8_15_CTRL)); printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n", - MPP_16_19_CTRL, orion5x_read(MPP_16_19_CTRL)); + MPP_16_19_CTRL, readl(MPP_16_19_CTRL)); printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n", - MPP_DEV_CTRL, orion5x_read(MPP_DEV_CTRL)); + MPP_DEV_CTRL, readl(MPP_DEV_CTRL)); printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n", - GPIO_OUT, orion5x_read(GPIO_OUT)); + GPIO_OUT, readl(GPIO_OUT)); printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n", - GPIO_IO_CONF, orion5x_read(GPIO_IO_CONF)); + GPIO_IO_CONF, readl(GPIO_IO_CONF)); printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n", - GPIO_BLINK_EN, orion5x_read(GPIO_BLINK_EN)); + GPIO_BLINK_EN, readl(GPIO_BLINK_EN)); printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n", - GPIO_IN_POL, orion5x_read(GPIO_IN_POL)); + GPIO_IN_POL, readl(GPIO_IN_POL)); printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n", - GPIO_DATA_IN, orion5x_read(GPIO_DATA_IN)); + GPIO_DATA_IN, readl(GPIO_DATA_IN)); printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n", - GPIO_LEVEL_MASK, orion5x_read(GPIO_LEVEL_MASK)); + GPIO_LEVEL_MASK, readl(GPIO_LEVEL_MASK)); printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n", - GPIO_EDGE_CAUSE, orion5x_read(GPIO_EDGE_CAUSE)); + GPIO_EDGE_CAUSE, readl(GPIO_EDGE_CAUSE)); printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n", - GPIO_EDGE_MASK, orion5x_read(GPIO_EDGE_MASK)); + GPIO_EDGE_MASK, readl(GPIO_EDGE_MASK)); } diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index dd21f38c5d3..e2a0084ab4a 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -82,7 +82,7 @@ static int orion5x_gpio_set_irq_type(u32 irq, u32 type) int pin = irq_to_gpio(irq); struct irq_desc *desc; - if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) { + if ((readl(GPIO_IO_CONF) & (1 << pin)) == 0) { printk(KERN_ERR "orion5x_gpio_set_irq_type failed " "(irq %d, pin %d).\n", irq, pin); return -EINVAL; @@ -117,7 +117,7 @@ static int orion5x_gpio_set_irq_type(u32 irq, u32 type) /* * set initial polarity based on current input level */ - if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN)) + if ((readl(GPIO_IN_POL) ^ readl(GPIO_DATA_IN)) & (1 << pin)) orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ else @@ -149,8 +149,8 @@ static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31); offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8; - cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) | - (orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK)); + cause = (readl(GPIO_DATA_IN) & readl(GPIO_LEVEL_MASK)) | + (readl(GPIO_EDGE_CAUSE) & readl(GPIO_EDGE_MASK)); for (pin = offs; pin < offs + 8; pin++) { if (cause & (1 << pin)) { @@ -158,9 +158,9 @@ static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) desc = irq_desc + irq; if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { /* Swap polarity (race with GPIO line) */ - u32 polarity = orion5x_read(GPIO_IN_POL); + u32 polarity = readl(GPIO_IN_POL); polarity ^= 1 << pin; - orion5x_write(GPIO_IN_POL, polarity); + writel(polarity, GPIO_IN_POL); } desc_handle_irq(irq, desc); } @@ -175,9 +175,9 @@ static void __init orion5x_init_gpio_irq(void) /* * Mask and clear GPIO IRQ interrupts */ - orion5x_write(GPIO_LEVEL_MASK, 0x0); - orion5x_write(GPIO_EDGE_MASK, 0x0); - orion5x_write(GPIO_EDGE_CAUSE, 0x0); + writel(0x0, GPIO_LEVEL_MASK); + writel(0x0, GPIO_EDGE_MASK); + writel(0x0, GPIO_EDGE_CAUSE); /* * Register chained level handlers for GPIO IRQs by default. diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index f5074b877b7..84feac4a1fe 100644 --- a/arch/arm/mach-orion5x/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c @@ -13,10 +13,12 @@ #include <linux/platform_device.h> #include <linux/pci.h> #include <linux/irq.h> +#include <linux/delay.h> #include <linux/mtd/physmap.h> #include <linux/mtd/nand.h> #include <linux/mv643xx_eth.h> #include <linux/i2c.h> +#include <linux/serial_reg.h> #include <linux/ata_platform.h> #include <asm/mach-types.h> #include <asm/gpio.h> @@ -25,6 +27,7 @@ #include <asm/arch/orion5x.h> #include <asm/plat-orion/orion_nand.h> #include "common.h" +#include "mpp.h" /***************************************************************************** * KUROBOX-PRO Info @@ -53,13 +56,11 @@ static struct mtd_partition kurobox_pro_nand_parts[] = { .name = "uImage", .offset = 0, .size = SZ_4M, - }, - { + }, { .name = "rootfs", .offset = SZ_4M, .size = SZ_64M, - }, - { + }, { .name = "extra", .offset = SZ_4M + SZ_64M, .size = SZ_256M - (SZ_4M + SZ_64M), @@ -132,8 +133,6 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) /* * PCI isn't used on the Kuro */ - printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n"); - return -1; } @@ -161,7 +160,6 @@ subsys_initcall(kurobox_pro_pci_init); static struct mv643xx_eth_platform_data kurobox_pro_eth_data = { .phy_addr = 8, - .force_phy_addr = 1, }; /***************************************************************************** @@ -175,12 +173,169 @@ static struct i2c_board_info __initdata kurobox_pro_i2c_rtc = { * SATA ****************************************************************************/ static struct mv_sata_platform_data kurobox_pro_sata_data = { - .n_ports = 2, + .n_ports = 2, }; /***************************************************************************** + * Kurobox Pro specific power off method via UART1-attached microcontroller + ****************************************************************************/ + +#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) + +static int kurobox_pro_miconread(unsigned char *buf, int count) +{ + int i; + int timeout; + + for (i = 0; i < count; i++) { + timeout = 10; + + while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) { + if (--timeout == 0) + break; + udelay(1000); + } + + if (timeout == 0) + break; + buf[i] = readl(UART1_REG(RX)); + } + + /* return read bytes */ + return i; +} + +static int kurobox_pro_miconwrite(const unsigned char *buf, int count) +{ + int i = 0; + + while (count--) { + while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE)) + barrier(); + writel(buf[i++], UART1_REG(TX)); + } + + return 0; +} + +static int kurobox_pro_miconsend(const unsigned char *data, int count) +{ + int i; + unsigned char checksum = 0; + unsigned char recv_buf[40]; + unsigned char send_buf[40]; + unsigned char correct_ack[3]; + int retry = 2; + + /* Generate checksum */ + for (i = 0; i < count; i++) + checksum -= data[i]; + + do { + /* Send data */ + kurobox_pro_miconwrite(data, count); + + /* send checksum */ + kurobox_pro_miconwrite(&checksum, 1); + + if (kurobox_pro_miconread(recv_buf, sizeof(recv_buf)) <= 3) { + printk(KERN_ERR ">%s: receive failed.\n", __func__); + + /* send preamble to clear the receive buffer */ + memset(&send_buf, 0xff, sizeof(send_buf)); + kurobox_pro_miconwrite(send_buf, sizeof(send_buf)); + + /* make dummy reads */ + mdelay(100); + kurobox_pro_miconread(recv_buf, sizeof(recv_buf)); + } else { + /* Generate expected ack */ + correct_ack[0] = 0x01; + correct_ack[1] = data[1]; + correct_ack[2] = 0x00; + + /* checksum Check */ + if ((recv_buf[0] + recv_buf[1] + recv_buf[2] + + recv_buf[3]) & 0xFF) { + printk(KERN_ERR ">%s: Checksum Error : " + "Received data[%02x, %02x, %02x, %02x]" + "\n", __func__, recv_buf[0], + recv_buf[1], recv_buf[2], recv_buf[3]); + } else { + /* Check Received Data */ + if (correct_ack[0] == recv_buf[0] && + correct_ack[1] == recv_buf[1] && + correct_ack[2] == recv_buf[2]) { + /* Interval for next command */ + mdelay(10); + + /* Receive ACK */ + return 0; + } + } + /* Received NAK or illegal Data */ + printk(KERN_ERR ">%s: Error : NAK or Illegal Data " + "Received\n", __func__); + } + } while (retry--); + + /* Interval for next command */ + mdelay(10); + + return -1; +} + +static void kurobox_pro_power_off(void) +{ + const unsigned char watchdogkill[] = {0x01, 0x35, 0x00}; + const unsigned char shutdownwait[] = {0x00, 0x0c}; + const unsigned char poweroff[] = {0x00, 0x06}; + /* 38400 baud divisor */ + const unsigned divisor = ((ORION5X_TCLK + (8 * 38400)) / (16 * 38400)); + + pr_info("%s: triggering power-off...\n", __func__); + + /* hijack uart1 and reset into sane state (38400,8n1,even parity) */ + writel(0x83, UART1_REG(LCR)); + writel(divisor & 0xff, UART1_REG(DLL)); + writel((divisor >> 8) & 0xff, UART1_REG(DLM)); + writel(0x1b, UART1_REG(LCR)); + writel(0x00, UART1_REG(IER)); + writel(0x07, UART1_REG(FCR)); + writel(0x00, UART1_REG(MCR)); + + /* Send the commands to shutdown the Kurobox Pro */ + kurobox_pro_miconsend(watchdogkill, sizeof(watchdogkill)) ; + kurobox_pro_miconsend(shutdownwait, sizeof(shutdownwait)) ; + kurobox_pro_miconsend(poweroff, sizeof(poweroff)); +} + +/***************************************************************************** * General Setup ****************************************************************************/ +static struct orion5x_mpp_mode kurobox_pro_mpp_modes[] __initdata = { + { 0, MPP_UNUSED }, + { 1, MPP_UNUSED }, + { 2, MPP_GPIO }, /* GPIO Micon */ + { 3, MPP_GPIO }, /* GPIO Rtc */ + { 4, MPP_UNUSED }, + { 5, MPP_UNUSED }, + { 6, MPP_NAND }, /* NAND Flash REn */ + { 7, MPP_NAND }, /* NAND Flash WEn */ + { 8, MPP_UNUSED }, + { 9, MPP_UNUSED }, + { 10, MPP_UNUSED }, + { 11, MPP_UNUSED }, + { 12, MPP_SATA_LED }, /* SATA 0 presence */ + { 13, MPP_SATA_LED }, /* SATA 1 presence */ + { 14, MPP_SATA_LED }, /* SATA 0 active */ + { 15, MPP_SATA_LED }, /* SATA 1 active */ + { 16, MPP_UART }, /* UART1 RXD */ + { 17, MPP_UART }, /* UART1 TXD */ + { 18, MPP_UART }, /* UART1 CTSn */ + { 19, MPP_UART }, /* UART1 RTSn */ + { -1 }, +}; static void __init kurobox_pro_init(void) { @@ -189,46 +344,33 @@ static void __init kurobox_pro_init(void) */ orion5x_init(); - /* - * Setup the CPU address decode windows for our devices - */ - orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, - KUROBOX_PRO_NOR_BOOT_SIZE); - orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE); + orion5x_mpp_conf(kurobox_pro_mpp_modes); /* - * Open a special address decode windows for the PCIe WA. + * Configure peripherals. */ - orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, - ORION5X_PCIE_WA_SIZE); - - /* - * Setup Multiplexing Pins -- - * MPP[0-1] Not used - * MPP[2] GPIO Micon - * MPP[3] GPIO RTC - * MPP[4-5] Not used - * MPP[6] Nand Flash REn - * MPP[7] Nand Flash WEn - * MPP[8-11] Not used - * MPP[12] SATA 0 presence Indication - * MPP[13] SATA 1 presence Indication - * MPP[14] SATA 0 active Indication - * MPP[15] SATA 1 active indication - * MPP[16-19] Not used - */ - orion5x_write(MPP_0_7_CTRL, 0x44220003); - orion5x_write(MPP_8_15_CTRL, 0x55550000); - orion5x_write(MPP_16_19_CTRL, 0x0); - - orion5x_gpio_set_valid_pins(0x0000000c); + orion5x_ehci0_init(); + orion5x_ehci1_init(); + orion5x_eth_init(&kurobox_pro_eth_data); + orion5x_i2c_init(); + orion5x_sata_init(&kurobox_pro_sata_data); + orion5x_uart0_init(); + orion5x_uart1_init(); + orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE, + KUROBOX_PRO_NOR_BOOT_SIZE); platform_device_register(&kurobox_pro_nor_flash); - if (machine_is_kurobox_pro()) + + if (machine_is_kurobox_pro()) { + orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, + KUROBOX_PRO_NAND_SIZE); platform_device_register(&kurobox_pro_nand_flash); + } + i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1); - orion5x_eth_init(&kurobox_pro_eth_data); - orion5x_sata_init(&kurobox_pro_sata_data); + + /* register Kurobox Pro specific power-off method */ + pm_power_off = kurobox_pro_power_off; } #ifdef CONFIG_MACH_KUROBOX_PRO diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c new file mode 100644 index 00000000000..a48cadb0159 --- /dev/null +++ b/arch/arm/mach-orion5x/mpp.c @@ -0,0 +1,163 @@ +/* + * arch/arm/mach-orion5x/mpp.c + * + * MPP functions for Marvell Orion 5x SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mbus.h> +#include <asm/hardware.h> +#include <asm/io.h> +#include "common.h" +#include "mpp.h" + +static int is_5181l(void) +{ + u32 dev; + u32 rev; + + orion5x_pcie_id(&dev, &rev); + + return !!(dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0); +} + +static int is_5182(void) +{ + u32 dev; + u32 rev; + + orion5x_pcie_id(&dev, &rev); + + return !!(dev == MV88F5182_DEV_ID); +} + +static int is_5281(void) +{ + u32 dev; + u32 rev; + + orion5x_pcie_id(&dev, &rev); + + return !!(dev == MV88F5281_DEV_ID); +} + +static int __init determine_type_encoding(int mpp, enum orion5x_mpp_type type) +{ + switch (type) { + case MPP_UNUSED: + case MPP_GPIO: + if (mpp == 0) + return 3; + if (mpp >= 1 && mpp <= 15) + return 0; + if (mpp >= 16 && mpp <= 19) { + if (is_5182()) + return 5; + if (type == MPP_UNUSED) + return 0; + } + return -1; + + case MPP_PCIE_RST_OUTn: + if (mpp == 0) + return 0; + return -1; + + case MPP_PCI_ARB: + if (mpp >= 0 && mpp <= 7) + return 2; + return -1; + + case MPP_PCI_PMEn: + if (mpp == 2) + return 3; + return -1; + + case MPP_GIGE: + if (mpp >= 8 && mpp <= 19) + return 1; + return -1; + + case MPP_NAND: + if (is_5182() || is_5281()) { + if (mpp >= 4 && mpp <= 7) + return 4; + if (mpp >= 12 && mpp <= 17) + return 4; + } + return -1; + + case MPP_PCI_CLK: + if (is_5181l() && mpp >= 6 && mpp <= 7) + return 5; + return -1; + + case MPP_SATA_LED: + if (is_5182()) { + if (mpp >= 4 && mpp <= 7) + return 5; + if (mpp >= 12 && mpp <= 15) + return 5; + } + return -1; + + case MPP_UART: + if (mpp >= 16 && mpp <= 19) + return 0; + return -1; + } + + printk(KERN_INFO "unknown MPP type %d\n", type); + + return -1; +} + +void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode) +{ + u32 mpp_0_7_ctrl = readl(MPP_0_7_CTRL); + u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL); + u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL); + + while (mode->mpp >= 0) { + u32 *reg; + int num_type; + int shift; + + if (mode->mpp >= 0 && mode->mpp <= 7) + reg = &mpp_0_7_ctrl; + else if (mode->mpp >= 8 && mode->mpp <= 15) + reg = &mpp_8_15_ctrl; + else if (mode->mpp >= 16 && mode->mpp <= 19) + reg = &mpp_16_19_ctrl; + else { + printk(KERN_ERR "orion5x_mpp_conf: invalid MPP " + "(%d)\n", mode->mpp); + continue; + } + + num_type = determine_type_encoding(mode->mpp, mode->type); + if (num_type < 0) { + printk(KERN_ERR "orion5x_mpp_conf: invalid MPP " + "combination (%d, %d)\n", mode->mpp, + mode->type); + continue; + } + + shift = (mode->mpp & 7) << 2; + *reg &= ~(0xf << shift); + *reg |= (num_type & 0xf) << shift; + + orion5x_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO)); + + mode++; + } + + writel(mpp_0_7_ctrl, MPP_0_7_CTRL); + writel(mpp_8_15_ctrl, MPP_8_15_CTRL); + writel(mpp_16_19_ctrl, MPP_16_19_CTRL); +} diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h new file mode 100644 index 00000000000..290e610dc01 --- /dev/null +++ b/arch/arm/mach-orion5x/mpp.h @@ -0,0 +1,74 @@ +#ifndef __ARCH_ORION5X_MPP_H +#define __ARCH_ORION5X_MPP_H + +enum orion5x_mpp_type { + /* + * This MPP is unused. + */ + MPP_UNUSED, + + /* + * This MPP pin is used as a generic GPIO pin. Valid for + * MPPs 0-15 and device bus data pins 16-31. On 5182, also + * valid for MPPs 16-19. + */ + MPP_GPIO, + + /* + * This MPP is used as PCIe_RST_OUTn pin. Valid for + * MPP 0 only. + */ + MPP_PCIE_RST_OUTn, + + /* + * This MPP is used as PCI arbiter pin (REQn/GNTn). + * Valid for MPPs 0-7 only. + */ + MPP_PCI_ARB, + + /* + * This MPP is used as PCI_PMEn pin. Valid for MPP 2 only. + */ + MPP_PCI_PMEn, + + /* + * This MPP is used as GigE half-duplex (COL, CRS) or GMII + * (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin. Valid for + * MPPs 8-19 only. + */ + MPP_GIGE, + + /* + * This MPP is used as NAND REn/WEn pin. Valid for MPPs + * 4-7 and 12-17 only, and only on the 5181l/5182/5281. + */ + MPP_NAND, + + /* + * This MPP is used as a PCI clock output pin. Valid for + * MPPs 6-7 only, and only on the 5181l. + */ + MPP_PCI_CLK, + + /* + * This MPP is used as a SATA presence/activity LED. + * Valid for MPPs 4-7 and 12-15 only, and only on the 5182. + */ + MPP_SATA_LED, + + /* + * This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin. + * Valid for MPPs 16-19 only. + */ + MPP_UART, +}; + +struct orion5x_mpp_mode { + int mpp; + enum orion5x_mpp_type type; +}; + +void orion5x_mpp_conf(struct orion5x_mpp_mode *mode); + + +#endif diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c new file mode 100644 index 00000000000..7ce9e407d9d --- /dev/null +++ b/arch/arm/mach-orion5x/mss2-setup.c @@ -0,0 +1,270 @@ +/* + * Maxtor Shared Storage II Board Setup + * + * Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pci.h> +#include <linux/irq.h> +#include <linux/mtd/physmap.h> +#include <linux/mv643xx_eth.h> +#include <linux/leds.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <linux/i2c.h> +#include <linux/ata_platform.h> +#include <linux/gpio.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/pci.h> +#include <asm/arch/orion5x.h> +#include "common.h" +#include "mpp.h" + +#define MSS2_NOR_BOOT_BASE 0xff800000 +#define MSS2_NOR_BOOT_SIZE SZ_256K + +/***************************************************************************** + * Maxtor Shared Storage II Info + ****************************************************************************/ + +/* + * Maxtor Shared Storage II hardware : + * - Marvell 88F5182-A2 C500 + * - Marvell 88E1111 Gigabit Ethernet PHY + * - RTC M41T81 (@0x68) on I2C bus + * - 256KB NOR flash + * - 64MB of RAM + */ + +/***************************************************************************** + * 256KB NOR Flash on BOOT Device + ****************************************************************************/ + +static struct physmap_flash_data mss2_nor_flash_data = { + .width = 1, +}; + +static struct resource mss2_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = MSS2_NOR_BOOT_BASE, + .end = MSS2_NOR_BOOT_BASE + MSS2_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device mss2_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &mss2_nor_flash_data, + }, + .resource = &mss2_nor_flash_resource, + .num_resources = 1, +}; + +/**************************************************************************** + * PCI setup + ****************************************************************************/ +static int __init mss2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq; + + /* + * Check for devices with hard-wired IRQs. + */ + irq = orion5x_pci_map_irq(dev, slot, pin); + if (irq != -1) + return irq; + + return -1; +} + +static struct hw_pci mss2_pci __initdata = { + .nr_controllers = 2, + .swizzle = pci_std_swizzle, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = mss2_pci_map_irq, +}; + +static int __init mss2_pci_init(void) +{ + if (machine_is_mss2()) + pci_common_init(&mss2_pci); + + return 0; +} +subsys_initcall(mss2_pci_init); + + +/***************************************************************************** + * Ethernet + ****************************************************************************/ + +static struct mv643xx_eth_platform_data mss2_eth_data = { + .phy_addr = 8, +}; + +/***************************************************************************** + * SATA + ****************************************************************************/ + +static struct mv_sata_platform_data mss2_sata_data = { + .n_ports = 2, +}; + +/***************************************************************************** + * GPIO buttons + ****************************************************************************/ + +#define MSS2_GPIO_KEY_RESET 12 +#define MSS2_GPIO_KEY_POWER 11 + +static struct gpio_keys_button mss2_buttons[] = { + { + .code = KEY_POWER, + .gpio = MSS2_GPIO_KEY_POWER, + .desc = "Power", + .active_low = 1, + }, { + .code = KEY_RESTART, + .gpio = MSS2_GPIO_KEY_RESET, + .desc = "Reset", + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data mss2_button_data = { + .buttons = mss2_buttons, + .nbuttons = ARRAY_SIZE(mss2_buttons), +}; + +static struct platform_device mss2_button_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &mss2_button_data, + }, +}; + +/***************************************************************************** + * RTC m41t81 on I2C bus + ****************************************************************************/ + +#define MSS2_GPIO_RTC_IRQ 3 + +static struct i2c_board_info __initdata mss2_i2c_rtc = { + I2C_BOARD_INFO("m41t81", 0x68), +}; + +/***************************************************************************** + * MSS2 power off method + ****************************************************************************/ +/* + * On the Maxtor Shared Storage II, the shutdown process is the following : + * - Userland modifies U-boot env to tell U-boot to go idle at next boot + * - The board reboots + * - U-boot starts and go into an idle mode until the user press "power" + */ +static void mss2_power_off(void) +{ + u32 reg; + + /* + * Enable and issue soft reset + */ + reg = readl(CPU_RESET_MASK); + reg |= 1 << 2; + writel(reg, CPU_RESET_MASK); + + reg = readl(CPU_SOFT_RESET); + reg |= 1; + writel(reg, CPU_SOFT_RESET); +} + +/**************************************************************************** + * General Setup + ****************************************************************************/ +static struct orion5x_mpp_mode mss2_mpp_modes[] __initdata = { + { 0, MPP_GPIO }, /* Power LED */ + { 1, MPP_GPIO }, /* Error LED */ + { 2, MPP_UNUSED }, + { 3, MPP_GPIO }, /* RTC interrupt */ + { 4, MPP_GPIO }, /* HDD ind. (Single/Dual)*/ + { 5, MPP_GPIO }, /* HD0 5V control */ + { 6, MPP_GPIO }, /* HD0 12V control */ + { 7, MPP_GPIO }, /* HD1 5V control */ + { 8, MPP_GPIO }, /* HD1 12V control */ + { 9, MPP_UNUSED }, + { 10, MPP_GPIO }, /* Fan control */ + { 11, MPP_GPIO }, /* Power button */ + { 12, MPP_GPIO }, /* Reset button */ + { 13, MPP_UNUSED }, + { 14, MPP_SATA_LED }, /* SATA 0 active */ + { 15, MPP_SATA_LED }, /* SATA 1 active */ + { 16, MPP_UNUSED }, + { 17, MPP_UNUSED }, + { 18, MPP_UNUSED }, + { 19, MPP_UNUSED }, + { -1 }, +}; + +static void __init mss2_init(void) +{ + /* Setup basic Orion functions. Need to be called early. */ + orion5x_init(); + + orion5x_mpp_conf(mss2_mpp_modes); + + /* + * MPP[20] Unused + * MPP[21] PCI clock + * MPP[22] USB 0 over current + * MPP[23] USB 1 over current + */ + + /* + * Configure peripherals. + */ + orion5x_ehci0_init(); + orion5x_ehci1_init(); + orion5x_eth_init(&mss2_eth_data); + orion5x_i2c_init(); + orion5x_sata_init(&mss2_sata_data); + orion5x_uart0_init(); + + orion5x_setup_dev_boot_win(MSS2_NOR_BOOT_BASE, MSS2_NOR_BOOT_SIZE); + platform_device_register(&mss2_nor_flash); + + platform_device_register(&mss2_button_device); + + if (gpio_request(MSS2_GPIO_RTC_IRQ, "rtc") == 0) { + if (gpio_direction_input(MSS2_GPIO_RTC_IRQ) == 0) + mss2_i2c_rtc.irq = gpio_to_irq(MSS2_GPIO_RTC_IRQ); + else + gpio_free(MSS2_GPIO_RTC_IRQ); + } + i2c_register_board_info(0, &mss2_i2c_rtc, 1); + + /* register mss2 specific power-off method */ + pm_power_off = mss2_power_off; +} + +MACHINE_START(MSS2, "Maxtor Shared Storage II") + /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */ + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = mss2_init, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, + .fixup = tag_fixup_mem32 +MACHINE_END diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c new file mode 100644 index 00000000000..f1dcad36b13 --- /dev/null +++ b/arch/arm/mach-orion5x/mv2120-setup.c @@ -0,0 +1,194 @@ +/* + * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org> + * Copyright (C) 2008 Martin Michlmayr <tbm@cyrius.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/irq.h> +#include <linux/mtd/physmap.h> +#include <linux/mv643xx_eth.h> +#include <linux/leds.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <linux/i2c.h> +#include <linux/ata_platform.h> +#include <asm/mach-types.h> +#include <asm/gpio.h> +#include <asm/mach/arch.h> +#include <asm/arch/orion5x.h> +#include "common.h" +#include "mpp.h" + +#define MV2120_NOR_BOOT_BASE 0xf4000000 +#define MV2120_NOR_BOOT_SIZE SZ_512K + +#define MV2120_GPIO_RTC_IRQ 3 +#define MV2120_GPIO_KEY_RESET 17 +#define MV2120_GPIO_KEY_POWER 18 +#define MV2120_GPIO_POWER_OFF 19 + + +/***************************************************************************** + * Ethernet + ****************************************************************************/ +static struct mv643xx_eth_platform_data mv2120_eth_data = { + .phy_addr = 8, +}; + +static struct mv_sata_platform_data mv2120_sata_data = { + .n_ports = 2, +}; + +static struct mtd_partition mv2120_partitions[] = { + { + .name = "firmware", + .size = 0x00080000, + .offset = 0, + }, +}; + +static struct physmap_flash_data mv2120_nor_flash_data = { + .width = 1, + .parts = mv2120_partitions, + .nr_parts = ARRAY_SIZE(mv2120_partitions) +}; + +static struct resource mv2120_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = MV2120_NOR_BOOT_BASE, + .end = MV2120_NOR_BOOT_BASE + MV2120_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device mv2120_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &mv2120_nor_flash_data, + }, + .resource = &mv2120_nor_flash_resource, + .num_resources = 1, +}; + +static struct gpio_keys_button mv2120_buttons[] = { + { + .code = KEY_RESTART, + .gpio = MV2120_GPIO_KEY_RESET, + .desc = "reset", + .active_low = 1, + }, { + .code = KEY_POWER, + .gpio = MV2120_GPIO_KEY_POWER, + .desc = "power", + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data mv2120_button_data = { + .buttons = mv2120_buttons, + .nbuttons = ARRAY_SIZE(mv2120_buttons), +}; + +static struct platform_device mv2120_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &mv2120_button_data, + }, +}; + + +/**************************************************************************** + * General Setup + ****************************************************************************/ +static struct orion5x_mpp_mode mv2120_mpp_modes[] __initdata = { + { 0, MPP_GPIO }, /* Sys status LED */ + { 1, MPP_GPIO }, /* Sys error LED */ + { 2, MPP_GPIO }, /* OverTemp interrupt */ + { 3, MPP_GPIO }, /* RTC interrupt */ + { 4, MPP_GPIO }, /* V_LED 5V */ + { 5, MPP_GPIO }, /* V_LED 3.3V */ + { 6, MPP_UNUSED }, + { 7, MPP_UNUSED }, + { 8, MPP_GPIO }, /* SATA 0 fail LED */ + { 9, MPP_GPIO }, /* SATA 1 fail LED */ + { 10, MPP_UNUSED }, + { 11, MPP_UNUSED }, + { 12, MPP_SATA_LED }, /* SATA 0 presence */ + { 13, MPP_SATA_LED }, /* SATA 1 presence */ + { 14, MPP_SATA_LED }, /* SATA 0 active */ + { 15, MPP_SATA_LED }, /* SATA 1 active */ + { 16, MPP_UNUSED }, + { 17, MPP_GPIO }, /* Reset button */ + { 18, MPP_GPIO }, /* Power button */ + { 19, MPP_GPIO }, /* Power off */ + { -1 }, +}; + +static struct i2c_board_info __initdata mv2120_i2c_rtc = { + I2C_BOARD_INFO("pcf8563", 0x51), + .irq = 0, +}; + +static void mv2120_power_off(void) +{ + pr_info("%s: triggering power-off...\n", __func__); + gpio_set_value(MV2120_GPIO_POWER_OFF, 0); +} + +static void __init mv2120_init(void) +{ + /* Setup basic Orion functions. Need to be called early. */ + orion5x_init(); + + orion5x_mpp_conf(mv2120_mpp_modes); + + /* + * Configure peripherals. + */ + orion5x_ehci0_init(); + orion5x_ehci1_init(); + orion5x_eth_init(&mv2120_eth_data); + orion5x_i2c_init(); + orion5x_sata_init(&mv2120_sata_data); + orion5x_uart0_init(); + + orion5x_setup_dev_boot_win(MV2120_NOR_BOOT_BASE, MV2120_NOR_BOOT_SIZE); + platform_device_register(&mv2120_nor_flash); + + platform_device_register(&mv2120_button_device); + + if (gpio_request(MV2120_GPIO_RTC_IRQ, "rtc") == 0) { + if (gpio_direction_input(MV2120_GPIO_RTC_IRQ) == 0) + mv2120_i2c_rtc.irq = gpio_to_irq(MV2120_GPIO_RTC_IRQ); + else + gpio_free(MV2120_GPIO_RTC_IRQ); + } + i2c_register_board_info(0, &mv2120_i2c_rtc, 1); + + /* register mv2120 specific power-off method */ + if (gpio_request(MV2120_GPIO_POWER_OFF, "POWEROFF") != 0 || + gpio_direction_output(MV2120_GPIO_POWER_OFF, 1) != 0) + pr_err("mv2120: failed to setup power-off GPIO\n"); + pm_power_off = mv2120_power_off; +} + +/* Warning: HP uses a wrong mach-type (=526) in their bootloader */ +MACHINE_START(MV2120, "HP Media Vault mv2120") + /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */ + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = mv2120_init, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, + .fixup = tag_fixup_mem32 +MACHINE_END diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index 9d5d39fa19c..256a4f68093 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -152,6 +152,8 @@ static int __init pcie_setup(struct pci_sys_data *sys) if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " "read transaction workaround\n"); + orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, + ORION5X_PCIE_WA_SIZE); pcie_ops.read = pcie_rd_conf_wa; } @@ -240,13 +242,13 @@ static int __init pcie_setup(struct pci_sys_data *sys) * PCI Address Decode Windows registers */ #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ - ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ - ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ - ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) -#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION5X_PCI_REG(0xc48) : \ - ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ - ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ - ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) + ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ + ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ + ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) +#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ + ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ + ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ + ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) @@ -264,9 +266,11 @@ static int __init pcie_setup(struct pci_sys_data *sys) */ static DEFINE_SPINLOCK(orion5x_pci_lock); +static int orion5x_pci_cardbus_mode; + static int orion5x_pci_local_bus_nr(void) { - u32 conf = orion5x_read(PCI_P2P_CONF); + u32 conf = readl(PCI_P2P_CONF); return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); } @@ -276,11 +280,11 @@ static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, unsigned long flags; spin_lock_irqsave(&orion5x_pci_lock, flags); - orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | - PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | - PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); + writel(PCI_CONF_BUS(bus) | + PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | + PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); - *val = orion5x_read(PCI_CONF_DATA); + *val = readl(PCI_CONF_DATA); if (size == 1) *val = (*val >> (8*(where & 0x3))) & 0xff; @@ -300,9 +304,9 @@ static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, spin_lock_irqsave(&orion5x_pci_lock, flags); - orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | - PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | - PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); + writel(PCI_CONF_BUS(bus) | + PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | + PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); if (size == 4) { __raw_writel(val, PCI_CONF_DATA); @@ -319,14 +323,30 @@ static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, return ret; } +static int orion5x_pci_valid_config(int bus, u32 devfn) +{ + if (bus == orion5x_pci_local_bus_nr()) { + /* + * Don't go out for local device + */ + if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) + return 0; + + /* + * When the PCI signals are directly connected to a + * Cardbus slot, ignore all but device IDs 0 and 1. + */ + if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1) + return 0; + } + + return 1; +} + static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - /* - * Don't go out for local device - */ - if (bus->number == orion5x_pci_local_bus_nr() && - PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) { + if (!orion5x_pci_valid_config(bus->number, devfn)) { *val = 0xffffffff; return PCIBIOS_DEVICE_NOT_FOUND; } @@ -338,8 +358,7 @@ static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - if (bus->number == orion5x_pci_local_bus_nr() && - PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) + if (!orion5x_pci_valid_config(bus->number, devfn)) return PCIBIOS_DEVICE_NOT_FOUND; return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), @@ -353,9 +372,9 @@ static struct pci_ops pci_ops = { static void __init orion5x_pci_set_bus_nr(int nr) { - u32 p2p = orion5x_read(PCI_P2P_CONF); + u32 p2p = readl(PCI_P2P_CONF); - if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) { + if (readl(PCI_MODE) & PCI_MODE_PCIX) { /* * PCI-X mode */ @@ -372,7 +391,7 @@ static void __init orion5x_pci_set_bus_nr(int nr) */ p2p &= ~PCI_P2P_BUS_MASK; p2p |= (nr << PCI_P2P_BUS_OFFS); - orion5x_write(PCI_P2P_CONF, p2p); + writel(p2p, PCI_P2P_CONF); } } @@ -399,7 +418,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) * First, disable windows. */ win_enable = 0xffffffff; - orion5x_write(PCI_BAR_ENABLE, win_enable); + writel(win_enable, PCI_BAR_ENABLE); /* * Setup windows for DDR banks. @@ -425,10 +444,10 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) */ reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); - orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), - (cs->size - 1) & 0xfffff000); - orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), - cs->base & 0xfffff000); + writel((cs->size - 1) & 0xfffff000, + PCI_BAR_SIZE_DDR_CS(cs->cs_index)); + writel(cs->base & 0xfffff000, + PCI_BAR_REMAP_DDR_CS(cs->cs_index)); /* * Enable decode window for this chip select. @@ -439,7 +458,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) /* * Re-enable decode windows. */ - orion5x_write(PCI_BAR_ENABLE, win_enable); + writel(win_enable, PCI_BAR_ENABLE); /* * Disable automatic update of address remaping when writing to BARs. @@ -522,6 +541,11 @@ static void __devinit rc_pci_fixup(struct pci_dev *dev) } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); +void __init orion5x_pci_set_cardbus_mode(void) +{ + orion5x_pci_cardbus_mode = 1; +} + int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) { int ret = 0; diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index 81abc1003aa..10ae6286426 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -26,6 +26,7 @@ #include <asm/mach/pci.h> #include <asm/arch/orion5x.h> #include "common.h" +#include "mpp.h" /***************************************************************************** * RD-88F5182 Info @@ -125,6 +126,7 @@ static int __init rd88f5182_dbgled_init(void) leds_event = rd88f5182_dbgled_event; } + return 0; } @@ -220,7 +222,6 @@ subsys_initcall(rd88f5182_pci_init); static struct mv643xx_eth_platform_data rd88f5182_eth_data = { .phy_addr = 8, - .force_phy_addr = 1, }; /***************************************************************************** @@ -234,15 +235,34 @@ static struct i2c_board_info __initdata rd88f5182_i2c_rtc = { * Sata ****************************************************************************/ static struct mv_sata_platform_data rd88f5182_sata_data = { - .n_ports = 2, + .n_ports = 2, }; /***************************************************************************** * General Setup ****************************************************************************/ - -static struct platform_device *rd88f5182_devices[] __initdata = { - &rd88f5182_nor_flash, +static struct orion5x_mpp_mode rd88f5182_mpp_modes[] __initdata = { + { 0, MPP_GPIO }, /* Debug Led */ + { 1, MPP_GPIO }, /* Reset Switch */ + { 2, MPP_UNUSED }, + { 3, MPP_GPIO }, /* RTC Int */ + { 4, MPP_GPIO }, + { 5, MPP_GPIO }, + { 6, MPP_GPIO }, /* PCI_intA */ + { 7, MPP_GPIO }, /* PCI_intB */ + { 8, MPP_UNUSED }, + { 9, MPP_UNUSED }, + { 10, MPP_UNUSED }, + { 11, MPP_UNUSED }, + { 12, MPP_SATA_LED }, /* SATA 0 presence */ + { 13, MPP_SATA_LED }, /* SATA 1 presence */ + { 14, MPP_SATA_LED }, /* SATA 0 active */ + { 15, MPP_SATA_LED }, /* SATA 1 active */ + { 16, MPP_UNUSED }, + { 17, MPP_UNUSED }, + { 18, MPP_UNUSED }, + { 19, MPP_UNUSED }, + { -1 }, }; static void __init rd88f5182_init(void) @@ -252,35 +272,9 @@ static void __init rd88f5182_init(void) */ orion5x_init(); - /* - * Setup the CPU address decode windows for our devices - */ - orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, - RD88F5182_NOR_BOOT_SIZE); - orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); - - /* - * Open a special address decode windows for the PCIe WA. - */ - orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, - ORION5X_PCIE_WA_SIZE); + orion5x_mpp_conf(rd88f5182_mpp_modes); /* - * Setup Multiplexing Pins -- - * MPP[0] Debug Led (GPIO - Out) - * MPP[1] Debug Led (GPIO - Out) - * MPP[2] N/A - * MPP[3] RTC_Int (GPIO - In) - * MPP[4] GPIO - * MPP[5] GPIO - * MPP[6] PCI_intA (GPIO - In) - * MPP[7] PCI_intB (GPIO - In) - * MPP[8-11] N/A - * MPP[12] SATA 0 presence Indication - * MPP[13] SATA 1 presence Indication - * MPP[14] SATA 0 active Indication - * MPP[15] SATA 1 active indication - * MPP[16-19] Not used * MPP[20] PCI Clock to MV88F5182 * MPP[21] PCI Clock to mini PCI CON11 * MPP[22] USB 0 over current indication @@ -289,16 +283,23 @@ static void __init rd88f5182_init(void) * MPP[25] USB 0 over current enable */ - orion5x_write(MPP_0_7_CTRL, 0x00000003); - orion5x_write(MPP_8_15_CTRL, 0x55550000); - orion5x_write(MPP_16_19_CTRL, 0x5555); + /* + * Configure peripherals. + */ + orion5x_ehci0_init(); + orion5x_ehci1_init(); + orion5x_eth_init(&rd88f5182_eth_data); + orion5x_i2c_init(); + orion5x_sata_init(&rd88f5182_sata_data); + orion5x_uart0_init(); - orion5x_gpio_set_valid_pins(0x000000fb); + orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE, + RD88F5182_NOR_BOOT_SIZE); + + orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE); + platform_device_register(&rd88f5182_nor_flash); - platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices)); i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); - orion5x_eth_init(&rd88f5182_eth_data); - orion5x_sata_init(&rd88f5182_sata_data); } MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 9afb41ee6e0..a9cef9703d5 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -28,6 +28,8 @@ #include <asm/mach/pci.h> #include <asm/arch/orion5x.h> #include "common.h" +#include "mpp.h" +#include "tsx09-common.h" #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 #define QNAP_TS209_NOR_BOOT_SIZE SZ_8M @@ -47,52 +49,54 @@ ***************************************************************************/ static struct mtd_partition qnap_ts209_partitions[] = { { - .name = "U-Boot", - .size = 0x00080000, - .offset = 0x00780000, - .mask_flags = MTD_WRITEABLE, + .name = "U-Boot", + .size = 0x00080000, + .offset = 0x00780000, + .mask_flags = MTD_WRITEABLE, }, { - .name = "Kernel", - .size = 0x00200000, - .offset = 0, + .name = "Kernel", + .size = 0x00200000, + .offset = 0, }, { - .name = "RootFS1", - .size = 0x00400000, - .offset = 0x00200000, + .name = "RootFS1", + .size = 0x00400000, + .offset = 0x00200000, }, { - .name = "RootFS2", - .size = 0x00100000, - .offset = 0x00600000, + .name = "RootFS2", + .size = 0x00100000, + .offset = 0x00600000, }, { - .name = "U-Boot Config", - .size = 0x00020000, - .offset = 0x00760000, + .name = "U-Boot Config", + .size = 0x00020000, + .offset = 0x00760000, }, { - .name = "NAS Config", - .size = 0x00060000, - .offset = 0x00700000, - .mask_flags = MTD_WRITEABLE, - } + .name = "NAS Config", + .size = 0x00060000, + .offset = 0x00700000, + .mask_flags = MTD_WRITEABLE, + }, }; static struct physmap_flash_data qnap_ts209_nor_flash_data = { - .width = 1, - .parts = qnap_ts209_partitions, - .nr_parts = ARRAY_SIZE(qnap_ts209_partitions) + .width = 1, + .parts = qnap_ts209_partitions, + .nr_parts = ARRAY_SIZE(qnap_ts209_partitions) }; static struct resource qnap_ts209_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = QNAP_TS209_NOR_BOOT_BASE, - .end = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1, + .flags = IORESOURCE_MEM, + .start = QNAP_TS209_NOR_BOOT_BASE, + .end = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1, }; static struct platform_device qnap_ts209_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { .platform_data = &qnap_ts209_nor_flash_data, }, - .resource = &qnap_ts209_nor_flash_resource, - .num_resources = 1, + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &qnap_ts209_nor_flash_data, + }, + .resource = &qnap_ts209_nor_flash_resource, + .num_resources = 1, }; /***************************************************************************** @@ -164,12 +168,12 @@ static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) } static struct hw_pci qnap_ts209_pci __initdata = { - .nr_controllers = 2, - .preinit = qnap_ts209_pci_preinit, - .swizzle = pci_std_swizzle, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = qnap_ts209_pci_map_irq, + .nr_controllers = 2, + .preinit = qnap_ts209_pci_preinit, + .swizzle = pci_std_swizzle, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = qnap_ts209_pci_map_irq, }; static int __init qnap_ts209_pci_init(void) @@ -183,96 +187,6 @@ static int __init qnap_ts209_pci_init(void) subsys_initcall(qnap_ts209_pci_init); /***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data qnap_ts209_eth_data = { - .phy_addr = 8, - .force_phy_addr = 1, -}; - -static int __init parse_hex_nibble(char n) -{ - if (n >= '0' && n <= '9') - return n - '0'; - - if (n >= 'A' && n <= 'F') - return n - 'A' + 10; - - if (n >= 'a' && n <= 'f') - return n - 'a' + 10; - - return -1; -} - -static int __init parse_hex_byte(const char *b) -{ - int hi; - int lo; - - hi = parse_hex_nibble(b[0]); - lo = parse_hex_nibble(b[1]); - - if (hi < 0 || lo < 0) - return -1; - - return (hi << 4) | lo; -} - -static int __init check_mac_addr(const char *addr_str) -{ - u_int8_t addr[6]; - int i; - - for (i = 0; i < 6; i++) { - int byte; - - /* - * Enforce "xx:xx:xx:xx:xx:xx\n" format. - */ - if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n')) - return -1; - - byte = parse_hex_byte(addr_str + (i * 3)); - if (byte < 0) - return -1; - addr[i] = byte; - } - - printk(KERN_INFO "ts209: found ethernet mac address "); - for (i = 0; i < 6; i++) - printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n"); - - memcpy(qnap_ts209_eth_data.mac_addr, addr, 6); - - return 0; -} - -/* - * The 'NAS Config' flash partition has an ext2 filesystem which - * contains a file that has the ethernet MAC address in plain text - * (format "xx:xx:xx:xx:xx:xx\n".) - */ -static void __init ts209_find_mac_addr(void) -{ - unsigned long addr; - - for (addr = 0x00700000; addr < 0x00760000; addr += 1024) { - char *nor_page; - int ret = 0; - - nor_page = ioremap(QNAP_TS209_NOR_BOOT_BASE + addr, 1024); - if (nor_page != NULL) { - ret = check_mac_addr(nor_page); - iounmap(nor_page); - } - - if (ret == 0) - break; - } -} - -/***************************************************************************** * RTC S35390A on I2C bus ****************************************************************************/ @@ -280,7 +194,7 @@ static void __init ts209_find_mac_addr(void) static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = { I2C_BOARD_INFO("s35390a", 0x30), - .irq = 0, + .irq = 0, }; /**************************************************************************** @@ -297,70 +211,63 @@ static struct gpio_keys_button qnap_ts209_buttons[] = { .gpio = QNAP_TS209_GPIO_KEY_MEDIA, .desc = "USB Copy Button", .active_low = 1, - }, - { + }, { .code = KEY_POWER, .gpio = QNAP_TS209_GPIO_KEY_RESET, .desc = "Reset Button", .active_low = 1, - } + }, }; static struct gpio_keys_platform_data qnap_ts209_button_data = { .buttons = qnap_ts209_buttons, - .nbuttons = ARRAY_SIZE(qnap_ts209_buttons), + .nbuttons = ARRAY_SIZE(qnap_ts209_buttons), }; static struct platform_device qnap_ts209_button_device = { .name = "gpio-keys", .id = -1, .num_resources = 0, - .dev = { .platform_data = &qnap_ts209_button_data, }, + .dev = { + .platform_data = &qnap_ts209_button_data, + }, }; /***************************************************************************** * SATA ****************************************************************************/ static struct mv_sata_platform_data qnap_ts209_sata_data = { - .n_ports = 2, + .n_ports = 2, }; /***************************************************************************** * General Setup ****************************************************************************/ - -static struct platform_device *qnap_ts209_devices[] __initdata = { - &qnap_ts209_nor_flash, - &qnap_ts209_button_device, +static struct orion5x_mpp_mode ts209_mpp_modes[] __initdata = { + { 0, MPP_UNUSED }, + { 1, MPP_GPIO }, /* USB copy button */ + { 2, MPP_GPIO }, /* Load defaults button */ + { 3, MPP_GPIO }, /* GPIO RTC */ + { 4, MPP_UNUSED }, + { 5, MPP_UNUSED }, + { 6, MPP_GPIO }, /* PCI Int A */ + { 7, MPP_GPIO }, /* PCI Int B */ + { 8, MPP_UNUSED }, + { 9, MPP_UNUSED }, + { 10, MPP_UNUSED }, + { 11, MPP_UNUSED }, + { 12, MPP_SATA_LED }, /* SATA 0 presence */ + { 13, MPP_SATA_LED }, /* SATA 1 presence */ + { 14, MPP_SATA_LED }, /* SATA 0 active */ + { 15, MPP_SATA_LED }, /* SATA 1 active */ + { 16, MPP_UART }, /* UART1 RXD */ + { 17, MPP_UART }, /* UART1 TXD */ + { 18, MPP_GPIO }, /* SW_RST */ + { 19, MPP_UNUSED }, + { -1 }, }; -/* - * QNAP TS-[12]09 specific power off method via UART1-attached PIC - */ - -#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) - -static void qnap_ts209_power_off(void) -{ - /* 19200 baud divisor */ - const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200)); - - pr_info("%s: triggering power-off...\n", __func__); - - /* hijack uart1 and reset into sane state (19200,8n1) */ - orion5x_write(UART1_REG(LCR), 0x83); - orion5x_write(UART1_REG(DLL), divisor & 0xff); - orion5x_write(UART1_REG(DLM), (divisor >> 8) & 0xff); - orion5x_write(UART1_REG(LCR), 0x03); - orion5x_write(UART1_REG(IER), 0x00); - orion5x_write(UART1_REG(FCR), 0x00); - orion5x_write(UART1_REG(MCR), 0x00); - - /* send the power-off command 'A' to PIC */ - orion5x_write(UART1_REG(TX), 'A'); -} - static void __init qnap_ts209_init(void) { /* @@ -368,51 +275,33 @@ static void __init qnap_ts209_init(void) */ orion5x_init(); - /* - * Setup flash mapping - */ - orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, - QNAP_TS209_NOR_BOOT_SIZE); - - /* - * Open a special address decode windows for the PCIe WA. - */ - orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, - ORION5X_PCIE_WA_SIZE); + orion5x_mpp_conf(ts209_mpp_modes); /* - * Setup Multiplexing Pins -- - * MPP[0] Reserved - * MPP[1] USB copy button (0 active) - * MPP[2] Load defaults button (0 active) - * MPP[3] GPIO RTC - * MPP[4-5] Reserved - * MPP[6] PCI Int A - * MPP[7] PCI Int B - * MPP[8-11] Reserved - * MPP[12] SATA 0 presence - * MPP[13] SATA 1 presence - * MPP[14] SATA 0 active - * MPP[15] SATA 1 active - * MPP[16] UART1 RXD - * MPP[17] UART1 TXD - * MPP[18] SW_RST (0 active) - * MPP[19] Reserved * MPP[20] PCI clock 0 * MPP[21] PCI clock 1 * MPP[22] USB 0 over current * MPP[23-25] Reserved */ - orion5x_write(MPP_0_7_CTRL, 0x3); - orion5x_write(MPP_8_15_CTRL, 0x55550000); - orion5x_write(MPP_16_19_CTRL, 0x5500); - orion5x_gpio_set_valid_pins(0x3cc0fff); - /* register ts209 specific power-off method */ - pm_power_off = qnap_ts209_power_off; + /* + * Configure peripherals. + */ + orion5x_ehci0_init(); + orion5x_ehci1_init(); + qnap_tsx09_find_mac_addr(QNAP_TS209_NOR_BOOT_BASE + + qnap_ts209_partitions[5].offset, + qnap_ts209_partitions[5].size); + orion5x_eth_init(&qnap_tsx09_eth_data); + orion5x_i2c_init(); + orion5x_sata_init(&qnap_ts209_sata_data); + orion5x_uart0_init(); + + orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE, + QNAP_TS209_NOR_BOOT_SIZE); + platform_device_register(&qnap_ts209_nor_flash); - platform_add_devices(qnap_ts209_devices, - ARRAY_SIZE(qnap_ts209_devices)); + platform_device_register(&qnap_ts209_button_device); /* Get RTC IRQ and register the chip */ if (gpio_request(TS209_RTC_GPIO, "rtc") == 0) { @@ -425,14 +314,12 @@ static void __init qnap_ts209_init(void) pr_warning("qnap_ts209_init: failed to get RTC IRQ\n"); i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); - ts209_find_mac_addr(); - orion5x_eth_init(&qnap_ts209_eth_data); - - orion5x_sata_init(&qnap_ts209_sata_data); + /* register tsx09 specific power-off method */ + pm_power_off = qnap_tsx09_power_off; } MACHINE_START(TS209, "QNAP TS-109/TS-209") - /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ + /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ .phys_io = ORION5X_REGS_PHYS_BASE, .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, .boot_params = 0x00000100, diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c new file mode 100644 index 00000000000..32f0ff073b7 --- /dev/null +++ b/arch/arm/mach-orion5x/ts409-setup.c @@ -0,0 +1,273 @@ +/* + * QNAP TS-409 Board Setup + * + * Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pci.h> +#include <linux/irq.h> +#include <linux/mtd/physmap.h> +#include <linux/mv643xx_eth.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <linux/i2c.h> +#include <linux/serial_reg.h> +#include <asm/mach-types.h> +#include <asm/gpio.h> +#include <asm/mach/arch.h> +#include <asm/mach/pci.h> +#include <asm/arch/orion5x.h> +#include "common.h" +#include "mpp.h" +#include "tsx09-common.h" + +/***************************************************************************** + * QNAP TS-409 Info + ****************************************************************************/ + +/* + * QNAP TS-409 hardware : + * - Marvell 88F5281-D0 + * - Marvell 88SX7042 SATA controller (PCIe) + * - Marvell 88E1118 Gigabit Ethernet PHY + * - RTC S35390A (@0x30) on I2C bus + * - 8MB NOR flash + * - 256MB of DDR-2 RAM + */ + +/* + * 8MB NOR flash Device bus boot chip select + */ + +#define QNAP_TS409_NOR_BOOT_BASE 0xff800000 +#define QNAP_TS409_NOR_BOOT_SIZE SZ_8M + +/**************************************************************************** + * 8MiB NOR flash. The struct mtd_partition is not in the same order as the + * partitions on the device because we want to keep compatability with + * existing QNAP firmware. + * + * Layout as used by QNAP: + * [2] 0x00000000-0x00200000 : "Kernel" + * [3] 0x00200000-0x00600000 : "RootFS1" + * [4] 0x00600000-0x00700000 : "RootFS2" + * [6] 0x00700000-0x00760000 : "NAS Config" (read-only) + * [5] 0x00760000-0x00780000 : "U-Boot Config" + * [1] 0x00780000-0x00800000 : "U-Boot" (read-only) + ***************************************************************************/ +static struct mtd_partition qnap_ts409_partitions[] = { + { + .name = "U-Boot", + .size = 0x00080000, + .offset = 0x00780000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "Kernel", + .size = 0x00200000, + .offset = 0, + }, { + .name = "RootFS1", + .size = 0x00400000, + .offset = 0x00200000, + }, { + .name = "RootFS2", + .size = 0x00100000, + .offset = 0x00600000, + }, { + .name = "U-Boot Config", + .size = 0x00020000, + .offset = 0x00760000, + }, { + .name = "NAS Config", + .size = 0x00060000, + .offset = 0x00700000, + .mask_flags = MTD_WRITEABLE, + }, +}; + +static struct physmap_flash_data qnap_ts409_nor_flash_data = { + .width = 1, + .parts = qnap_ts409_partitions, + .nr_parts = ARRAY_SIZE(qnap_ts409_partitions) +}; + +static struct resource qnap_ts409_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = QNAP_TS409_NOR_BOOT_BASE, + .end = QNAP_TS409_NOR_BOOT_BASE + QNAP_TS409_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device qnap_ts409_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { .platform_data = &qnap_ts409_nor_flash_data, }, + .num_resources = 1, + .resource = &qnap_ts409_nor_flash_resource, +}; + +/***************************************************************************** + * PCI + ****************************************************************************/ + +static int __init qnap_ts409_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq; + + /* + * Check for devices with hard-wired IRQs. + */ + irq = orion5x_pci_map_irq(dev, slot, pin); + if (irq != -1) + return irq; + + /* + * PCI isn't used on the TS-409 + */ + return -1; +} + +static struct hw_pci qnap_ts409_pci __initdata = { + .nr_controllers = 2, + .swizzle = pci_std_swizzle, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = qnap_ts409_pci_map_irq, +}; + +static int __init qnap_ts409_pci_init(void) +{ + if (machine_is_ts409()) + pci_common_init(&qnap_ts409_pci); + + return 0; +} + +subsys_initcall(qnap_ts409_pci_init); + +/***************************************************************************** + * RTC S35390A on I2C bus + ****************************************************************************/ + +#define TS409_RTC_GPIO 10 + +static struct i2c_board_info __initdata qnap_ts409_i2c_rtc = { + I2C_BOARD_INFO("s35390a", 0x30), +}; + +/**************************************************************************** + * GPIO Attached Keys + * Power button is attached to the PIC microcontroller + ****************************************************************************/ + +#define QNAP_TS409_GPIO_KEY_MEDIA 15 + +static struct gpio_keys_button qnap_ts409_buttons[] = { + { + .code = KEY_RESTART, + .gpio = QNAP_TS409_GPIO_KEY_MEDIA, + .desc = "USB Copy Button", + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data qnap_ts409_button_data = { + .buttons = qnap_ts409_buttons, + .nbuttons = ARRAY_SIZE(qnap_ts409_buttons), +}; + +static struct platform_device qnap_ts409_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &qnap_ts409_button_data, + }, +}; + +/***************************************************************************** + * General Setup + ****************************************************************************/ +static struct orion5x_mpp_mode ts409_mpp_modes[] __initdata = { + { 0, MPP_UNUSED }, + { 1, MPP_UNUSED }, + { 2, MPP_UNUSED }, + { 3, MPP_UNUSED }, + { 4, MPP_GPIO }, /* HDD 1 status */ + { 5, MPP_GPIO }, /* HDD 2 status */ + { 6, MPP_GPIO }, /* HDD 3 status */ + { 7, MPP_GPIO }, /* HDD 4 status */ + { 8, MPP_UNUSED }, + { 9, MPP_UNUSED }, + { 10, MPP_GPIO }, /* RTC int */ + { 11, MPP_UNUSED }, + { 12, MPP_UNUSED }, + { 13, MPP_UNUSED }, + { 14, MPP_GPIO }, /* SW_RST */ + { 15, MPP_GPIO }, /* USB copy button */ + { 16, MPP_UART }, /* UART1 RXD */ + { 17, MPP_UART }, /* UART1 TXD */ + { 18, MPP_UNUSED }, + { 19, MPP_UNUSED }, + { -1 }, +}; + +static void __init qnap_ts409_init(void) +{ + /* + * Setup basic Orion functions. Need to be called early. + */ + orion5x_init(); + + orion5x_mpp_conf(ts409_mpp_modes); + + /* + * Configure peripherals. + */ + orion5x_ehci0_init(); + qnap_tsx09_find_mac_addr(QNAP_TS409_NOR_BOOT_BASE + + qnap_ts409_partitions[5].offset, + qnap_ts409_partitions[5].size); + orion5x_eth_init(&qnap_tsx09_eth_data); + orion5x_i2c_init(); + orion5x_uart0_init(); + + orion5x_setup_dev_boot_win(QNAP_TS409_NOR_BOOT_BASE, + QNAP_TS409_NOR_BOOT_SIZE); + platform_device_register(&qnap_ts409_nor_flash); + + platform_device_register(&qnap_ts409_button_device); + + /* Get RTC IRQ and register the chip */ + if (gpio_request(TS409_RTC_GPIO, "rtc") == 0) { + if (gpio_direction_input(TS409_RTC_GPIO) == 0) + qnap_ts409_i2c_rtc.irq = gpio_to_irq(TS409_RTC_GPIO); + else + gpio_free(TS409_RTC_GPIO); + } + if (qnap_ts409_i2c_rtc.irq == 0) + pr_warning("qnap_ts409_init: failed to get RTC IRQ\n"); + i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1); + + /* register tsx09 specific power-off method */ + pm_power_off = qnap_tsx09_power_off; +} + +MACHINE_START(TS409, "QNAP TS-409") + /* Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com> */ + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = qnap_ts409_init, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, + .fixup = tag_fixup_mem32, +MACHINE_END diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c new file mode 100644 index 00000000000..77e9f351f07 --- /dev/null +++ b/arch/arm/mach-orion5x/ts78xx-setup.c @@ -0,0 +1,277 @@ +/* + * arch/arm/mach-orion5x/ts78xx-setup.c + * + * Maintainer: Alexander Clouter <alex@digriz.org.uk> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> +#include <linux/mv643xx_eth.h> +#include <linux/ata_platform.h> +#include <linux/m48t86.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/arch/orion5x.h> +#include "common.h" +#include "mpp.h" + +/***************************************************************************** + * TS-78xx Info + ****************************************************************************/ + +/* + * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE + */ +#define TS78XX_FPGA_REGS_PHYS_BASE 0xe8000000 +#define TS78XX_FPGA_REGS_VIRT_BASE 0xff900000 +#define TS78XX_FPGA_REGS_SIZE SZ_1M + +#define TS78XX_FPGA_REGS_SYSCON_ID (TS78XX_FPGA_REGS_VIRT_BASE | 0x000) +#define TS78XX_FPGA_REGS_SYSCON_LCDI (TS78XX_FPGA_REGS_VIRT_BASE | 0x004) +#define TS78XX_FPGA_REGS_SYSCON_LCDO (TS78XX_FPGA_REGS_VIRT_BASE | 0x008) + +#define TS78XX_FPGA_REGS_RTC_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x808) +#define TS78XX_FPGA_REGS_RTC_DATA (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c) + +/* + * 512kB NOR flash Device + */ +#define TS78XX_NOR_BOOT_BASE 0xff800000 +#define TS78XX_NOR_BOOT_SIZE SZ_512K + +/***************************************************************************** + * I/O Address Mapping + ****************************************************************************/ +static struct map_desc ts78xx_io_desc[] __initdata = { + { + .virtual = TS78XX_FPGA_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE), + .length = TS78XX_FPGA_REGS_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init ts78xx_map_io(void) +{ + orion5x_map_io(); + iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc)); +} + +/***************************************************************************** + * 512kB NOR Boot Flash - the chip is a M25P40 + ****************************************************************************/ +static struct mtd_partition ts78xx_nor_boot_flash_resources[] = { + { + .name = "ts-bootrom", + .offset = 0, + /* only the first 256kB is used */ + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, + }, +}; + +static struct physmap_flash_data ts78xx_nor_boot_flash_data = { + .width = 1, + .parts = ts78xx_nor_boot_flash_resources, + .nr_parts = ARRAY_SIZE(ts78xx_nor_boot_flash_resources), +}; + +static struct resource ts78xx_nor_boot_flash_resource = { + .flags = IORESOURCE_MEM, + .start = TS78XX_NOR_BOOT_BASE, + .end = TS78XX_NOR_BOOT_BASE + TS78XX_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device ts78xx_nor_boot_flash = { + .name = "physmap-flash", + .id = -1, + .dev = { + .platform_data = &ts78xx_nor_boot_flash_data, + }, + .num_resources = 1, + .resource = &ts78xx_nor_boot_flash_resource, +}; + +/***************************************************************************** + * Ethernet + ****************************************************************************/ +static struct mv643xx_eth_platform_data ts78xx_eth_data = { + .phy_addr = 0, + .force_phy_addr = 1, +}; + +/***************************************************************************** + * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c + ****************************************************************************/ +#ifdef CONFIG_RTC_DRV_M48T86 +static unsigned char ts78xx_rtc_readbyte(unsigned long addr) +{ + writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL); + return readb(TS78XX_FPGA_REGS_RTC_DATA); +} + +static void ts78xx_rtc_writebyte(unsigned char value, unsigned long addr) +{ + writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL); + writeb(value, TS78XX_FPGA_REGS_RTC_DATA); +} + +static struct m48t86_ops ts78xx_rtc_ops = { + .readbyte = ts78xx_rtc_readbyte, + .writebyte = ts78xx_rtc_writebyte, +}; + +static struct platform_device ts78xx_rtc_device = { + .name = "rtc-m48t86", + .id = -1, + .dev = { + .platform_data = &ts78xx_rtc_ops, + }, + .num_resources = 0, +}; + +/* + * TS uses some of the user storage space on the RTC chip so see if it is + * present; as it's an optional feature at purchase time and not all boards + * will have it present + * + * I've used the method TS use in their rtc7800.c example for the detection + * + * TODO: track down a guinea pig without an RTC to see if we can work out a + * better RTC detection routine + */ +static int __init ts78xx_rtc_init(void) +{ + unsigned char tmp_rtc0, tmp_rtc1; + + tmp_rtc0 = ts78xx_rtc_readbyte(126); + tmp_rtc1 = ts78xx_rtc_readbyte(127); + + ts78xx_rtc_writebyte(0x00, 126); + ts78xx_rtc_writebyte(0x55, 127); + if (ts78xx_rtc_readbyte(127) == 0x55) { + ts78xx_rtc_writebyte(0xaa, 127); + if (ts78xx_rtc_readbyte(127) == 0xaa + && ts78xx_rtc_readbyte(126) == 0x00) { + ts78xx_rtc_writebyte(tmp_rtc0, 126); + ts78xx_rtc_writebyte(tmp_rtc1, 127); + platform_device_register(&ts78xx_rtc_device); + return 1; + } + } + + return 0; +}; +#else +static int __init ts78xx_rtc_init(void) +{ + return 0; +} +#endif + +/***************************************************************************** + * SATA + ****************************************************************************/ +static struct mv_sata_platform_data ts78xx_sata_data = { + .n_ports = 2, +}; + +/***************************************************************************** + * print some information regarding the board + ****************************************************************************/ +static void __init ts78xx_print_board_id(void) +{ + unsigned int board_info; + + board_info = readl(TS78XX_FPGA_REGS_SYSCON_ID); + printk(KERN_INFO "TS-78xx Info: FPGA rev=%.2x, Board Magic=%.6x, ", + board_info & 0xff, + (board_info >> 8) & 0xffffff); + board_info = readl(TS78XX_FPGA_REGS_SYSCON_LCDI); + printk("JP1=%d, JP2=%d\n", + (board_info >> 30) & 0x1, + (board_info >> 31) & 0x1); +}; + +/***************************************************************************** + * General Setup + ****************************************************************************/ +static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = { + { 0, MPP_UNUSED }, + { 1, MPP_GPIO }, /* JTAG Clock */ + { 2, MPP_GPIO }, /* JTAG Data In */ + { 3, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB2B */ + { 4, MPP_GPIO }, /* JTAG Data Out */ + { 5, MPP_GPIO }, /* JTAG TMS */ + { 6, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */ + { 7, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB22B */ + { 8, MPP_UNUSED }, + { 9, MPP_UNUSED }, + { 10, MPP_UNUSED }, + { 11, MPP_UNUSED }, + { 12, MPP_UNUSED }, + { 13, MPP_UNUSED }, + { 14, MPP_UNUSED }, + { 15, MPP_UNUSED }, + { 16, MPP_UART }, + { 17, MPP_UART }, + { 18, MPP_UART }, + { 19, MPP_UART }, + { -1 }, +}; + +static void __init ts78xx_init(void) +{ + /* + * Setup basic Orion functions. Need to be called early. + */ + orion5x_init(); + + ts78xx_print_board_id(); + + orion5x_mpp_conf(ts78xx_mpp_modes); + + /* + * MPP[20] PCI Clock Out 1 + * MPP[21] PCI Clock Out 0 + * MPP[22] Unused + * MPP[23] Unused + * MPP[24] Unused + * MPP[25] Unused + */ + + /* + * Configure peripherals. + */ + orion5x_ehci0_init(); + orion5x_ehci1_init(); + orion5x_eth_init(&ts78xx_eth_data); + orion5x_sata_init(&ts78xx_sata_data); + orion5x_uart0_init(); + orion5x_uart1_init(); + + orion5x_setup_dev_boot_win(TS78XX_NOR_BOOT_BASE, + TS78XX_NOR_BOOT_SIZE); + platform_device_register(&ts78xx_nor_boot_flash); + + if (!ts78xx_rtc_init()) + printk(KERN_INFO "TS-78xx RTC not detected or enabled\n"); +} + +MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC") + /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */ + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = ts78xx_init, + .map_io = ts78xx_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, +MACHINE_END diff --git a/arch/arm/mach-orion5x/tsx09-common.c b/arch/arm/mach-orion5x/tsx09-common.c new file mode 100644 index 00000000000..83feac3147a --- /dev/null +++ b/arch/arm/mach-orion5x/tsx09-common.c @@ -0,0 +1,133 @@ +/* + * QNAP TS-x09 Boards common functions + * + * Maintainers: Lennert Buytenhek <buytenh@marvell.com> + * Byron Bradley <byron.bbradley@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/mv643xx_eth.h> +#include <linux/timex.h> +#include <linux/serial_reg.h> +#include "tsx09-common.h" + +/***************************************************************************** + * QNAP TS-x09 specific power off method via UART1-attached PIC + ****************************************************************************/ + +#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) + +void qnap_tsx09_power_off(void) +{ + /* 19200 baud divisor */ + const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200)); + + pr_info("%s: triggering power-off...\n", __func__); + + /* hijack uart1 and reset into sane state (19200,8n1) */ + writel(0x83, UART1_REG(LCR)); + writel(divisor & 0xff, UART1_REG(DLL)); + writel((divisor >> 8) & 0xff, UART1_REG(DLM)); + writel(0x03, UART1_REG(LCR)); + writel(0x00, UART1_REG(IER)); + writel(0x00, UART1_REG(FCR)); + writel(0x00, UART1_REG(MCR)); + + /* send the power-off command 'A' to PIC */ + writel('A', UART1_REG(TX)); +} + +/***************************************************************************** + * Ethernet + ****************************************************************************/ + +struct mv643xx_eth_platform_data qnap_tsx09_eth_data = { + .phy_addr = 8, +}; + +static int __init qnap_tsx09_parse_hex_nibble(char n) +{ + if (n >= '0' && n <= '9') + return n - '0'; + + if (n >= 'A' && n <= 'F') + return n - 'A' + 10; + + if (n >= 'a' && n <= 'f') + return n - 'a' + 10; + + return -1; +} + +static int __init qnap_tsx09_parse_hex_byte(const char *b) +{ + int hi; + int lo; + + hi = qnap_tsx09_parse_hex_nibble(b[0]); + lo = qnap_tsx09_parse_hex_nibble(b[1]); + + if (hi < 0 || lo < 0) + return -1; + + return (hi << 4) | lo; +} + +static int __init qnap_tsx09_check_mac_addr(const char *addr_str) +{ + u_int8_t addr[6]; + int i; + + for (i = 0; i < 6; i++) { + int byte; + + /* + * Enforce "xx:xx:xx:xx:xx:xx\n" format. + */ + if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n')) + return -1; + + byte = qnap_tsx09_parse_hex_byte(addr_str + (i * 3)); + if (byte < 0) + return -1; + addr[i] = byte; + } + + printk(KERN_INFO "tsx09: found ethernet mac address "); + for (i = 0; i < 6; i++) + printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n"); + + memcpy(qnap_tsx09_eth_data.mac_addr, addr, 6); + + return 0; +} + +/* + * The 'NAS Config' flash partition has an ext2 filesystem which + * contains a file that has the ethernet MAC address in plain text + * (format "xx:xx:xx:xx:xx:xx\n"). + */ +void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size) +{ + unsigned long addr; + + for (addr = mem_base; addr < (mem_base + size); addr += 1024) { + char *nor_page; + int ret = 0; + + nor_page = ioremap(addr, 1024); + if (nor_page != NULL) { + ret = qnap_tsx09_check_mac_addr(nor_page); + iounmap(nor_page); + } + + if (ret == 0) + break; + } +} diff --git a/arch/arm/mach-orion5x/tsx09-common.h b/arch/arm/mach-orion5x/tsx09-common.h new file mode 100644 index 00000000000..0984264616f --- /dev/null +++ b/arch/arm/mach-orion5x/tsx09-common.h @@ -0,0 +1,20 @@ +#ifndef __ARCH_ORION5X_TSX09_COMMON_H +#define __ARCH_ORION5X_TSX09_COMMON_H + +/* + * QNAP TS-x09 Boards power-off function + */ +extern void qnap_tsx09_power_off(void); + +/* + * QNAP TS-x09 Boards function to find Ethernet MAC address in flash memory + */ +extern void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size); + +/* + * QNAP TS-x09 Boards ethernet declaration + */ +extern struct mv643xx_eth_platform_data qnap_tsx09_eth_data; + + +#endif diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c new file mode 100644 index 00000000000..aeab55c6a82 --- /dev/null +++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c @@ -0,0 +1,173 @@ +/* + * arch/arm/mach-orion5x/wrt350n-v2-setup.c + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pci.h> +#include <linux/irq.h> +#include <linux/delay.h> +#include <linux/mtd/physmap.h> +#include <linux/mv643xx_eth.h> +#include <asm/mach-types.h> +#include <asm/gpio.h> +#include <asm/mach/arch.h> +#include <asm/mach/pci.h> +#include <asm/arch/orion5x.h> +#include "common.h" +#include "mpp.h" + +static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = { + { 0, MPP_GPIO }, /* Power LED green (0=on) */ + { 1, MPP_GPIO }, /* Security LED (0=on) */ + { 2, MPP_GPIO }, /* Internal Button (0=on) */ + { 3, MPP_GPIO }, /* Reset Button (0=on) */ + { 4, MPP_GPIO }, /* PCI int */ + { 5, MPP_GPIO }, /* Power LED orange (0=on) */ + { 6, MPP_GPIO }, /* USB LED (0=on) */ + { 7, MPP_GPIO }, /* Wireless LED (0=on) */ + { 8, MPP_UNUSED }, /* ??? */ + { 9, MPP_GIGE }, /* GE_RXERR */ + { 10, MPP_UNUSED }, /* ??? */ + { 11, MPP_UNUSED }, /* ??? */ + { 12, MPP_GIGE }, /* GE_TXD[4] */ + { 13, MPP_GIGE }, /* GE_TXD[5] */ + { 14, MPP_GIGE }, /* GE_TXD[6] */ + { 15, MPP_GIGE }, /* GE_TXD[7] */ + { 16, MPP_GIGE }, /* GE_RXD[4] */ + { 17, MPP_GIGE }, /* GE_RXD[5] */ + { 18, MPP_GIGE }, /* GE_RXD[6] */ + { 19, MPP_GIGE }, /* GE_RXD[7] */ + { -1 }, +}; + +/* + * 8M NOR flash Device bus boot chip select + */ +#define WRT350N_V2_NOR_BOOT_BASE 0xf4000000 +#define WRT350N_V2_NOR_BOOT_SIZE SZ_8M + +static struct mtd_partition wrt350n_v2_nor_flash_partitions[] = { + { + .name = "kernel", + .offset = 0x00000000, + .size = 0x00760000, + }, { + .name = "rootfs", + .offset = 0x001a0000, + .size = 0x005c0000, + }, { + .name = "lang", + .offset = 0x00760000, + .size = 0x00040000, + }, { + .name = "nvram", + .offset = 0x007a0000, + .size = 0x00020000, + }, { + .name = "u-boot", + .offset = 0x007c0000, + .size = 0x00040000, + }, +}; + +static struct physmap_flash_data wrt350n_v2_nor_flash_data = { + .width = 1, + .parts = wrt350n_v2_nor_flash_partitions, + .nr_parts = ARRAY_SIZE(wrt350n_v2_nor_flash_partitions), +}; + +static struct resource wrt350n_v2_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = WRT350N_V2_NOR_BOOT_BASE, + .end = WRT350N_V2_NOR_BOOT_BASE + WRT350N_V2_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device wrt350n_v2_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &wrt350n_v2_nor_flash_data, + }, + .num_resources = 1, + .resource = &wrt350n_v2_nor_flash_resource, +}; + +static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = { + .phy_addr = -1, +}; + +static void __init wrt350n_v2_init(void) +{ + /* + * Setup basic Orion functions. Need to be called early. + */ + orion5x_init(); + + orion5x_mpp_conf(wrt350n_v2_mpp_modes); + + /* + * Configure peripherals. + */ + orion5x_ehci0_init(); + orion5x_eth_init(&wrt350n_v2_eth_data); + orion5x_uart0_init(); + + orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE, + WRT350N_V2_NOR_BOOT_SIZE); + platform_device_register(&wrt350n_v2_nor_flash); +} + +static int __init wrt350n_v2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq; + + /* + * Check for devices with hard-wired IRQs. + */ + irq = orion5x_pci_map_irq(dev, slot, pin); + if (irq != -1) + return irq; + + /* + * Mini-PCI slot. + */ + if (slot == 7) + return gpio_to_irq(4); + + return -1; +} + +static struct hw_pci wrt350n_v2_pci __initdata = { + .nr_controllers = 2, + .swizzle = pci_std_swizzle, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = wrt350n_v2_pci_map_irq, +}; + +static int __init wrt350n_v2_pci_init(void) +{ + if (machine_is_wrt350n_v2()) + pci_common_init(&wrt350n_v2_pci); + + return 0; +} +subsys_initcall(wrt350n_v2_pci_init); + +MACHINE_START(WRT350N_V2, "Linksys WRT350N v2") + /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = wrt350n_v2_init, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, + .fixup = tag_fixup_mem32, +MACHINE_END diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 33ed048502a..236603bbafd 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -365,7 +365,7 @@ config CPU_XSC3 # Feroceon config CPU_FEROCEON bool - depends on ARCH_ORION5X + depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD || ARCH_MV78XX0 default y select CPU_32v5 select CPU_ABRT_EV5T @@ -373,7 +373,7 @@ config CPU_FEROCEON select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_COPY_FEROCEON if MMU - select CPU_TLB_V4WBI if MMU + select CPU_TLB_FEROCEON if MMU config CPU_FEROCEON_OLD_ID bool "Accept early Feroceon cores with an ARM926 ID" @@ -551,6 +551,11 @@ config CPU_TLB_V4WBI ARM Architecture Version 4 TLB with writeback cache and invalidate instruction cache entry. +config CPU_TLB_FEROCEON + bool + help + Feroceon TLB (v4wbi with non-outer-cachable page table walks). + config CPU_TLB_V6 bool @@ -709,6 +714,14 @@ config OUTER_CACHE bool default n +config CACHE_FEROCEON_L2 + bool "Enable the Feroceon L2 cache controller" + depends on ARCH_KIRKWOOD || ARCH_MV78XX0 + default y + select OUTER_CACHE + help + This option enables the Feroceon L2 cache controller. + config CACHE_L2X0 bool "Enable the L2x0 outer cache controller" depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 32b2d2d213a..f64b92557b1 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o obj-$(CONFIG_CPU_TLB_V4WB) += tlb-v4wb.o obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o +obj-$(CONFIG_CPU_TLB_FEROCEON) += tlb-v4wbi.o # reuse v4wbi TLB functions obj-$(CONFIG_CPU_TLB_V6) += tlb-v6.o obj-$(CONFIG_CPU_TLB_V7) += tlb-v7.o @@ -73,4 +74,5 @@ obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o obj-$(CONFIG_CPU_V6) += proc-v6.o obj-$(CONFIG_CPU_V7) += proc-v7.o +obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c new file mode 100644 index 00000000000..20eec4ba173 --- /dev/null +++ b/arch/arm/mm/cache-feroceon-l2.c @@ -0,0 +1,318 @@ +/* + * arch/arm/mm/cache-feroceon-l2.c - Feroceon L2 cache controller support + * + * Copyright (C) 2008 Marvell Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * References: + * - Unified Layer 2 Cache for Feroceon CPU Cores, + * Document ID MV-S104858-00, Rev. A, October 23 2007. + */ + +#include <linux/init.h> +#include <asm/cacheflush.h> +#include <asm/plat-orion/cache-feroceon-l2.h> + + +/* + * Low-level cache maintenance operations. + * + * As well as the regular 'clean/invalidate/flush L2 cache line by + * MVA' instructions, the Feroceon L2 cache controller also features + * 'clean/invalidate L2 range by MVA' operations. + * + * Cache range operations are initiated by writing the start and + * end addresses to successive cp15 registers, and process every + * cache line whose first byte address lies in the inclusive range + * [start:end]. + * + * The cache range operations stall the CPU pipeline until completion. + * + * The range operations require two successive cp15 writes, in + * between which we don't want to be preempted. + */ +static inline void l2_clean_pa(unsigned long addr) +{ + __asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr)); +} + +static inline void l2_clean_mva_range(unsigned long start, unsigned long end) +{ + unsigned long flags; + + /* + * Make sure 'start' and 'end' reference the same page, as + * L2 is PIPT and range operations only do a TLB lookup on + * the start address. + */ + BUG_ON((start ^ end) & ~(PAGE_SIZE - 1)); + + raw_local_irq_save(flags); + __asm__("mcr p15, 1, %0, c15, c9, 4" : : "r" (start)); + __asm__("mcr p15, 1, %0, c15, c9, 5" : : "r" (end)); + raw_local_irq_restore(flags); +} + +static inline void l2_clean_pa_range(unsigned long start, unsigned long end) +{ + l2_clean_mva_range(__phys_to_virt(start), __phys_to_virt(end)); +} + +static inline void l2_clean_inv_pa(unsigned long addr) +{ + __asm__("mcr p15, 1, %0, c15, c10, 3" : : "r" (addr)); +} + +static inline void l2_inv_pa(unsigned long addr) +{ + __asm__("mcr p15, 1, %0, c15, c11, 3" : : "r" (addr)); +} + +static inline void l2_inv_mva_range(unsigned long start, unsigned long end) +{ + unsigned long flags; + + /* + * Make sure 'start' and 'end' reference the same page, as + * L2 is PIPT and range operations only do a TLB lookup on + * the start address. + */ + BUG_ON((start ^ end) & ~(PAGE_SIZE - 1)); + + raw_local_irq_save(flags); + __asm__("mcr p15, 1, %0, c15, c11, 4" : : "r" (start)); + __asm__("mcr p15, 1, %0, c15, c11, 5" : : "r" (end)); + raw_local_irq_restore(flags); +} + +static inline void l2_inv_pa_range(unsigned long start, unsigned long end) +{ + l2_inv_mva_range(__phys_to_virt(start), __phys_to_virt(end)); +} + + +/* + * Linux primitives. + * + * Note that the end addresses passed to Linux primitives are + * noninclusive, while the hardware cache range operations use + * inclusive start and end addresses. + */ +#define CACHE_LINE_SIZE 32 +#define MAX_RANGE_SIZE 1024 + +static int l2_wt_override; + +static unsigned long calc_range_end(unsigned long start, unsigned long end) +{ + unsigned long range_end; + + BUG_ON(start & (CACHE_LINE_SIZE - 1)); + BUG_ON(end & (CACHE_LINE_SIZE - 1)); + + /* + * Try to process all cache lines between 'start' and 'end'. + */ + range_end = end; + + /* + * Limit the number of cache lines processed at once, + * since cache range operations stall the CPU pipeline + * until completion. + */ + if (range_end > start + MAX_RANGE_SIZE) + range_end = start + MAX_RANGE_SIZE; + + /* + * Cache range operations can't straddle a page boundary. + */ + if (range_end > (start | (PAGE_SIZE - 1)) + 1) + range_end = (start | (PAGE_SIZE - 1)) + 1; + + return range_end; +} + +static void feroceon_l2_inv_range(unsigned long start, unsigned long end) +{ + /* + * Clean and invalidate partial first cache line. + */ + if (start & (CACHE_LINE_SIZE - 1)) { + l2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1)); + start = (start | (CACHE_LINE_SIZE - 1)) + 1; + } + + /* + * Clean and invalidate partial last cache line. + */ + if (end & (CACHE_LINE_SIZE - 1)) { + l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); + end &= ~(CACHE_LINE_SIZE - 1); + } + + /* + * Invalidate all full cache lines between 'start' and 'end'. + */ + while (start != end) { + unsigned long range_end = calc_range_end(start, end); + l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE); + start = range_end; + } + + dsb(); +} + +static void feroceon_l2_clean_range(unsigned long start, unsigned long end) +{ + /* + * If L2 is forced to WT, the L2 will always be clean and we + * don't need to do anything here. + */ + if (!l2_wt_override) { + start &= ~(CACHE_LINE_SIZE - 1); + end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1); + while (start != end) { + unsigned long range_end = calc_range_end(start, end); + l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE); + start = range_end; + } + } + + dsb(); +} + +static void feroceon_l2_flush_range(unsigned long start, unsigned long end) +{ + start &= ~(CACHE_LINE_SIZE - 1); + end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1); + while (start != end) { + unsigned long range_end = calc_range_end(start, end); + if (!l2_wt_override) + l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE); + l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE); + start = range_end; + } + + dsb(); +} + + +/* + * Routines to disable and re-enable the D-cache and I-cache at run + * time. These are necessary because the L2 cache can only be enabled + * or disabled while the L1 Dcache and Icache are both disabled. + */ +static void __init invalidate_and_disable_dcache(void) +{ + u32 cr; + + cr = get_cr(); + if (cr & CR_C) { + unsigned long flags; + + raw_local_irq_save(flags); + flush_cache_all(); + set_cr(cr & ~CR_C); + raw_local_irq_restore(flags); + } +} + +static void __init enable_dcache(void) +{ + u32 cr; + + cr = get_cr(); + if (!(cr & CR_C)) + set_cr(cr | CR_C); +} + +static void __init __invalidate_icache(void) +{ + int dummy; + + __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0\n" : "=r" (dummy)); +} + +static void __init invalidate_and_disable_icache(void) +{ + u32 cr; + + cr = get_cr(); + if (cr & CR_I) { + set_cr(cr & ~CR_I); + __invalidate_icache(); + } +} + +static void __init enable_icache(void) +{ + u32 cr; + + cr = get_cr(); + if (!(cr & CR_I)) + set_cr(cr | CR_I); +} + +static inline u32 read_extra_features(void) +{ + u32 u; + + __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u)); + + return u; +} + +static inline void write_extra_features(u32 u) +{ + __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u)); +} + +static void __init disable_l2_prefetch(void) +{ + u32 u; + + /* + * Read the CPU Extra Features register and verify that the + * Disable L2 Prefetch bit is set. + */ + u = read_extra_features(); + if (!(u & 0x01000000)) { + printk(KERN_INFO "Feroceon L2: Disabling L2 prefetch.\n"); + write_extra_features(u | 0x01000000); + } +} + +static void __init enable_l2(void) +{ + u32 u; + + u = read_extra_features(); + if (!(u & 0x00400000)) { + printk(KERN_INFO "Feroceon L2: Enabling L2\n"); + + invalidate_and_disable_dcache(); + invalidate_and_disable_icache(); + write_extra_features(u | 0x00400000); + enable_icache(); + enable_dcache(); + } +} + +void __init feroceon_l2_init(int __l2_wt_override) +{ + l2_wt_override = __l2_wt_override; + + disable_l2_prefetch(); + + outer_cache.inv_range = feroceon_l2_inv_range; + outer_cache.clean_range = feroceon_l2_clean_range; + outer_cache.flush_range = feroceon_l2_flush_range; + + enable_l2(); + + printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n", + l2_wt_override ? ", in WT override mode" : ""); +} diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index a02c1712b52..63ca1ea5c26 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -44,11 +44,31 @@ */ #define CACHE_DLINESIZE 32 + .bss + .align 3 +__cache_params_loc: + .space 8 + .text +__cache_params: + .word __cache_params_loc + /* * cpu_feroceon_proc_init() */ ENTRY(cpu_feroceon_proc_init) + mrc p15, 0, r0, c0, c0, 1 @ read cache type register + ldr r1, __cache_params + mov r2, #(16 << 5) + tst r0, #(1 << 16) @ get way + mov r0, r0, lsr #18 @ get cache size order + movne r3, #((4 - 1) << 30) @ 4-way + and r0, r0, #0xf + moveq r3, #0 @ 1-way + mov r2, r2, lsl r0 @ actual cache size + movne r2, r2, lsr #2 @ turned into # of sets + sub r2, r2, #(1 << 5) + stmia r1, {r2, r3} mov pc, lr /* @@ -59,6 +79,13 @@ ENTRY(cpu_feroceon_proc_fin) mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE msr cpsr_c, ip bl feroceon_flush_kern_cache_all + +#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH) + mov r0, #0 + mcr p15, 1, r0, c15, c9, 0 @ clean L2 + mcr p15, 0, r0, c7, c10, 4 @ drain WB +#endif + mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x000e @ ............wca. @@ -117,11 +144,19 @@ ENTRY(feroceon_flush_user_cache_all) */ ENTRY(feroceon_flush_kern_cache_all) mov r2, #VM_EXEC - mov ip, #0 + __flush_whole_cache: -1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate - bne 1b + ldr r1, __cache_params + ldmia r1, {r1, r3} +1: orr ip, r1, r3 +2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way + subs ip, ip, #(1 << 30) @ next way + bcs 2b + subs r1, r1, #(1 << 5) @ next set + bcs 1b + tst r2, #VM_EXEC + mov ip, #0 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache mcrne p15, 0, ip, c7, c10, 4 @ drain WB mov pc, lr @@ -138,7 +173,6 @@ __flush_whole_cache: */ .align 5 ENTRY(feroceon_flush_user_cache_range) - mov ip, #0 sub r3, r1, r0 @ calculate total size cmp r3, #CACHE_DLIMIT bgt __flush_whole_cache @@ -152,6 +186,7 @@ ENTRY(feroceon_flush_user_cache_range) cmp r0, r1 blo 1b tst r2, #VM_EXEC + mov ip, #0 mcrne p15, 0, ip, c7, c10, 4 @ drain WB mov pc, lr @@ -209,6 +244,20 @@ ENTRY(feroceon_flush_kern_dcache_page) mcr p15, 0, r0, c7, c10, 4 @ drain WB mov pc, lr + .align 5 +ENTRY(feroceon_range_flush_kern_dcache_page) + mrs r2, cpsr + add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive + orr r3, r2, #PSR_I_BIT + msr cpsr_c, r3 @ disable interrupts + mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start + mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top + msr cpsr_c, r2 @ restore interrupts + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + /* * dma_inv_range(start, end) * @@ -225,10 +274,10 @@ ENTRY(feroceon_flush_kern_dcache_page) .align 5 ENTRY(feroceon_dma_inv_range) tst r0, #CACHE_DLINESIZE - 1 + bic r0, r0, #CACHE_DLINESIZE - 1 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry tst r1, #CACHE_DLINESIZE - 1 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry - bic r0, r0, #CACHE_DLINESIZE - 1 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 @@ -236,6 +285,22 @@ ENTRY(feroceon_dma_inv_range) mcr p15, 0, r0, c7, c10, 4 @ drain WB mov pc, lr + .align 5 +ENTRY(feroceon_range_dma_inv_range) + mrs r2, cpsr + tst r0, #CACHE_DLINESIZE - 1 + mcrne p15, 0, r0, c7, c10, 1 @ clean D entry + tst r1, #CACHE_DLINESIZE - 1 + mcrne p15, 0, r1, c7, c10, 1 @ clean D entry + cmp r1, r0 + subne r1, r1, #1 @ top address is inclusive + orr r3, r2, #PSR_I_BIT + msr cpsr_c, r3 @ disable interrupts + mcr p15, 5, r0, c15, c14, 0 @ D inv range start + mcr p15, 5, r1, c15, c14, 1 @ D inv range top + msr cpsr_c, r2 @ restore interrupts + mov pc, lr + /* * dma_clean_range(start, end) * @@ -256,6 +321,19 @@ ENTRY(feroceon_dma_clean_range) mcr p15, 0, r0, c7, c10, 4 @ drain WB mov pc, lr + .align 5 +ENTRY(feroceon_range_dma_clean_range) + mrs r2, cpsr + cmp r1, r0 + subne r1, r1, #1 @ top address is inclusive + orr r3, r2, #PSR_I_BIT + msr cpsr_c, r3 @ disable interrupts + mcr p15, 5, r0, c15, c13, 0 @ D clean range start + mcr p15, 5, r1, c15, c13, 1 @ D clean range top + msr cpsr_c, r2 @ restore interrupts + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + /* * dma_flush_range(start, end) * @@ -274,6 +352,19 @@ ENTRY(feroceon_dma_flush_range) mcr p15, 0, r0, c7, c10, 4 @ drain WB mov pc, lr + .align 5 +ENTRY(feroceon_range_dma_flush_range) + mrs r2, cpsr + cmp r1, r0 + subne r1, r1, #1 @ top address is inclusive + orr r3, r2, #PSR_I_BIT + msr cpsr_c, r3 @ disable interrupts + mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start + mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top + msr cpsr_c, r2 @ restore interrupts + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mov pc, lr + ENTRY(feroceon_cache_fns) .long feroceon_flush_kern_cache_all .long feroceon_flush_user_cache_all @@ -285,12 +376,33 @@ ENTRY(feroceon_cache_fns) .long feroceon_dma_clean_range .long feroceon_dma_flush_range +ENTRY(feroceon_range_cache_fns) + .long feroceon_flush_kern_cache_all + .long feroceon_flush_user_cache_all + .long feroceon_flush_user_cache_range + .long feroceon_coherent_kern_range + .long feroceon_coherent_user_range + .long feroceon_range_flush_kern_dcache_page + .long feroceon_range_dma_inv_range + .long feroceon_range_dma_clean_range + .long feroceon_range_dma_flush_range + .align 5 ENTRY(cpu_feroceon_dcache_clean_area) +#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH) + mov r2, r0 + mov r3, r1 +#endif 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry add r0, r0, #CACHE_DLINESIZE subs r1, r1, #CACHE_DLINESIZE bhi 1b +#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH) +1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry + add r2, r2, #CACHE_DLINESIZE + subs r3, r3, #CACHE_DLINESIZE + bhi 1b +#endif mcr p15, 0, r0, c7, c10, 4 @ drain WB mov pc, lr @@ -306,16 +418,25 @@ ENTRY(cpu_feroceon_dcache_clean_area) .align 5 ENTRY(cpu_feroceon_switch_mm) #ifdef CONFIG_MMU - mov ip, #0 -@ && 'Clean & Invalidate whole DCache' -1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate - bne 1b - mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache - mcr p15, 0, ip, c7, c10, 4 @ drain WB + /* + * Note: we wish to call __flush_whole_cache but we need to preserve + * lr to do so. The only way without touching main memory is to + * use r2 which is normally used to test the VM_EXEC flag, and + * compensate locally for the skipped ops if it is not set. + */ + mov r2, lr @ abuse r2 to preserve lr + bl __flush_whole_cache + @ if r2 contains the VM_EXEC bit then the next 2 ops are done already + tst r2, #VM_EXEC + mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache + mcreq p15, 0, ip, c7, c10, 4 @ drain WB + mcr p15, 0, r0, c2, c0, 0 @ load page table pointer mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs -#endif + mov pc, r2 +#else mov pc, lr +#endif /* * cpu_feroceon_set_pte_ext(ptep, pte, ext) @@ -345,6 +466,9 @@ ENTRY(cpu_feroceon_set_pte_ext) str r2, [r0] @ hardware version mov r0, r0 mcr p15, 0, r0, c7, c10, 1 @ clean D entry +#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH) + mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry +#endif mcr p15, 0, r0, c7, c10, 4 @ drain WB #endif mov pc, lr @@ -414,6 +538,21 @@ cpu_feroceon_name: .asciz "Feroceon" .size cpu_feroceon_name, . - cpu_feroceon_name + .type cpu_88fr531_name, #object +cpu_88fr531_name: + .asciz "Feroceon 88FR531-vd" + .size cpu_88fr531_name, . - cpu_88fr531_name + + .type cpu_88fr571_name, #object +cpu_88fr571_name: + .asciz "Feroceon 88FR571-vd" + .size cpu_88fr571_name, . - cpu_88fr571_name + + .type cpu_88fr131_name, #object +cpu_88fr131_name: + .asciz "Feroceon 88FR131" + .size cpu_88fr131_name, . - cpu_88fr131_name + .align .section ".proc.info.init", #alloc, #execinstr @@ -421,15 +560,15 @@ cpu_feroceon_name: #ifdef CONFIG_CPU_FEROCEON_OLD_ID .type __feroceon_old_id_proc_info,#object __feroceon_old_id_proc_info: - .long 0x41069260 - .long 0xfffffff0 - .long PMD_TYPE_SECT | \ + .long 0x41009260 + .long 0xff00fff0 + .long PMD_TYPE_SECT | \ PMD_SECT_BUFFERABLE | \ PMD_SECT_CACHEABLE | \ PMD_BIT4 | \ PMD_SECT_AP_WRITE | \ PMD_SECT_AP_READ - .long PMD_TYPE_SECT | \ + .long PMD_TYPE_SECT | \ PMD_BIT4 | \ PMD_SECT_AP_WRITE | \ PMD_SECT_AP_READ @@ -445,17 +584,17 @@ __feroceon_old_id_proc_info: .size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info #endif - .type __feroceon_proc_info,#object -__feroceon_proc_info: + .type __88fr531_proc_info,#object +__88fr531_proc_info: .long 0x56055310 .long 0xfffffff0 - .long PMD_TYPE_SECT | \ + .long PMD_TYPE_SECT | \ PMD_SECT_BUFFERABLE | \ PMD_SECT_CACHEABLE | \ PMD_BIT4 | \ PMD_SECT_AP_WRITE | \ PMD_SECT_AP_READ - .long PMD_TYPE_SECT | \ + .long PMD_TYPE_SECT | \ PMD_BIT4 | \ PMD_SECT_AP_WRITE | \ PMD_SECT_AP_READ @@ -463,9 +602,59 @@ __feroceon_proc_info: .long cpu_arch_name .long cpu_elf_name .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP - .long cpu_feroceon_name + .long cpu_88fr531_name .long feroceon_processor_functions .long v4wbi_tlb_fns .long feroceon_user_fns .long feroceon_cache_fns - .size __feroceon_proc_info, . - __feroceon_proc_info + .size __88fr531_proc_info, . - __88fr531_proc_info + + .type __88fr571_proc_info,#object +__88fr571_proc_info: + .long 0x56155710 + .long 0xfffffff0 + .long PMD_TYPE_SECT | \ + PMD_SECT_BUFFERABLE | \ + PMD_SECT_CACHEABLE | \ + PMD_BIT4 | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ + .long PMD_TYPE_SECT | \ + PMD_BIT4 | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ + b __feroceon_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP + .long cpu_88fr571_name + .long feroceon_processor_functions + .long v4wbi_tlb_fns + .long feroceon_user_fns + .long feroceon_range_cache_fns + .size __88fr571_proc_info, . - __88fr571_proc_info + + .type __88fr131_proc_info,#object +__88fr131_proc_info: + .long 0x56251310 + .long 0xfffffff0 + .long PMD_TYPE_SECT | \ + PMD_SECT_BUFFERABLE | \ + PMD_SECT_CACHEABLE | \ + PMD_BIT4 | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ + .long PMD_TYPE_SECT | \ + PMD_BIT4 | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ + b __feroceon_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP + .long cpu_88fr131_name + .long feroceon_processor_functions + .long v4wbi_tlb_fns + .long feroceon_user_fns + .long feroceon_range_cache_fns + .size __88fr131_proc_info, . - __88fr131_proc_info diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c index c5b669d234b..fe66a183516 100644 --- a/arch/arm/plat-orion/irq.c +++ b/arch/arm/plat-orion/irq.c @@ -36,8 +36,8 @@ static void orion_irq_unmask(u32 irq) static struct irq_chip orion_irq_chip = { .name = "orion_irq", - .ack = orion_irq_mask, .mask = orion_irq_mask, + .mask_ack = orion_irq_mask, .unmask = orion_irq_unmask, }; @@ -59,6 +59,7 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) set_irq_chip(irq, &orion_irq_chip); set_irq_chip_data(irq, maskaddr); set_irq_handler(irq, handle_level_irq); + irq_desc[irq].status |= IRQ_LEVEL; set_irq_flags(irq, IRQF_VALID); } } diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c index abfda53f180..ca32c60e14d 100644 --- a/arch/arm/plat-orion/pcie.c +++ b/arch/arm/plat-orion/pcie.c @@ -39,6 +39,7 @@ #define PCIE_CONF_DATA_OFF 0x18fc #define PCIE_MASK_OFF 0x1910 #define PCIE_CTRL_OFF 0x1a00 +#define PCIE_CTRL_X1_MODE 0x0001 #define PCIE_STAT_OFF 0x1a04 #define PCIE_STAT_DEV_OFFS 20 #define PCIE_STAT_DEV_MASK 0x1f @@ -62,6 +63,11 @@ int orion_pcie_link_up(void __iomem *base) return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); } +int __init orion_pcie_x4_mode(void __iomem *base) +{ + return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE); +} + int orion_pcie_get_local_bus_nr(void __iomem *base) { u32 stat = readl(base + PCIE_STAT_OFF); diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 28b5285446e..93c4ef9f006 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c @@ -74,7 +74,7 @@ orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) /* * Clear and enable clockevent timer interrupt. */ - writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); + writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); u = readl(BRIDGE_MASK); u |= BRIDGE_INT_TIMER1; @@ -138,7 +138,7 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) /* * ACK pending timer interrupt. */ - writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); + writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); } local_irq_restore(flags); @@ -159,7 +159,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) /* * ACK timer interrupt and call event handler. */ - writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); + writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE); orion_clkevt.event_handler(&orion_clkevt); return IRQ_HANDLED; |