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-rw-r--r--arch/microblaze/kernel/cpu/Makefile8
-rw-r--r--arch/microblaze/kernel/cpu/cache.c258
-rw-r--r--arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c101
-rw-r--r--arch/microblaze/kernel/cpu/cpuinfo-static.c144
-rw-r--r--arch/microblaze/kernel/cpu/cpuinfo.c86
-rw-r--r--arch/microblaze/kernel/cpu/mb.c148
-rw-r--r--arch/microblaze/kernel/cpu/pvr.c81
7 files changed, 826 insertions, 0 deletions
diff --git a/arch/microblaze/kernel/cpu/Makefile b/arch/microblaze/kernel/cpu/Makefile
new file mode 100644
index 00000000000..20646e54927
--- /dev/null
+++ b/arch/microblaze/kernel/cpu/Makefile
@@ -0,0 +1,8 @@
+#
+# Build the appropriate CPU version support
+#
+
+EXTRA_CFLAGS += -DCPU_MAJOR=$(CPU_MAJOR) -DCPU_MINOR=$(CPU_MINOR) \
+ -DCPU_REV=$(CPU_REV)
+
+obj-y += cache.o cpuinfo.o cpuinfo-pvr-full.o cpuinfo-static.o mb.o pvr.o
diff --git a/arch/microblaze/kernel/cpu/cache.c b/arch/microblaze/kernel/cpu/cache.c
new file mode 100644
index 00000000000..be9fecca4f9
--- /dev/null
+++ b/arch/microblaze/kernel/cpu/cache.c
@@ -0,0 +1,258 @@
+/*
+ * Cache control for MicroBlaze cache memories
+ *
+ * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2007-2009 PetaLogix
+ * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file COPYING in the main directory of this
+ * archive for more details.
+ */
+
+#include <asm/cacheflush.h>
+#include <linux/cache.h>
+#include <asm/cpuinfo.h>
+
+/* Exported functions */
+
+void _enable_icache(void)
+{
+ if (cpuinfo.use_icache) {
+#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
+ __asm__ __volatile__ (" \
+ msrset r0, %0; \
+ nop; " \
+ : \
+ : "i" (MSR_ICE) \
+ : "memory");
+#else
+ __asm__ __volatile__ (" \
+ mfs r12, rmsr; \
+ nop; \
+ ori r12, r12, %0; \
+ mts rmsr, r12; \
+ nop; " \
+ : \
+ : "i" (MSR_ICE) \
+ : "memory", "r12");
+#endif
+ }
+}
+
+void _disable_icache(void)
+{
+ if (cpuinfo.use_icache) {
+#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
+ __asm__ __volatile__ (" \
+ msrclr r0, %0; \
+ nop; " \
+ : \
+ : "i" (MSR_ICE) \
+ : "memory");
+#else
+ __asm__ __volatile__ (" \
+ mfs r12, rmsr; \
+ nop; \
+ andi r12, r12, ~%0; \
+ mts rmsr, r12; \
+ nop; " \
+ : \
+ : "i" (MSR_ICE) \
+ : "memory", "r12");
+#endif
+ }
+}
+
+void _invalidate_icache(unsigned int addr)
+{
+ if (cpuinfo.use_icache) {
+ __asm__ __volatile__ (" \
+ wic %0, r0" \
+ : \
+ : "r" (addr));
+ }
+}
+
+void _enable_dcache(void)
+{
+ if (cpuinfo.use_dcache) {
+#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
+ __asm__ __volatile__ (" \
+ msrset r0, %0; \
+ nop; " \
+ : \
+ : "i" (MSR_DCE) \
+ : "memory");
+#else
+ __asm__ __volatile__ (" \
+ mfs r12, rmsr; \
+ nop; \
+ ori r12, r12, %0; \
+ mts rmsr, r12; \
+ nop; " \
+ : \
+ : "i" (MSR_DCE) \
+ : "memory", "r12");
+#endif
+ }
+}
+
+void _disable_dcache(void)
+{
+ if (cpuinfo.use_dcache) {
+#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
+ __asm__ __volatile__ (" \
+ msrclr r0, %0; \
+ nop; " \
+ : \
+ : "i" (MSR_DCE) \
+ : "memory");
+#else
+ __asm__ __volatile__ (" \
+ mfs r12, rmsr; \
+ nop; \
+ andi r12, r12, ~%0; \
+ mts rmsr, r12; \
+ nop; " \
+ : \
+ : "i" (MSR_DCE) \
+ : "memory", "r12");
+#endif
+ }
+}
+
+void _invalidate_dcache(unsigned int addr)
+{
+ if (cpuinfo.use_dcache)
+ __asm__ __volatile__ (" \
+ wdc %0, r0" \
+ : \
+ : "r" (addr));
+}
+
+void __invalidate_icache_all(void)
+{
+ unsigned int i;
+ unsigned flags;
+
+ if (cpuinfo.use_icache) {
+ local_irq_save(flags);
+ __disable_icache();
+
+ /* Just loop through cache size and invalidate, no need to add
+ CACHE_BASE address */
+ for (i = 0; i < cpuinfo.icache_size;
+ i += cpuinfo.icache_line)
+ __invalidate_icache(i);
+
+ __enable_icache();
+ local_irq_restore(flags);
+ }
+}
+
+void __invalidate_icache_range(unsigned long start, unsigned long end)
+{
+ unsigned int i;
+ unsigned flags;
+ unsigned int align;
+
+ if (cpuinfo.use_icache) {
+ /*
+ * No need to cover entire cache range,
+ * just cover cache footprint
+ */
+ end = min(start + cpuinfo.icache_size, end);
+ align = ~(cpuinfo.icache_line - 1);
+ start &= align; /* Make sure we are aligned */
+ /* Push end up to the next cache line */
+ end = ((end & align) + cpuinfo.icache_line);
+
+ local_irq_save(flags);
+ __disable_icache();
+
+ for (i = start; i < end; i += cpuinfo.icache_line)
+ __invalidate_icache(i);
+
+ __enable_icache();
+ local_irq_restore(flags);
+ }
+}
+
+void __invalidate_icache_page(struct vm_area_struct *vma, struct page *page)
+{
+ __invalidate_icache_all();
+}
+
+void __invalidate_icache_user_range(struct vm_area_struct *vma,
+ struct page *page, unsigned long adr,
+ int len)
+{
+ __invalidate_icache_all();
+}
+
+void __invalidate_cache_sigtramp(unsigned long addr)
+{
+ __invalidate_icache_range(addr, addr + 8);
+}
+
+void __invalidate_dcache_all(void)
+{
+ unsigned int i;
+ unsigned flags;
+
+ if (cpuinfo.use_dcache) {
+ local_irq_save(flags);
+ __disable_dcache();
+
+ /*
+ * Just loop through cache size and invalidate,
+ * no need to add CACHE_BASE address
+ */
+ for (i = 0; i < cpuinfo.dcache_size;
+ i += cpuinfo.dcache_line)
+ __invalidate_dcache(i);
+
+ __enable_dcache();
+ local_irq_restore(flags);
+ }
+}
+
+void __invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+ unsigned int i;
+ unsigned flags;
+ unsigned int align;
+
+ if (cpuinfo.use_dcache) {
+ /*
+ * No need to cover entire cache range,
+ * just cover cache footprint
+ */
+ end = min(start + cpuinfo.dcache_size, end);
+ align = ~(cpuinfo.dcache_line - 1);
+ start &= align; /* Make sure we are aligned */
+ /* Push end up to the next cache line */
+ end = ((end & align) + cpuinfo.dcache_line);
+ local_irq_save(flags);
+ __disable_dcache();
+
+ for (i = start; i < end; i += cpuinfo.dcache_line)
+ __invalidate_dcache(i);
+
+ __enable_dcache();
+ local_irq_restore(flags);
+ }
+}
+
+void __invalidate_dcache_page(struct vm_area_struct *vma, struct page *page)
+{
+ __invalidate_dcache_all();
+}
+
+void __invalidate_dcache_user_range(struct vm_area_struct *vma,
+ struct page *page, unsigned long adr,
+ int len)
+{
+ __invalidate_dcache_all();
+}
diff --git a/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c b/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
new file mode 100644
index 00000000000..cf7424a6bb8
--- /dev/null
+++ b/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
@@ -0,0 +1,101 @@
+/*
+ * Support for MicroBlaze PVR (processor version register)
+ *
+ * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2007-2009 PetaLogix
+ * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/string.h>
+#include <asm/pvr.h>
+#include <asm/cpuinfo.h>
+
+/*
+ * Helper macro to map between fields in our struct cpuinfo, and
+ * the PVR macros in pvr.h.
+ */
+
+#define CI(c, p) { ci->c = PVR_##p(pvr); }
+#define err_printk(x) \
+ early_printk("ERROR: Microblaze " x " - different for PVR and DTS\n");
+
+void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)
+{
+ struct pvr_s pvr;
+ int temp; /* for saving temp value */
+ get_pvr(&pvr);
+
+ temp = PVR_USE_BARREL(pvr) | PVR_USE_MSR_INSTR(pvr) |\
+ PVR_USE_PCMP_INSTR(pvr) | PVR_USE_DIV(pvr);
+ if (ci->use_instr != temp)
+ err_printk("BARREL, MSR, PCMP or DIV");
+ ci->use_instr = temp;
+
+ temp = PVR_USE_HW_MUL(pvr) | PVR_USE_MUL64(pvr);
+ if (ci->use_mult != temp)
+ err_printk("HW_MUL");
+ ci->use_mult = temp;
+
+ temp = PVR_USE_FPU(pvr) | PVR_USE_FPU2(pvr);
+ if (ci->use_fpu != temp)
+ err_printk("HW_FPU");
+ ci->use_fpu = temp;
+
+ ci->use_exc = PVR_OPCODE_0x0_ILLEGAL(pvr) |\
+ PVR_UNALIGNED_EXCEPTION(pvr) |\
+ PVR_ILL_OPCODE_EXCEPTION(pvr) |\
+ PVR_IOPB_BUS_EXCEPTION(pvr) |\
+ PVR_DOPB_BUS_EXCEPTION(pvr) |\
+ PVR_DIV_ZERO_EXCEPTION(pvr) |\
+ PVR_FPU_EXCEPTION(pvr) |\
+ PVR_FSL_EXCEPTION(pvr);
+
+ CI(pvr_user1, USER1);
+ CI(pvr_user2, USER2);
+
+ CI(mmu, USE_MMU);
+
+ CI(ver_code, VERSION);
+
+ CI(use_icache, USE_ICACHE);
+ CI(icache_tagbits, ICACHE_ADDR_TAG_BITS);
+ CI(icache_write, ICACHE_ALLOW_WR);
+ CI(icache_line, ICACHE_LINE_LEN);
+ CI(icache_size, ICACHE_BYTE_SIZE);
+ CI(icache_base, ICACHE_BASEADDR);
+ CI(icache_high, ICACHE_HIGHADDR);
+
+ CI(use_dcache, USE_DCACHE);
+ CI(dcache_tagbits, DCACHE_ADDR_TAG_BITS);
+ CI(dcache_write, DCACHE_ALLOW_WR);
+ CI(dcache_line, DCACHE_LINE_LEN);
+ CI(dcache_size, DCACHE_BYTE_SIZE);
+ CI(dcache_base, DCACHE_BASEADDR);
+ CI(dcache_high, DCACHE_HIGHADDR);
+
+ CI(use_dopb, D_OPB);
+ CI(use_iopb, I_OPB);
+ CI(use_dlmb, D_LMB);
+ CI(use_ilmb, I_LMB);
+ CI(num_fsl, FSL_LINKS);
+
+ CI(irq_edge, INTERRUPT_IS_EDGE);
+ CI(irq_positive, EDGE_IS_POSITIVE);
+
+ CI(area_optimised, AREA_OPTIMISED);
+
+ CI(hw_debug, DEBUG_ENABLED);
+ CI(num_pc_brk, NUMBER_OF_PC_BRK);
+ CI(num_rd_brk, NUMBER_OF_RD_ADDR_BRK);
+ CI(num_wr_brk, NUMBER_OF_WR_ADDR_BRK);
+
+ CI(fpga_family_code, TARGET_FAMILY);
+
+ /* take timebase-frequency from DTS */
+ ci->cpu_clock_freq = fcpu(cpu, "timebase-frequency");
+}
diff --git a/arch/microblaze/kernel/cpu/cpuinfo-static.c b/arch/microblaze/kernel/cpu/cpuinfo-static.c
new file mode 100644
index 00000000000..cfe44effdb7
--- /dev/null
+++ b/arch/microblaze/kernel/cpu/cpuinfo-static.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2007-2009 PetaLogix
+ * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <asm/cpuinfo.h>
+#include <asm/pvr.h>
+
+const static char family_string[] = CONFIG_XILINX_MICROBLAZE0_FAMILY;
+const static char cpu_ver_string[] = CONFIG_XILINX_MICROBLAZE0_HW_VER;
+
+#define err_printk(x) \
+ early_printk("ERROR: Microblaze " x "- different for kernel and DTS\n");
+
+void __init set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu)
+{
+ int i = 0;
+
+ ci->use_instr =
+ (fcpu(cpu, "xlnx,use-barrel") ? PVR0_USE_BARREL_MASK : 0) |
+ (fcpu(cpu, "xlnx,use-msr-instr") ? PVR2_USE_MSR_INSTR : 0) |
+ (fcpu(cpu, "xlnx,use-pcmp-instr") ? PVR2_USE_PCMP_INSTR : 0) |
+ (fcpu(cpu, "xlnx,use-div") ? PVR0_USE_DIV_MASK : 0);
+ if (CONFIG_XILINX_MICROBLAZE0_USE_BARREL)
+ i |= PVR0_USE_BARREL_MASK;
+ if (CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR)
+ i |= PVR2_USE_MSR_INSTR;
+ if (CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR)
+ i |= PVR2_USE_PCMP_INSTR;
+ if (CONFIG_XILINX_MICROBLAZE0_USE_DIV)
+ i |= PVR0_USE_DIV_MASK;
+ if (ci->use_instr != i)
+ err_printk("BARREL, MSR, PCMP or DIV");
+
+ ci->use_mult = fcpu(cpu, "xlnx,use-hw-mul");
+ if (ci->use_mult != CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)
+ err_printk("HW_MUL");
+ ci->use_mult =
+ (ci->use_mult > 1 ?
+ (PVR2_USE_MUL64_MASK | PVR0_USE_HW_MUL_MASK) :
+ (ci->use_mult == 1 ? PVR0_USE_HW_MUL_MASK : 0));
+
+ ci->use_fpu = fcpu(cpu, "xlnx,use-fpu");
+ if (ci->use_fpu != CONFIG_XILINX_MICROBLAZE0_USE_FPU)
+ err_printk("HW_FPU");
+ ci->use_fpu = (ci->use_fpu > 1 ?
+ (PVR2_USE_FPU2_MASK | PVR0_USE_FPU_MASK) :
+ (ci->use_fpu == 1 ? PVR0_USE_FPU_MASK : 0));
+
+ ci->use_exc =
+ (fcpu(cpu, "xlnx,unaligned-exceptions") ?
+ PVR2_UNALIGNED_EXC_MASK : 0) |
+ (fcpu(cpu, "xlnx,ill-opcode-exception") ?
+ PVR2_ILL_OPCODE_EXC_MASK : 0) |
+ (fcpu(cpu, "xlnx,iopb-bus-exception") ?
+ PVR2_IOPB_BUS_EXC_MASK : 0) |
+ (fcpu(cpu, "xlnx,dopb-bus-exception") ?
+ PVR2_DOPB_BUS_EXC_MASK : 0) |
+ (fcpu(cpu, "xlnx,div-zero-exception") ?
+ PVR2_DIV_ZERO_EXC_MASK : 0) |
+ (fcpu(cpu, "xlnx,fpu-exception") ? PVR2_FPU_EXC_MASK : 0) |
+ (fcpu(cpu, "xlnx,fsl-exception") ? PVR2_USE_EXTEND_FSL : 0);
+
+ ci->use_icache = fcpu(cpu, "xlnx,use-icache");
+ ci->icache_tagbits = fcpu(cpu, "xlnx,addr-tag-bits");
+ ci->icache_write = fcpu(cpu, "xlnx,allow-icache-wr");
+ ci->icache_line = fcpu(cpu, "xlnx,icache-line-len") << 2;
+ if (!ci->icache_line) {
+ if (fcpu(cpu, "xlnx,icache-use-fsl"))
+ ci->icache_line = 4 << 2;
+ else
+ ci->icache_line = 1 << 2;
+ }
+ ci->icache_size = fcpu(cpu, "i-cache-size");
+ ci->icache_base = fcpu(cpu, "i-cache-baseaddr");
+ ci->icache_high = fcpu(cpu, "i-cache-highaddr");
+
+ ci->use_dcache = fcpu(cpu, "xlnx,use-dcache");
+ ci->dcache_tagbits = fcpu(cpu, "xlnx,dcache-addr-tag");
+ ci->dcache_write = fcpu(cpu, "xlnx,allow-dcache-wr");
+ ci->dcache_line = fcpu(cpu, "xlnx,dcache-line-len") << 2;
+ if (!ci->dcache_line) {
+ if (fcpu(cpu, "xlnx,dcache-use-fsl"))
+ ci->dcache_line = 4 << 2;
+ else
+ ci->dcache_line = 1 << 2;
+ }
+ ci->dcache_size = fcpu(cpu, "d-cache-size");
+ ci->dcache_base = fcpu(cpu, "d-cache-baseaddr");
+ ci->dcache_high = fcpu(cpu, "d-cache-highaddr");
+
+ ci->use_dopb = fcpu(cpu, "xlnx,d-opb");
+ ci->use_iopb = fcpu(cpu, "xlnx,i-opb");
+ ci->use_dlmb = fcpu(cpu, "xlnx,d-lmb");
+ ci->use_ilmb = fcpu(cpu, "xlnx,i-lmb");
+
+ ci->num_fsl = fcpu(cpu, "xlnx,fsl-links");
+ ci->irq_edge = fcpu(cpu, "xlnx,interrupt-is-edge");
+ ci->irq_positive = fcpu(cpu, "xlnx,edge-is-positive");
+ ci->area_optimised = 0;
+
+ ci->hw_debug = fcpu(cpu, "xlnx,debug-enabled");
+ ci->num_pc_brk = fcpu(cpu, "xlnx,number-of-pc-brk");
+ ci->num_rd_brk = fcpu(cpu, "xlnx,number-of-rd-addr-brk");
+ ci->num_wr_brk = fcpu(cpu, "xlnx,number-of-wr-addr-brk");
+
+ ci->cpu_clock_freq = fcpu(cpu, "timebase-frequency");
+
+ ci->pvr_user1 = fcpu(cpu, "xlnx,pvr-user1");
+ ci->pvr_user2 = fcpu(cpu, "xlnx,pvr-user2");
+
+ ci->mmu = fcpu(cpu, "xlnx,use-mmu");
+
+ ci->ver_code = 0;
+ ci->fpga_family_code = 0;
+
+ /* Do various fixups based on CPU version and FPGA family strings */
+
+ /* Resolved the CPU version code */
+ for (i = 0; cpu_ver_lookup[i].s != NULL; i++) {
+ if (strcmp(cpu_ver_lookup[i].s, cpu_ver_string) == 0)
+ ci->ver_code = cpu_ver_lookup[i].k;
+ }
+
+ /* Resolved the fpga family code */
+ for (i = 0; family_string_lookup[i].s != NULL; i++) {
+ if (strcmp(family_string_lookup[i].s, family_string) == 0)
+ ci->fpga_family_code = family_string_lookup[i].k;
+ }
+
+ /* FIXME - mb3 and spartan2 do not exist in PVR */
+ /* This is mb3 and on a non Spartan2 */
+ if (ci->ver_code == 0x20 && ci->fpga_family_code != 0xf0)
+ /* Hardware Multiplier in use */
+ ci->use_mult = 1;
+}
diff --git a/arch/microblaze/kernel/cpu/cpuinfo.c b/arch/microblaze/kernel/cpu/cpuinfo.c
new file mode 100644
index 00000000000..4a740dfcf6d
--- /dev/null
+++ b/arch/microblaze/kernel/cpu/cpuinfo.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2007-2009 PetaLogix
+ * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <asm/cpuinfo.h>
+#include <asm/pvr.h>
+
+const struct cpu_ver_key cpu_ver_lookup[] = {
+ /* These key value are as per MBV field in PVR0 */
+ {"5.00.a", 0x01},
+ {"5.00.b", 0x02},
+ {"5.00.c", 0x03},
+ {"6.00.a", 0x04},
+ {"6.00.b", 0x06},
+ {"7.00.a", 0x05},
+ {"7.00.b", 0x07},
+ {"7.10.a", 0x08},
+ {"7.10.b", 0x09},
+ {"7.10.c", 0x0a},
+ {"7.10.d", 0x0b},
+ /* FIXME There is no keycode defined in MBV for these versions */
+ {"2.10.a", 0x10},
+ {"3.00.a", 0x20},
+ {"4.00.a", 0x30},
+ {"4.00.b", 0x40},
+ {NULL, 0},
+};
+
+/*
+ * FIXME Not sure if the actual key is defined by Xilinx in the PVR
+ */
+const struct family_string_key family_string_lookup[] = {
+ {"virtex2", 0x4},
+ {"virtex2pro", 0x5},
+ {"spartan3", 0x6},
+ {"virtex4", 0x7},
+ {"virtex5", 0x8},
+ {"spartan3e", 0x9},
+ {"spartan3a", 0xa},
+ {"spartan3an", 0xb},
+ {"spartan3adsp", 0xc},
+ /* FIXME There is no key code defined for spartan2 */
+ {"spartan2", 0xf0},
+ {NULL, 0},
+};
+
+struct cpuinfo cpuinfo;
+
+void __init setup_cpuinfo(void)
+{
+ struct device_node *cpu = NULL;
+
+ cpu = (struct device_node *) of_find_node_by_type(NULL, "cpu");
+ if (!cpu)
+ printk(KERN_ERR "You don't have cpu!!!\n");
+
+ printk(KERN_INFO "%s: initialising\n", __func__);
+
+ switch (cpu_has_pvr()) {
+ case 0:
+ printk(KERN_WARNING
+ "%s: No PVR support. Using static CPU info from FDT\n",
+ __func__);
+ set_cpuinfo_static(&cpuinfo, cpu);
+ break;
+/* FIXME I found weird behavior with MB 7.00.a/b
+ * please do not use FULL PVR with MMU */
+ case 1:
+ printk(KERN_INFO "%s: Using full CPU PVR support\n",
+ __func__);
+ set_cpuinfo_static(&cpuinfo, cpu);
+ set_cpuinfo_pvr_full(&cpuinfo, cpu);
+ break;
+ default:
+ printk(KERN_WARNING "%s: Unsupported PVR setting\n", __func__);
+ set_cpuinfo_static(&cpuinfo, cpu);
+ }
+}
diff --git a/arch/microblaze/kernel/cpu/mb.c b/arch/microblaze/kernel/cpu/mb.c
new file mode 100644
index 00000000000..3b6212bdc8d
--- /dev/null
+++ b/arch/microblaze/kernel/cpu/mb.c
@@ -0,0 +1,148 @@
+/*
+ * CPU-version specific code
+ *
+ * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2006-2009 PetaLogix
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/seq_file.h>
+#include <linux/cpu.h>
+#include <linux/initrd.h>
+
+#include <linux/bug.h>
+#include <asm/cpuinfo.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <asm/page.h>
+#include <linux/param.h>
+#include <asm/pvr.h>
+#include <asm/sections.h>
+#include <asm/setup.h>
+
+static int show_cpuinfo(struct seq_file *m, void *v)
+{
+ int count = 0;
+ char *fpga_family = "Unknown";
+ char *cpu_ver = "Unknown";
+ int i;
+
+ /* Denormalised to get the fpga family string */
+ for (i = 0; family_string_lookup[i].s != NULL; i++) {
+ if (cpuinfo.fpga_family_code == family_string_lookup[i].k) {
+ fpga_family = (char *)family_string_lookup[i].s;
+ break;
+ }
+ }
+
+ /* Denormalised to get the hw version string */
+ for (i = 0; cpu_ver_lookup[i].s != NULL; i++) {
+ if (cpuinfo.ver_code == cpu_ver_lookup[i].k) {
+ cpu_ver = (char *)cpu_ver_lookup[i].s;
+ break;
+ }
+ }
+
+ count = seq_printf(m,
+ "CPU-Family: MicroBlaze\n"
+ "FPGA-Arch: %s\n"
+ "CPU-Ver: %s\n"
+ "CPU-MHz: %d.%02d\n"
+ "BogoMips: %lu.%02lu\n",
+ fpga_family,
+ cpu_ver,
+ cpuinfo.cpu_clock_freq /
+ 1000000,
+ cpuinfo.cpu_clock_freq %
+ 1000000,
+ loops_per_jiffy / (500000 / HZ),
+ (loops_per_jiffy / (5000 / HZ)) % 100);
+
+ count += seq_printf(m,
+ "HW:\n Shift:\t\t%s\n"
+ " MSR:\t\t%s\n"
+ " PCMP:\t\t%s\n"
+ " DIV:\t\t%s\n",
+ (cpuinfo.use_instr & PVR0_USE_BARREL_MASK) ? "yes" : "no",
+ (cpuinfo.use_instr & PVR2_USE_MSR_INSTR) ? "yes" : "no",
+ (cpuinfo.use_instr & PVR2_USE_PCMP_INSTR) ? "yes" : "no",
+ (cpuinfo.use_instr & PVR0_USE_DIV_MASK) ? "yes" : "no");
+
+ count += seq_printf(m,
+ " MMU:\t\t%x\n",
+ cpuinfo.mmu);
+
+ count += seq_printf(m,
+ " MUL:\t\t%s\n"
+ " FPU:\t\t%s\n",
+ (cpuinfo.use_mult & PVR2_USE_MUL64_MASK) ? "v2" :
+ (cpuinfo.use_mult & PVR0_USE_HW_MUL_MASK) ? "v1" : "no",
+ (cpuinfo.use_fpu & PVR2_USE_FPU2_MASK) ? "v2" :
+ (cpuinfo.use_fpu & PVR0_USE_FPU_MASK) ? "v1" : "no");
+
+ count += seq_printf(m,
+ " Exc:\t\t%s%s%s%s%s%s%s%s\n",
+ (cpuinfo.use_exc & PVR2_OPCODE_0x0_ILL_MASK) ? "op0x0 " : "",
+ (cpuinfo.use_exc & PVR2_UNALIGNED_EXC_MASK) ? "unal " : "",
+ (cpuinfo.use_exc & PVR2_ILL_OPCODE_EXC_MASK) ? "ill " : "",
+ (cpuinfo.use_exc & PVR2_IOPB_BUS_EXC_MASK) ? "iopb " : "",
+ (cpuinfo.use_exc & PVR2_DOPB_BUS_EXC_MASK) ? "dopb " : "",
+ (cpuinfo.use_exc & PVR2_DIV_ZERO_EXC_MASK) ? "zero " : "",
+ (cpuinfo.use_exc & PVR2_FPU_EXC_MASK) ? "fpu " : "",
+ (cpuinfo.use_exc & PVR2_USE_FSL_EXC) ? "fsl " : "");
+
+ if (cpuinfo.use_icache)
+ count += seq_printf(m,
+ "Icache:\t\t%ukB\n",
+ cpuinfo.icache_size >> 10);
+ else
+ count += seq_printf(m, "Icache:\t\tno\n");
+
+ if (cpuinfo.use_dcache)
+ count += seq_printf(m,
+ "Dcache:\t\t%ukB\n",
+ cpuinfo.dcache_size >> 10);
+ else
+ count += seq_printf(m, "Dcache:\t\tno\n");
+
+ count += seq_printf(m,
+ "HW-Debug:\t%s\n",
+ cpuinfo.hw_debug ? "yes" : "no");
+
+ count += seq_printf(m,
+ "PVR-USR1:\t%x\n"
+ "PVR-USR2:\t%x\n",
+ cpuinfo.pvr_user1,
+ cpuinfo.pvr_user2);
+
+ return 0;
+}
+
+static void *c_start(struct seq_file *m, loff_t *pos)
+{
+ int i = *pos;
+
+ return i < NR_CPUS ? (void *) (i + 1) : NULL;
+}
+
+static void *c_next(struct seq_file *m, void *v, loff_t *pos)
+{
+ ++*pos;
+ return c_start(m, pos);
+}
+
+static void c_stop(struct seq_file *m, void *v)
+{
+}
+
+const struct seq_operations cpuinfo_op = {
+ .start = c_start,
+ .next = c_next,
+ .stop = c_stop,
+ .show = show_cpuinfo,
+};
diff --git a/arch/microblaze/kernel/cpu/pvr.c b/arch/microblaze/kernel/cpu/pvr.c
new file mode 100644
index 00000000000..c9a4340ddd5
--- /dev/null
+++ b/arch/microblaze/kernel/cpu/pvr.c
@@ -0,0 +1,81 @@
+/*
+ * Support for MicroBlaze PVR (processor version register)
+ *
+ * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2007-2009 PetaLogix
+ * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/compiler.h>
+#include <asm/system.h>
+#include <asm/exceptions.h>
+#include <asm/pvr.h>
+
+/*
+ * Until we get an assembler that knows about the pvr registers,
+ * this horrible cruft will have to do.
+ * That hardcoded opcode is mfs r3, rpvrNN
+ */
+
+#define get_single_pvr(pvrid, val) \
+{ \
+ register unsigned tmp __asm__("r3"); \
+ tmp = 0x0; /* Prevent warning about unused */ \
+ __asm__ __volatile__ ( \
+ ".byte 0x94,0x60,0xa0, " #pvrid "\n\t" \
+ : "=r" (tmp) : : "memory"); \
+ val = tmp; \
+}
+
+/*
+ * Does the CPU support the PVR register?
+ * return value:
+ * 0: no PVR
+ * 1: simple PVR
+ * 2: full PVR
+ *
+ * This must work on all CPU versions, including those before the
+ * PVR was even an option.
+ */
+
+int cpu_has_pvr(void)
+{
+ unsigned flags;
+ unsigned pvr0;
+
+ local_save_flags(flags);
+
+ /* PVR bit in MSR tells us if there is any support */
+ if (!(flags & PVR_MSR_BIT))
+ return 0;
+
+ get_single_pvr(0x00, pvr0);
+ pr_debug("%s: pvr0 is 0x%08x\n", __func__, pvr0);
+
+ if (pvr0 & PVR0_PVR_FULL_MASK)
+ return 1;
+
+ /* for partial PVR use static cpuinfo */
+ return 2;
+}
+
+void get_pvr(struct pvr_s *p)
+{
+ get_single_pvr(0, p->pvr[0]);
+ get_single_pvr(1, p->pvr[1]);
+ get_single_pvr(2, p->pvr[2]);
+ get_single_pvr(3, p->pvr[3]);
+ get_single_pvr(4, p->pvr[4]);
+ get_single_pvr(5, p->pvr[5]);
+ get_single_pvr(6, p->pvr[6]);
+ get_single_pvr(7, p->pvr[7]);
+ get_single_pvr(8, p->pvr[8]);
+ get_single_pvr(9, p->pvr[9]);
+ get_single_pvr(10, p->pvr[10]);
+ get_single_pvr(11, p->pvr[11]);
+}