diff options
Diffstat (limited to 'arch/mips/ddb5xxx/ddb5476')
| -rw-r--r-- | arch/mips/ddb5xxx/ddb5476/Makefile | 9 | ||||
| -rw-r--r-- | arch/mips/ddb5xxx/ddb5476/dbg_io.c | 136 | ||||
| -rw-r--r-- | arch/mips/ddb5xxx/ddb5476/int-handler.S | 112 | ||||
| -rw-r--r-- | arch/mips/ddb5xxx/ddb5476/irq.c | 143 | ||||
| -rw-r--r-- | arch/mips/ddb5xxx/ddb5476/nile4_pic.c | 190 | ||||
| -rw-r--r-- | arch/mips/ddb5xxx/ddb5476/setup.c | 297 | ||||
| -rw-r--r-- | arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c | 112 |
7 files changed, 999 insertions, 0 deletions
diff --git a/arch/mips/ddb5xxx/ddb5476/Makefile b/arch/mips/ddb5xxx/ddb5476/Makefile new file mode 100644 index 00000000000..61eec363cb0 --- /dev/null +++ b/arch/mips/ddb5xxx/ddb5476/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for the NEC DDB Vrc-5476 specific kernel interface routines +# under Linux. +# + +obj-y += setup.o irq.o int-handler.o nile4_pic.o vrc5476_irq.o +obj-$(CONFIG_KGDB) += dbg_io.o + +EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/ddb5xxx/ddb5476/dbg_io.c b/arch/mips/ddb5xxx/ddb5476/dbg_io.c new file mode 100644 index 00000000000..85e9e501367 --- /dev/null +++ b/arch/mips/ddb5xxx/ddb5476/dbg_io.c @@ -0,0 +1,136 @@ +/* + * kgdb io functions for DDB5476. We use the second serial port. + * + * Copyright (C) 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +/* ======================= CONFIG ======================== */ + +/* [jsun] we use the second serial port for kdb */ +#define BASE 0xa60002f8 +#define MAX_BAUD 115200 + +/* distance in bytes between two serial registers */ +#define REG_OFFSET 1 + +/* + * 0 - kgdb does serial init + * 1 - kgdb skip serial init + */ +static int remoteDebugInitialized = 0; + +/* + * the default baud rate *if* kgdb does serial init + */ +#define BAUD_DEFAULT UART16550_BAUD_38400 + +/* ======================= END OF CONFIG ======================== */ + +typedef unsigned char uint8; +typedef unsigned int uint32; + +#define UART16550_BAUD_2400 2400 +#define UART16550_BAUD_4800 4800 +#define UART16550_BAUD_9600 9600 +#define UART16550_BAUD_19200 19200 +#define UART16550_BAUD_38400 38400 +#define UART16550_BAUD_57600 57600 +#define UART16550_BAUD_115200 115200 + +#define UART16550_PARITY_NONE 0 +#define UART16550_PARITY_ODD 0x08 +#define UART16550_PARITY_EVEN 0x18 +#define UART16550_PARITY_MARK 0x28 +#define UART16550_PARITY_SPACE 0x38 + +#define UART16550_DATA_5BIT 0x0 +#define UART16550_DATA_6BIT 0x1 +#define UART16550_DATA_7BIT 0x2 +#define UART16550_DATA_8BIT 0x3 + +#define UART16550_STOP_1BIT 0x0 +#define UART16550_STOP_2BIT 0x4 + +/* register offset */ +#define OFS_RCV_BUFFER 0 +#define OFS_TRANS_HOLD 0 +#define OFS_SEND_BUFFER 0 +#define OFS_INTR_ENABLE (1*REG_OFFSET) +#define OFS_INTR_ID (2*REG_OFFSET) +#define OFS_DATA_FORMAT (3*REG_OFFSET) +#define OFS_LINE_CONTROL (3*REG_OFFSET) +#define OFS_MODEM_CONTROL (4*REG_OFFSET) +#define OFS_RS232_OUTPUT (4*REG_OFFSET) +#define OFS_LINE_STATUS (5*REG_OFFSET) +#define OFS_MODEM_STATUS (6*REG_OFFSET) +#define OFS_RS232_INPUT (6*REG_OFFSET) +#define OFS_SCRATCH_PAD (7*REG_OFFSET) + +#define OFS_DIVISOR_LSB (0*REG_OFFSET) +#define OFS_DIVISOR_MSB (1*REG_OFFSET) + + +/* memory-mapped read/write of the port */ +#define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) +#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) + +void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) +{ + /* disable interrupts */ + UART16550_WRITE(OFS_INTR_ENABLE, 0); + + /* set up buad rate */ + { + uint32 divisor; + + /* set DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x80); + + /* set divisor */ + divisor = MAX_BAUD / baud; + UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); + UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); + + /* clear DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x0); + } + + /* set data format */ + UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); +} + + +uint8 getDebugChar(void) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(BAUD_DEFAULT, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT); + } + + while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); + return UART16550_READ(OFS_RCV_BUFFER); +} + + +int putDebugChar(uint8 byte) +{ + if (!remoteDebugInitialized) { + remoteDebugInitialized = 1; + debugInit(BAUD_DEFAULT, + UART16550_DATA_8BIT, + UART16550_PARITY_NONE, UART16550_STOP_1BIT); + } + + while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); + UART16550_WRITE(OFS_SEND_BUFFER, byte); + return 1; +} diff --git a/arch/mips/ddb5xxx/ddb5476/int-handler.S b/arch/mips/ddb5xxx/ddb5476/int-handler.S new file mode 100644 index 00000000000..12c292e189b --- /dev/null +++ b/arch/mips/ddb5xxx/ddb5476/int-handler.S @@ -0,0 +1,112 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * First-level interrupt dispatcher for ddb5476 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include <asm/asm.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/regdef.h> +#include <asm/stackframe.h> + +#include <asm/ddb5xxx/ddb5476.h> + +/* + * first level interrupt dispatcher for ocelot board - + * We check for the timer first, then check PCI ints A and D. + * Then check for serial IRQ and fall through. + */ + .align 5 + NESTED(ddb5476_handle_int, PT_SIZE, sp) + SAVE_ALL + CLI + .set at + .set noreorder + mfc0 t0, CP0_CAUSE + mfc0 t2, CP0_STATUS + + and t0, t2 + + andi t1, t0, STATUSF_IP7 /* cpu timer */ + bnez t1, ll_cpu_ip7 + andi t1, t0, STATUSF_IP2 /* vrc5476 & i8259 */ + bnez t1, ll_cpu_ip2 + andi t1, t0, STATUSF_IP3 + bnez t1, ll_cpu_ip3 + andi t1, t0, STATUSF_IP4 + bnez t1, ll_cpu_ip4 + andi t1, t0, STATUSF_IP5 + bnez t1, ll_cpu_ip5 + andi t1, t0, STATUSF_IP6 + bnez t1, ll_cpu_ip6 + andi t1, t0, STATUSF_IP0 /* software int 0 */ + bnez t1, ll_cpu_ip0 + andi t1, t0, STATUSF_IP1 /* software int 1 */ + bnez t1, ll_cpu_ip1 + nop + + .set reorder + + /* wrong alarm or masked ... */ + // j spurious_interrupt + move a0, sp + jal vrc5476_irq_dispatch + j ret_from_irq + nop + + .align 5 + +ll_cpu_ip0: + li a0, CPU_IRQ_BASE + 0 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cpu_ip1: + li a0, CPU_IRQ_BASE + 1 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cpu_ip2: /* jump to second-level dispatching */ + move a0, sp + jal vrc5476_irq_dispatch + j ret_from_irq + +ll_cpu_ip3: + li a0, CPU_IRQ_BASE + 3 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cpu_ip4: + li a0, CPU_IRQ_BASE + 4 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cpu_ip5: + li a0, CPU_IRQ_BASE + 5 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cpu_ip6: + li a0, CPU_IRQ_BASE + 6 + move a1, sp + jal do_IRQ + j ret_from_irq + +ll_cpu_ip7: + li a0, CPU_IRQ_BASE + 7 + move a1, sp + jal do_IRQ + j ret_from_irq + + END(ddb5476_handle_int) diff --git a/arch/mips/ddb5xxx/ddb5476/irq.c b/arch/mips/ddb5xxx/ddb5476/irq.c new file mode 100644 index 00000000000..5388b5868c4 --- /dev/null +++ b/arch/mips/ddb5xxx/ddb5476/irq.c @@ -0,0 +1,143 @@ +/* + * arch/mips/ddb5476/irq.c -- NEC DDB Vrc-5476 interrupt routines + * + * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> + * Sony Software Development Center Europe (SDCE), Brussels + * + * Re-write the whole thing to use new irq.c file. + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + */ +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/types.h> +#include <linux/interrupt.h> + +#include <asm/i8259.h> +#include <asm/io.h> +#include <asm/ptrace.h> + +#include <asm/ddb5xxx/ddb5xxx.h> + +#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */ +#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */ +#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */ + +#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */ +#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */ +#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */ + +#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */ +#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */ + +#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */ +#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */ + +#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */ +#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */ + +static void m1543_irq_setup(void) +{ + /* + * The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all + * the possible IO sources in the M1543 are in use by us. We will + * use the following mapping: + * + * IRQ1 - keyboard (default set by M1543) + * IRQ3 - reserved for UART B (default set by M1543) (note that + * the schematics for the DDB Vrc-5476 board seem to + * indicate that IRQ3 is connected to the DS1386 + * watchdog timer interrupt output so we might have + * a conflict) + * IRQ4 - reserved for UART A (default set by M1543) + * IRQ5 - parallel (default set by M1543) + * IRQ8 - DS1386 time of day (RTC) interrupt + * IRQ9 - USB (hardwired in ddb_setup) + * IRQ10 - PMU (hardwired in ddb_setup) + * IRQ12 - mouse + * IRQ14,15 - IDE controller (need to be confirmed, jsun) + */ + + /* + * Assing mouse interrupt to IRQ12 + */ + + /* Enter configuration mode */ + outb(0x51, M1543_PNP_CONFIG); + outb(0x23, M1543_PNP_CONFIG); + + /* Select logical device 7 (Keyboard) */ + outb(0x07, M1543_PNP_INDEX); + outb(0x07, M1543_PNP_DATA); + + /* Select IRQ12 */ + outb(0x72, M1543_PNP_INDEX); + outb(0x0c, M1543_PNP_DATA); + + /* Leave configration mode */ + outb(0xbb, M1543_PNP_CONFIG); +} + +static void nile4_irq_setup(void) +{ + int i; + + /* Map all interrupts to CPU int #0 (IP2) */ + nile4_map_irq_all(0); + + /* PCI INTA#-E# must be level triggered */ + nile4_set_pci_irq_level_or_edge(0, 1); + nile4_set_pci_irq_level_or_edge(1, 1); + nile4_set_pci_irq_level_or_edge(2, 1); + nile4_set_pci_irq_level_or_edge(3, 1); + + /* PCI INTA#, B#, D# must be active low, INTC# must be active high */ + nile4_set_pci_irq_polarity(0, 0); + nile4_set_pci_irq_polarity(1, 0); + nile4_set_pci_irq_polarity(2, 1); + nile4_set_pci_irq_polarity(3, 0); + + for (i = 0; i < 16; i++) + nile4_clear_irq(i); + + /* Enable CPU int #0 */ + nile4_enable_irq_output(0); + + /* memory resource acquire in ddb_setup */ +} + +static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; +static struct irqaction irq_error = { no_action, 0, CPU_MASK_NONE, "error", NULL, NULL }; + +extern asmlinkage void ddb5476_handle_int(void); +extern int setup_irq(unsigned int irq, struct irqaction *irqaction); +extern void mips_cpu_irq_init(u32 irq_base); +extern void vrc5476_irq_init(u32 irq_base); + +void __init arch_init_irq(void) +{ + /* hardware initialization */ + nile4_irq_setup(); + m1543_irq_setup(); + + /* controller setup */ + init_i8259_irqs(); + vrc5476_irq_init(VRC5476_IRQ_BASE); + mips_cpu_irq_init(CPU_IRQ_BASE); + + /* setup cascade interrupts */ + setup_irq(VRC5476_IRQ_BASE + VRC5476_I8259_CASCADE, &irq_cascade); + setup_irq(CPU_IRQ_BASE + CPU_VRC5476_CASCADE, &irq_cascade); + + /* setup error interrupts for debugging */ + setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CPCE, &irq_error); + setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CNTD, &irq_error); + setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_MCE, &irq_error); + setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_LBRT, &irq_error); + setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCIS, &irq_error); + setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCI, &irq_error); + + /* setup the grandpa intr vector */ + set_except_vector(0, ddb5476_handle_int); +} diff --git a/arch/mips/ddb5xxx/ddb5476/nile4_pic.c b/arch/mips/ddb5xxx/ddb5476/nile4_pic.c new file mode 100644 index 00000000000..e930cee7944 --- /dev/null +++ b/arch/mips/ddb5xxx/ddb5476/nile4_pic.c @@ -0,0 +1,190 @@ +/* + * arch/mips/ddb5476/nile4.c -- + * low-level PIC code for NEC Vrc-5476 (Nile 4) + * + * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> + * Sony Software Development Center Europe (SDCE), Brussels + * + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + */ +#include <linux/config.h> +#include <linux/kernel.h> +#include <linux/types.h> + +#include <asm/addrspace.h> + +#include <asm/ddb5xxx/ddb5xxx.h> + + +/* + * Interrupt Programming + */ +void nile4_map_irq(int nile4_irq, int cpu_irq) +{ + u32 offset, t; + + offset = DDB_INTCTRL; + if (nile4_irq >= 8) { + offset += 4; + nile4_irq -= 8; + } + t = ddb_in32(offset); + t &= ~(7 << (nile4_irq * 4)); + t |= cpu_irq << (nile4_irq * 4); + ddb_out32(offset, t); +} + +void nile4_map_irq_all(int cpu_irq) +{ + u32 all, t; + + all = cpu_irq; + all |= all << 4; + all |= all << 8; + all |= all << 16; + t = ddb_in32(DDB_INTCTRL); + t &= 0x88888888; + t |= all; + ddb_out32(DDB_INTCTRL, t); + t = ddb_in32(DDB_INTCTRL + 4); + t &= 0x88888888; + t |= all; + ddb_out32(DDB_INTCTRL + 4, t); +} + +void nile4_enable_irq(int nile4_irq) +{ + u32 offset, t; + + offset = DDB_INTCTRL; + if (nile4_irq >= 8) { + offset += 4; + nile4_irq -= 8; + } + t = ddb_in32(offset); + t |= 8 << (nile4_irq * 4); + ddb_out32(offset, t); +} + +void nile4_disable_irq(int nile4_irq) +{ + u32 offset, t; + + offset = DDB_INTCTRL; + if (nile4_irq >= 8) { + offset += 4; + nile4_irq -= 8; + } + t = ddb_in32(offset); + t &= ~(8 << (nile4_irq * 4)); + ddb_out32(offset, t); +} + +void nile4_disable_irq_all(void) +{ + ddb_out32(DDB_INTCTRL, 0); + ddb_out32(DDB_INTCTRL + 4, 0); +} + +u16 nile4_get_irq_stat(int cpu_irq) +{ + return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2); +} + +void nile4_enable_irq_output(int cpu_irq) +{ + u32 t; + + t = ddb_in32(DDB_INTSTAT1 + 4); + t |= 1 << (16 + cpu_irq); + ddb_out32(DDB_INTSTAT1, t); +} + +void nile4_disable_irq_output(int cpu_irq) +{ + u32 t; + + t = ddb_in32(DDB_INTSTAT1 + 4); + t &= ~(1 << (16 + cpu_irq)); + ddb_out32(DDB_INTSTAT1, t); +} + +void nile4_set_pci_irq_polarity(int pci_irq, int high) +{ + u32 t; + + t = ddb_in32(DDB_INTPPES); + if (high) + t &= ~(1 << (pci_irq * 2)); + else + t |= 1 << (pci_irq * 2); + ddb_out32(DDB_INTPPES, t); +} + +void nile4_set_pci_irq_level_or_edge(int pci_irq, int level) +{ + u32 t; + + t = ddb_in32(DDB_INTPPES); + if (level) + t |= 2 << (pci_irq * 2); + else + t &= ~(2 << (pci_irq * 2)); + ddb_out32(DDB_INTPPES, t); +} + +void nile4_clear_irq(int nile4_irq) +{ + ddb_out32(DDB_INTCLR, 1 << nile4_irq); +} + +void nile4_clear_irq_mask(u32 mask) +{ + ddb_out32(DDB_INTCLR, mask); +} + +u8 nile4_i8259_iack(void) +{ + u8 irq; + u32 reg; + + /* Set window 0 for interrupt acknowledge */ + reg = ddb_in32(DDB_PCIINIT0); + + ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32); + irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE); + /* restore window 0 for PCI I/O space */ + // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32); + ddb_out32(DDB_PCIINIT0, reg); + + /* i8269.c set the base vector to be 0x0 */ + return irq + I8259_IRQ_BASE; +} + +#if defined(CONFIG_RUNTIME_DEBUG) +void nile4_dump_irq_status(void) +{ + printk(KERN_DEBUG " + CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4), + (void *) ddb_in32(DDB_CPUSTAT)); + printk(KERN_DEBUG " + INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4), + (void *) ddb_in32(DDB_INTCTRL)); + printk(KERN_DEBUG + "INTSTAT0 = %p:%p\n", + (void *) ddb_in32(DDB_INTSTAT0 + 4), + (void *) ddb_in32(DDB_INTSTAT0)); + printk(KERN_DEBUG + "INTSTAT1 = %p:%p\n", + (void *) ddb_in32(DDB_INTSTAT1 + 4), + (void *) ddb_in32(DDB_INTSTAT1)); + printk(KERN_DEBUG + "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4), + (void *) ddb_in32(DDB_INTCLR)); + printk(KERN_DEBUG + "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4), + (void *) ddb_in32(DDB_INTPPES)); +} +#endif diff --git a/arch/mips/ddb5xxx/ddb5476/setup.c b/arch/mips/ddb5xxx/ddb5476/setup.c new file mode 100644 index 00000000000..71531f8146e --- /dev/null +++ b/arch/mips/ddb5xxx/ddb5476/setup.c @@ -0,0 +1,297 @@ +/* + * arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines + * + * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> + * Sony Software Development Center Europe (SDCE), Brussels + */ +#include <linux/init.h> +#include <linux/kbd_ll.h> +#include <linux/kernel.h> +#include <linux/kdev_t.h> +#include <linux/types.h> +#include <linux/sched.h> +#include <linux/pci.h> + +#include <asm/addrspace.h> +#include <asm/bcache.h> +#include <asm/irq.h> +#include <asm/reboot.h> +#include <asm/gdb-stub.h> +#include <asm/time.h> +#include <asm/debug.h> +#include <asm/traps.h> + +#include <asm/ddb5xxx/ddb5xxx.h> + +// #define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */ + +#ifdef USE_CPU_COUNTER_TIMER + +#define CPU_COUNTER_FREQUENCY 83000000 +#else +/* otherwise we use general purpose timer */ +#define TIMER_FREQUENCY 83000000 +#define TIMER_BASE DDB_T2CTRL +#define TIMER_IRQ (VRC5476_IRQ_BASE + VRC5476_IRQ_GPT) +#endif + +static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000; + +static void ddb_machine_restart(char *command) +{ + u32 t; + + /* PCI cold reset */ + t = ddb_in32(DDB_PCICTRL + 4); + t |= 0x40000000; + ddb_out32(DDB_PCICTRL + 4, t); + /* CPU cold reset */ + t = ddb_in32(DDB_CPUSTAT); + t |= 1; + ddb_out32(DDB_CPUSTAT, t); + /* Call the PROM */ + back_to_prom(); +} + +static void ddb_machine_halt(void) +{ + printk(KERN_NOTICE "DDB Vrc-5476 halted.\n"); + while (1); +} + +static void ddb_machine_power_off(void) +{ + printk(KERN_NOTICE "DDB Vrc-5476 halted. Please turn off the power.\n"); + while (1); +} + +extern void rtc_ds1386_init(unsigned long base); + +static void __init ddb_time_init(void) +{ +#if defined(USE_CPU_COUNTER_TIMER) + mips_hpt_frequency = CPU_COUNTER_FREQUENCY; +#endif + + /* we have ds1396 RTC chip */ + rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE)); +} + + +extern int setup_irq(unsigned int irq, struct irqaction *irqaction); +static void __init ddb_timer_setup(struct irqaction *irq) +{ +#if defined(USE_CPU_COUNTER_TIMER) + + unsigned int count; + + /* we are using the cpu counter for timer interrupts */ + setup_irq(CPU_IRQ_BASE + 7, irq); + + /* to generate the first timer interrupt */ + count = read_c0_count(); + write_c0_compare(count + 1000); + +#else + + ddb_out32(TIMER_BASE, TIMER_FREQUENCY/HZ); + ddb_out32(TIMER_BASE+4, 0x1); /* enable timer */ + setup_irq(TIMER_IRQ, irq); +#endif +} + +static struct { + struct resource dma1; + struct resource timer; + struct resource rtc; + struct resource dma_page_reg; + struct resource dma2; +} ddb5476_ioport = { + { + "dma1", 0x00, 0x1f, IORESOURCE_BUSY}, { + "timer", 0x40, 0x5f, IORESOURCE_BUSY}, { + "rtc", 0x70, 0x7f, IORESOURCE_BUSY}, { + "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, { + "dma2", 0xc0, 0xdf, IORESOURCE_BUSY} +}; + +static struct { + struct resource nile4; +} ddb5476_iomem = { + { "Nile 4", DDB_BASE, DDB_BASE + DDB_SIZE - 1, IORESOURCE_BUSY} +}; + + +static void ddb5476_board_init(void); + +static void __init ddb5476_setup(void) +{ + set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE)); + + board_time_init = ddb_time_init; + board_timer_setup = ddb_timer_setup; + + _machine_restart = ddb_machine_restart; + _machine_halt = ddb_machine_halt; + _machine_power_off = ddb_machine_power_off; + + /* request io port/mem resources */ + if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) || + request_resource(&ioport_resource, &ddb5476_ioport.timer) || + request_resource(&ioport_resource, &ddb5476_ioport.rtc) || + request_resource(&ioport_resource, + &ddb5476_ioport.dma_page_reg) + || request_resource(&ioport_resource, &ddb5476_ioport.dma2) + || request_resource(&iomem_resource, &ddb5476_iomem.nile4)) { + printk + ("ddb_setup - requesting oo port resources failed.\n"); + for (;;); + } + + /* Reboot on panic */ + panic_timeout = 180; + + /* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */ + /* *(long*)0xbfa00218 = 0x8; */ + + /* board initialization stuff */ + ddb5476_board_init(); +} + +early_initcall(ddb5476_setup); + +/* + * We don't trust bios. We essentially does hardware re-initialization + * as complete as possible, as far as we know we can safely do. + */ +static void ddb5476_board_init(void) +{ + /* ----------- setup PDARs ------------ */ + /* check SDRAM0, whether we are on MEM bus does not matter */ + db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) == + ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1)); + + /* SDRAM1 should be turned off. What is this for anyway ? */ + db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0); + + /* flash 1&2, DDB status, DDB control */ + ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0); + ddb_set_pdar(DDB_DCS3, DDB_DCS3_BASE, DDB_DCS3_SIZE, 16, 0, 0); + ddb_set_pdar(DDB_DCS4, DDB_DCS4_BASE, DDB_DCS4_SIZE, 8, 0, 0); + ddb_set_pdar(DDB_DCS5, DDB_DCS5_BASE, DDB_DCS5_SIZE, 8, 0, 0); + + /* shut off other pdar so they don't accidentally get into the way */ + ddb_set_pdar(DDB_DCS6, 0xffffffff, 0, 32, 0, 0); + ddb_set_pdar(DDB_DCS7, 0xffffffff, 0, 32, 0, 0); + ddb_set_pdar(DDB_DCS8, 0xffffffff, 0, 32, 0, 0); + + /* verify VRC5477 base addr */ + /* don't care about some details */ + db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) == + ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0)); + + /* verify BOOT ROM addr */ + /* don't care about some details */ + db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) == + ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0)); + + /* setup PCI windows - window1 for MEM/config, window0 for IO */ + ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1); + ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32); + + ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1); + ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32); + + /* ----------- setup PDARs ------------ */ + /* this is problematic - it will reset Aladin which cause we loose + * serial port, and we don't know how to set up Aladin chip again. + */ + // ddb_pci_reset_bus(); + + ddb_out32(DDB_BAR0, 0x00000008); + + ddb_out32(DDB_BARC, 0xffffffff); + ddb_out32(DDB_BARB, 0xffffffff); + ddb_out32(DDB_BAR1, 0xffffffff); + ddb_out32(DDB_BAR2, 0xffffffff); + ddb_out32(DDB_BAR3, 0xffffffff); + ddb_out32(DDB_BAR4, 0xffffffff); + ddb_out32(DDB_BAR5, 0xffffffff); + ddb_out32(DDB_BAR6, 0xffffffff); + ddb_out32(DDB_BAR7, 0xffffffff); + ddb_out32(DDB_BAR8, 0xffffffff); + + /* ----------- switch PCI1 to PCI CONFIG space ------------ */ + ddb_set_pdar(DDB_PCIW1, DDB_PCI_CONFIG_BASE, DDB_PCI_CONFIG_SIZE, 32, 0, 1); + ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_CFG, 0x0, DDB_PCI_ACCESS_32); + + /* ----- M1543 PCI setup ------ */ + + /* we know M1543 PCI-ISA controller is at addr:18 */ + /* xxxx1010 makes USB at addr:13 and PMU at addr:14 */ + *(volatile unsigned char *) 0xa8040072 &= 0xf0; + *(volatile unsigned char *) 0xa8040072 |= 0xa; + + /* setup USB interrupt to IRQ 9, (bit 0:3 - 0001) + * no IOCHRDY signal, (bit 7 - 1) + * M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1) + * Make USB Master INTAJ level to edge conversion (bit 4 - 1) + */ + *(unsigned char *) 0xa8040074 = 0xd1; + + /* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011) + * SCI routing to IRQ 13 disabled (bit 7 - 1) + * SCI interrupt level to edge conversion bypassed (bit 4 - 0) + */ + *(unsigned char *) 0xa8040076 = 0x83; + + /* setup IDE controller + * enable IDE controller (bit 6 - 1) + * IDE IDSEL to be addr:24 (bit 4:5 - 11) + * no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0) + * no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0) + * primary IRQ is 14, secondary is 15 (bit 1:0 - 01 + */ + // *(unsigned char*)0xa8040058 = 0x71; + // *(unsigned char*)0xa8040058 = 0x79; + // *(unsigned char*)0xa8040058 = 0x74; // use SIRQ, primary tri-state + *(unsigned char *) 0xa8040058 = 0x75; // primary tri-state + +#if 0 + /* this is not necessary if M5229 does not use SIRQ */ + *(unsigned char *) 0xa8040044 = 0x0d; // primary to IRQ 14 + *(unsigned char *) 0xa8040075 = 0x0d; // secondary to IRQ 14 +#endif + + /* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */ + /* M5229 IDSEL is addr:24; see above setting */ + *(unsigned char *) 0xa9000050 |= 0x1; + + /* enable bus master (bit 2) and IO decoding (bit 0) */ + *(unsigned char *) 0xa9000004 |= 0x5; + + /* enable native, copied from arch/ppc/k2boot/head.S */ + /* TODO - need volatile, need to be portable */ + *(unsigned char *) 0xa9000009 = 0xff; + + /* ----- end of M1543 PCI setup ------ */ + + /* ----- reset on-board ether chip ------ */ + *((volatile u32 *) 0xa8020004) |= 1; /* decode I/O */ + *((volatile u32 *) 0xa8020010) = 0; /* set BAR address */ + + /* send reset command */ + *((volatile u32 *) 0xa6000000) = 1; /* do a soft reset */ + + /* disable ether chip */ + *((volatile u32 *) 0xa8020004) = 0; /* disable any decoding */ + + /* put it into sleep */ + *((volatile u32 *) 0xa8020040) = 0x80000000; + + /* ----- end of reset on-board ether chip ------ */ + + /* ----------- switch PCI1 back to PCI MEM space ------------ */ + ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1); + ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32); +} diff --git a/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c b/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c new file mode 100644 index 00000000000..a77682be01a --- /dev/null +++ b/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c @@ -0,0 +1,112 @@ +/* + * The irq controller for vrc5476. + * + * Copyright (C) 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/types.h> +#include <linux/ptrace.h> + +#include <asm/system.h> + +#include <asm/ddb5xxx/ddb5xxx.h> + +static int irq_base; + +static void vrc5476_irq_enable(uint irq) +{ + nile4_enable_irq(irq - irq_base); +} + +static void vrc5476_irq_disable(uint irq) +{ + nile4_disable_irq(irq - irq_base); +} + +static unsigned int vrc5476_irq_startup(uint irq) +{ + nile4_enable_irq(irq - irq_base); + return 0; +} + +#define vrc5476_irq_shutdown vrc5476_irq_disable + +static void vrc5476_irq_ack(uint irq) +{ + nile4_clear_irq(irq - irq_base); + nile4_disable_irq(irq - irq_base); +} + +static void vrc5476_irq_end(uint irq) +{ + if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) + vrc5476_irq_enable(irq); +} + +static hw_irq_controller vrc5476_irq_controller = { + "vrc5476", + vrc5476_irq_startup, + vrc5476_irq_shutdown, + vrc5476_irq_enable, + vrc5476_irq_disable, + vrc5476_irq_ack, + vrc5476_irq_end, + NULL /* no affinity stuff for UP */ +}; + +void __init +vrc5476_irq_init(u32 base) +{ + u32 i; + + irq_base = base; + for (i= base; i< base + NUM_VRC5476_IRQ; i++) { + irq_desc[i].status = IRQ_DISABLED; + irq_desc[i].action = NULL; + irq_desc[i].depth = 1; + irq_desc[i].handler = &vrc5476_irq_controller; + } +} + + +asmlinkage void +vrc5476_irq_dispatch(struct pt_regs *regs) +{ + extern void spurious_interrupt(void); + + u32 mask; + int nile4_irq; + + mask = nile4_get_irq_stat(0); + + /* quick check for possible time interrupt */ + if (mask & (1 << VRC5476_IRQ_GPT)) { + do_IRQ(VRC5476_IRQ_BASE + VRC5476_IRQ_GPT, regs); + return; + } + + /* check for i8259 interrupts */ + if (mask & (1 << VRC5476_I8259_CASCADE)) { + int i8259_irq = nile4_i8259_iack(); + do_IRQ(I8259_IRQ_BASE + i8259_irq, regs); + return; + } + + /* regular nile4 interrupts (we should not really have any */ + for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1) { + if (mask & 1) { + do_IRQ(VRC5476_IRQ_BASE + nile4_irq, regs); + return; + } + } + spurious_interrupt(); +} |