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Diffstat (limited to 'arch/mips/mm/c-octeon.c')
-rw-r--r--arch/mips/mm/c-octeon.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 94e05e5733c..0f9c488044d 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -174,7 +174,7 @@ static void octeon_flush_cache_page(struct vm_area_struct *vma,
* Probe Octeon's caches
*
*/
-static void __devinit probe_octeon(void)
+static void __cpuinit probe_octeon(void)
{
unsigned long icache_size;
unsigned long dcache_size;
@@ -183,6 +183,7 @@ static void __devinit probe_octeon(void)
switch (c->cputype) {
case CPU_CAVIUM_OCTEON:
+ case CPU_CAVIUM_OCTEON_PLUS:
config1 = read_c0_config1();
c->icache.linesz = 2 << ((config1 >> 19) & 7);
c->icache.sets = 64 << ((config1 >> 22) & 7);
@@ -192,10 +193,10 @@ static void __devinit probe_octeon(void)
c->icache.sets * c->icache.ways * c->icache.linesz;
c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
c->dcache.linesz = 128;
- if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
- c->dcache.sets = 1; /* CN3XXX has one Dcache set */
- else
+ if (c->cputype == CPU_CAVIUM_OCTEON_PLUS)
c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
+ else
+ c->dcache.sets = 1; /* CN3XXX has one Dcache set */
c->dcache.ways = 64;
dcache_size =
c->dcache.sets * c->dcache.ways * c->dcache.linesz;
@@ -235,7 +236,7 @@ static void __devinit probe_octeon(void)
* Setup the Octeon cache flush routines
*
*/
-void __devinit octeon_cache_init(void)
+void __cpuinit octeon_cache_init(void)
{
extern unsigned long ebase;
extern char except_vec2_octeon;
@@ -305,4 +306,3 @@ asmlinkage void cache_parity_error_octeon_non_recoverable(void)
{
cache_parity_error_octeon(1);
}
-