diff options
Diffstat (limited to 'arch/mips')
145 files changed, 1216 insertions, 957 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e61465a18c7..25f3b0a11ca 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -72,12 +72,12 @@ config MIPS_COBALT select IRQ_CPU select IRQ_GT641XX select PCI_GT64XXX_PCI0 + select PCI select SYS_HAS_CPU_NEVADA select SYS_HAS_EARLY_PRINTK select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN - select GENERIC_HARDIRQS_NO__DO_IRQ config MACH_DECSTATION bool "DECstations" @@ -132,11 +132,10 @@ config MACH_JAZZ select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL select SYS_SUPPORTS_100HZ - select GENERIC_HARDIRQS_NO__DO_IRQ help This a family of machines based on the MIPS R4030 chipset which was used by several vendors to build RISC/os and Windows NT workstations. - Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and + Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and Olivetti M700-10 workstations. config LASAT @@ -154,7 +153,6 @@ config LASAT select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if BROKEN select SYS_SUPPORTS_LITTLE_ENDIAN - select GENERIC_HARDIRQS_NO__DO_IRQ config LEMOTE_FULONG bool "Lemote Fulong mini-PC" @@ -175,7 +173,6 @@ config LEMOTE_FULONG select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_HIGHMEM select SYS_HAS_EARLY_PRINTK - select GENERIC_HARDIRQS_NO__DO_IRQ select GENERIC_ISA_DMA_SUPPORT_BROKEN select CPU_HAS_WB help @@ -238,15 +235,18 @@ config MIPS_SIM This option enables support for MIPS Technologies MIPSsim software emulator. -config MACH_EMMA - bool "NEC EMMA series based machines" +config NEC_MARKEINS + bool "NEC EMMA2RH Mark-eins board" + select SOC_EMMA2RH + select HW_HAS_PCI + help + This enables support for the NEC Electronics Mark-eins boards. config MACH_VR41XX bool "NEC VR4100 series based machines" select CEVT_R4K select CSRC_R4K select SYS_HAS_CPU_VR41XX - select GENERIC_HARDIRQS_NO__DO_IRQ config NXP_STB220 bool "NXP STB220 board" @@ -360,7 +360,6 @@ config SGI_IP27 select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_NUMA select SYS_SUPPORTS_SMP - select GENERIC_HARDIRQS_NO__DO_IRQ help This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics workstations. To compile a Linux kernel that runs on these, say Y @@ -559,7 +558,6 @@ config MIKROTIK_RB532 select CEVT_R4K select CSRC_R4K select DMA_NONCOHERENT - select GENERIC_HARDIRQS_NO__DO_IRQ select HW_HAS_PCI select IRQ_CPU select SYS_HAS_CPU_MIPS32_R1 @@ -596,7 +594,7 @@ config WR_PPMC board, which is based on GT64120 bridge chip. config CAVIUM_OCTEON_SIMULATOR - bool "Support for the Cavium Networks Octeon Simulator" + bool "Cavium Networks Octeon Simulator" select CEVT_R4K select 64BIT_PHYS_ADDR select DMA_COHERENT @@ -610,7 +608,7 @@ config CAVIUM_OCTEON_SIMULATOR hardware. config CAVIUM_OCTEON_REFERENCE_BOARD - bool "Support for the Cavium Networks Octeon reference board" + bool "Cavium Networks Octeon reference board" select CEVT_R4K select 64BIT_PHYS_ADDR select DMA_COHERENT @@ -637,7 +635,6 @@ endchoice source "arch/mips/alchemy/Kconfig" source "arch/mips/basler/excite/Kconfig" -source "arch/mips/emma/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/lasat/Kconfig" source "arch/mips/pmc-sierra/Kconfig" @@ -697,8 +694,7 @@ config SCHED_OMIT_FRAME_POINTER default y config GENERIC_HARDIRQS_NO__DO_IRQ - bool - default n + def_bool y # # Select some configuration options automatically based on user selections. @@ -895,6 +891,18 @@ config MIPS_RM9122 bool select SERIAL_RM9000 +config SOC_EMMA2RH + bool + select CEVT_R4K + select CSRC_R4K + select DMA_NONCOHERENT + select IRQ_CPU + select SWAP_IO_SPACE + select SYS_HAS_CPU_R5500 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + config SOC_PNX833X bool select CEVT_R4K @@ -905,7 +913,6 @@ config SOC_PNX833X select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_BIG_ENDIAN - select GENERIC_HARDIRQS_NO__DO_IRQ select GENERIC_GPIO select CPU_MIPSR2_IRQ_VI @@ -924,17 +931,11 @@ config SOC_PNX8550 select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_EARLY_PRINTK select SYS_SUPPORTS_32BIT_KERNEL - select GENERIC_HARDIRQS_NO__DO_IRQ select GENERIC_GPIO config SWAP_IO_SPACE bool -config EMMA2RH - bool - depends on MARKEINS - default y - config SERIAL_RM9000 bool @@ -1411,13 +1412,12 @@ config PAGE_SIZE_4KB config PAGE_SIZE_8KB bool "8kB" - depends on EXPERIMENTAL && CPU_R8000 + depends on (EXPERIMENTAL && CPU_R8000) || CPU_CAVIUM_OCTEON help Using 8kB page size will result in higher performance kernel at the price of higher memory consumption. This option is available - only on the R8000 processor. Not that at the time of this writing - this option is still high experimental; there are also issues with - compatibility of user applications. + only on R8000 and cnMIPS processors. Note that you will need a + suitable Linux distribution to support this. config PAGE_SIZE_16KB bool "16kB" @@ -1428,6 +1428,15 @@ config PAGE_SIZE_16KB all non-R3000 family processors. Note that you will need a suitable Linux distribution to support this. +config PAGE_SIZE_32KB + bool "32kB" + depends on CPU_CAVIUM_OCTEON + help + Using 32kB page size will result in higher performance kernel at + the price of higher memory consumption. This option is available + only on cnMIPS cores. Note that you will need a suitable Linux + distribution to support this. + config PAGE_SIZE_64KB bool "64kB" depends on EXPERIMENTAL && !CPU_R3000 && !CPU_TX39XX @@ -1958,10 +1967,6 @@ config SECCOMP endmenu -config RWSEM_GENERIC_SPINLOCK - bool - default y - config LOCKDEP_SUPPORT bool default y diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 21b00e95dae..c4cae9e6b80 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -14,8 +14,6 @@ KBUILD_DEFCONFIG := ip22_defconfig -cflags-y := -ffunction-sections - # # Select the object file format to substitute into the linker script. # @@ -50,6 +48,9 @@ ifneq ($(SUBARCH),$(ARCH)) endif endif +cflags-y := -ffunction-sections +cflags-y += $(call cc-option, -mno-check-zero-division) + ifdef CONFIG_32BIT ld-emul = $(32bit-emul) vmlinux-32 = vmlinux @@ -416,7 +417,7 @@ load-$(CONFIG_PNX8550_STB810) += 0xffffffff80060000 # # Common NEC EMMAXXX # -core-$(CONFIG_SOC_EMMA) += arch/mips/emma/common/ +core-$(CONFIG_SOC_EMMA2RH) += arch/mips/emma/common/ cflags-$(CONFIG_SOC_EMMA2RH) += -I$(srctree)/arch/mips/include/asm/mach-emma2rh # @@ -472,12 +473,12 @@ endif # Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys # ifdef CONFIG_SGI_IP28 - ifeq ($(call cc-option-yn,-mr10k-cache-barrier=1), n) - $(error gcc doesn't support needed option -mr10k-cache-barrier=1) + ifeq ($(call cc-option-yn,-mr10k-cache-barrier=store), n) + $(error gcc doesn't support needed option -mr10k-cache-barrier=store) endif endif core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/ -cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=1 -I$(srctree)/arch/mips/include/asm/mach-ip28 +cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=store -I$(srctree)/arch/mips/include/asm/mach-ip28 load-$(CONFIG_SGI_IP28) += 0xa800000020004000 # @@ -720,11 +721,17 @@ ifdef CONFIG_MIPS32_O32 $(Q)$(MAKE) $(build)=. missing-syscalls EXTRA_CFLAGS="-mabi=32" endif +install: + $(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE) + $(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE) + $(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE) + archclean: @$(MAKE) $(clean)=arch/mips/boot @$(MAKE) $(clean)=arch/mips/lasat define archhelp + echo ' install - install kernel into $(INSTALL_PATH)' echo ' vmlinux.ecoff - ECOFF boot image' echo ' vmlinux.bin - Raw binary boot image' echo ' vmlinux.srec - SREC boot image' diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 7f8ef13d001..8128aebfb15 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -134,4 +134,4 @@ config SOC_AU1X00 select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_APM_EMULATION - select GENERIC_HARDIRQS_NO__DO_IRQ + select ARCH_REQUIRE_GPIOLIB diff --git a/arch/mips/alchemy/common/gpio.c b/arch/mips/alchemy/common/gpio.c index e660ddd611c..91a9c4436c3 100644 --- a/arch/mips/alchemy/common/gpio.c +++ b/arch/mips/alchemy/common/gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007, OpenWrt.org, Florian Fainelli <florian@openwrt.org> + * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org> * Architecture specific GPIO support * * This program is free software; you can redistribute it and/or modify it @@ -27,122 +27,175 @@ * others have a second one : GPIO2 */ +#include <linux/kernel.h> #include <linux/module.h> +#include <linux/types.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> #include <asm/mach-au1x00/au1000.h> #include <asm/gpio.h> -#define gpio1 sys -#if !defined(CONFIG_SOC_AU1000) - -static struct au1x00_gpio2 *const gpio2 = (struct au1x00_gpio2 *) GPIO2_BASE; -#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000 +struct au1000_gpio_chip { + struct gpio_chip chip; + void __iomem *regbase; +}; -static int au1xxx_gpio2_read(unsigned gpio) +#if !defined(CONFIG_SOC_AU1000) +static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset) { - gpio -= AU1XXX_GPIO_BASE; - return ((gpio2->pinstate >> gpio) & 0x01); + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + return readl(gpch->regbase + AU1000_GPIO2_ST) & mask; } -static void au1xxx_gpio2_write(unsigned gpio, int value) +static void au1000_gpio2_set(struct gpio_chip *chip, + unsigned offset, int value) { - gpio -= AU1XXX_GPIO_BASE; + u32 mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset)); + struct au1000_gpio_chip *gpch; + unsigned long flags; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); - gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio); + local_irq_save(flags); + writel(mask, gpch->regbase + AU1000_GPIO2_OUT); + local_irq_restore(flags); } -static int au1xxx_gpio2_direction_input(unsigned gpio) +static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset) { - gpio -= AU1XXX_GPIO_BASE; - gpio2->dir &= ~(0x01 << gpio); + u32 mask = 1 << offset; + u32 tmp; + struct au1000_gpio_chip *gpch; + unsigned long flags; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + + local_irq_save(flags); + tmp = readl(gpch->regbase + AU1000_GPIO2_DIR); + tmp &= ~mask; + writel(tmp, gpch->regbase + AU1000_GPIO2_DIR); + local_irq_restore(flags); + return 0; } -static int au1xxx_gpio2_direction_output(unsigned gpio, int value) +static int au1000_gpio2_direction_output(struct gpio_chip *chip, + unsigned offset, int value) { - gpio -= AU1XXX_GPIO_BASE; - gpio2->dir |= 0x01 << gpio; - gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio); + u32 mask = 1 << offset; + u32 out_mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset)); + u32 tmp; + struct au1000_gpio_chip *gpch; + unsigned long flags; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + + local_irq_save(flags); + tmp = readl(gpch->regbase + AU1000_GPIO2_DIR); + tmp |= mask; + writel(tmp, gpch->regbase + AU1000_GPIO2_DIR); + writel(out_mask, gpch->regbase + AU1000_GPIO2_OUT); + local_irq_restore(flags); + return 0; } - #endif /* !defined(CONFIG_SOC_AU1000) */ -static int au1xxx_gpio1_read(unsigned gpio) +static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset) { - return (gpio1->pinstaterd >> gpio) & 0x01; + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + return readl(gpch->regbase + AU1000_GPIO1_ST) & mask; } -static void au1xxx_gpio1_write(unsigned gpio, int value) +static void au1000_gpio1_set(struct gpio_chip *chip, + unsigned offset, int value) { + u32 mask = 1 << offset; + u32 reg_offset; + struct au1000_gpio_chip *gpch; + unsigned long flags; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + if (value) - gpio1->outputset = (0x01 << gpio); + reg_offset = AU1000_GPIO1_OUT; else - /* Output a zero */ - gpio1->outputclr = (0x01 << gpio); -} + reg_offset = AU1000_GPIO1_CLR; -static int au1xxx_gpio1_direction_input(unsigned gpio) -{ - gpio1->pininputen = (0x01 << gpio); - return 0; + local_irq_save(flags); + writel(mask, gpch->regbase + reg_offset); + local_irq_restore(flags); } -static int au1xxx_gpio1_direction_output(unsigned gpio, int value) +static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset) { - gpio1->trioutclr = (0x01 & gpio); - au1xxx_gpio1_write(gpio, value); + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + writel(mask, gpch->regbase + AU1000_GPIO1_ST); + return 0; } -int au1xxx_gpio_get_value(unsigned gpio) +static int au1000_gpio1_direction_output(struct gpio_chip *chip, + unsigned offset, int value) { - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - return 0; -#else - return au1xxx_gpio2_read(gpio); -#endif - else - return au1xxx_gpio1_read(gpio); -} -EXPORT_SYMBOL(au1xxx_gpio_get_value); + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; -void au1xxx_gpio_set_value(unsigned gpio, int value) -{ - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - ; -#else - au1xxx_gpio2_write(gpio, value); -#endif - else - au1xxx_gpio1_write(gpio, value); -} -EXPORT_SYMBOL(au1xxx_gpio_set_value); + gpch = container_of(chip, struct au1000_gpio_chip, chip); -int au1xxx_gpio_direction_input(unsigned gpio) -{ - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - return -ENODEV; -#else - return au1xxx_gpio2_direction_input(gpio); -#endif + writel(mask, gpch->regbase + AU1000_GPIO1_TRI_OUT); + au1000_gpio1_set(chip, offset, value); - return au1xxx_gpio1_direction_input(gpio); + return 0; } -EXPORT_SYMBOL(au1xxx_gpio_direction_input); -int au1xxx_gpio_direction_output(unsigned gpio, int value) +struct au1000_gpio_chip au1000_gpio_chip[] = { + [0] = { + .regbase = (void __iomem *)SYS_BASE, + .chip = { + .label = "au1000-gpio1", + .direction_input = au1000_gpio1_direction_input, + .direction_output = au1000_gpio1_direction_output, + .get = au1000_gpio1_get, + .set = au1000_gpio1_set, + .base = 0, + .ngpio = 32, + }, + }, +#if !defined(CONFIG_SOC_AU1000) + [1] = { + .regbase = (void __iomem *)GPIO2_BASE, + .chip = { + .label = "au1000-gpio2", + .direction_input = au1000_gpio2_direction_input, + .direction_output = au1000_gpio2_direction_output, + .get = au1000_gpio2_get, + .set = au1000_gpio2_set, + .base = AU1XXX_GPIO_BASE, + .ngpio = 32, + }, + }, +#endif +}; + +static int __init au1000_gpio_init(void) { - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - return -ENODEV; -#else - return au1xxx_gpio2_direction_output(gpio, value); + gpiochip_add(&au1000_gpio_chip[0].chip); +#if !defined(CONFIG_SOC_AU1000) + gpiochip_add(&au1000_gpio_chip[1].chip); #endif - return au1xxx_gpio1_direction_output(gpio, value); + return 0; } -EXPORT_SYMBOL(au1xxx_gpio_direction_output); +arch_initcall(au1000_gpio_init); + diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 5c76c6448e0..117f99f7064 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -80,14 +80,14 @@ static struct resource au1xxx_usb_ohci_resources[] = { }; /* The dmamask must be set for OHCI to work */ -static u64 ohci_dmamask = DMA_32BIT_MASK; +static u64 ohci_dmamask = DMA_BIT_MASK(32); static struct platform_device au1xxx_usb_ohci_device = { .name = "au1xxx-ohci", .id = 0, .dev = { .dma_mask = &ohci_dmamask, - .coherent_dma_mask = DMA_32BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources), .resource = au1xxx_usb_ohci_resources, @@ -109,14 +109,14 @@ static struct resource au1100_lcd_resources[] = { } }; -static u64 au1100_lcd_dmamask = DMA_32BIT_MASK; +static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); static struct platform_device au1100_lcd_device = { .name = "au1100-lcd", .id = 0, .dev = { .dma_mask = &au1100_lcd_dmamask, - .coherent_dma_mask = DMA_32BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(au1100_lcd_resources), .resource = au1100_lcd_resources, @@ -138,14 +138,14 @@ static struct resource au1xxx_usb_ehci_resources[] = { }, }; -static u64 ehci_dmamask = DMA_32BIT_MASK; +static u64 ehci_dmamask = DMA_BIT_MASK(32); static struct platform_device au1xxx_usb_ehci_device = { .name = "au1xxx-ehci", .id = 0, .dev = { .dma_mask = &ehci_dmamask, - .coherent_dma_mask = DMA_32BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(au1xxx_usb_ehci_resources), .resource = au1xxx_usb_ehci_resources, @@ -165,14 +165,14 @@ static struct resource au1xxx_usb_gdt_resources[] = { }, }; -static u64 udc_dmamask = DMA_32BIT_MASK; +static u64 udc_dmamask = DMA_BIT_MASK(32); static struct platform_device au1xxx_usb_gdt_device = { .name = "au1xxx-udc", .id = 0, .dev = { .dma_mask = &udc_dmamask, - .coherent_dma_mask = DMA_32BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(au1xxx_usb_gdt_resources), .resource = au1xxx_usb_gdt_resources, @@ -192,14 +192,14 @@ static struct resource au1xxx_usb_otg_resources[] = { }, }; -static u64 uoc_dmamask = DMA_32BIT_MASK; +static u64 uoc_dmamask = DMA_BIT_MASK(32); static struct platform_device au1xxx_usb_otg_device = { .name = "au1xxx-uoc", .id = 0, .dev = { .dma_mask = &uoc_dmamask, - .coherent_dma_mask = DMA_32BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(au1xxx_usb_otg_resources), .resource = au1xxx_usb_otg_resources, @@ -218,20 +218,20 @@ static struct resource au1200_lcd_resources[] = { } }; -static u64 au1200_lcd_dmamask = DMA_32BIT_MASK; +static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32); static struct platform_device au1200_lcd_device = { .name = "au1200-lcd", .id = 0, .dev = { .dma_mask = &au1200_lcd_dmamask, - .coherent_dma_mask = DMA_32BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(au1200_lcd_resources), .resource = au1200_lcd_resources, }; -static u64 au1xxx_mmc_dmamask = DMA_32BIT_MASK; +static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); extern struct au1xmmc_platform_data au1xmmc_platdata[2]; @@ -263,7 +263,7 @@ static struct platform_device au1200_mmc0_device = { .id = 0, .dev = { .dma_mask = &au1xxx_mmc_dmamask, - .coherent_dma_mask = DMA_32BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &au1xmmc_platdata[0], }, .num_resources = ARRAY_SIZE(au1200_mmc0_resources), @@ -299,7 +299,7 @@ static struct platform_device au1200_mmc1_device = { .id = 1, .dev = { .dma_mask = &au1xxx_mmc_dmamask, - .coherent_dma_mask = DMA_32BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &au1xmmc_platdata[1], }, .num_resources = ARRAY_SIZE(au1200_mmc1_resources), diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index f58d4ffb894..33fbae79af5 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -44,7 +44,7 @@ extern int allow_au1k_wait; /* default off for CP0 Counter */ -static cycle_t au1x_counter1_read(void) +static cycle_t au1x_counter1_read(struct clocksource *cs) { return au_readl(SYS_RTCREAD); } diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index 95303297c53..b93dff4a678 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -22,6 +22,7 @@ #include <linux/init.h> #include <linux/leds.h> #include <linux/platform_device.h> +#include <linux/smc91x.h> #include <asm/mach-au1x00/au1xxx.h> #include <asm/mach-au1x00/au1100_mmc.h> @@ -118,19 +119,25 @@ static struct resource ide_resources[] = { } }; -static u64 ide_dmamask = DMA_32BIT_MASK; +static u64 ide_dmamask = DMA_BIT_MASK(32); static struct platform_device ide_device = { .name = "au1200-ide", .id = 0, .dev = { .dma_mask = &ide_dmamask, - .coherent_dma_mask = DMA_32BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(ide_resources), .resource = ide_resources }; +static struct smc91x_platdata smc_data = { + .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT, + .leda = RPC_LED_100_10, + .ledb = RPC_LED_TX_RX, +}; + static struct resource smc91c111_resources[] = { [0] = { .name = "smc91x-regs", @@ -146,6 +153,9 @@ static struct resource smc91c111_resources[] = { }; static struct platform_device smc91c111_device = { + .dev = { + .platform_data = &smc_data, + }, .name = "smc91x", .id = -1, .num_resources = ARRAY_SIZE(smc91c111_resources), diff --git a/arch/mips/basler/excite/excite_iodev.c b/arch/mips/basler/excite/excite_iodev.c index a1e3526b4a9..dfbfd7e2ac0 100644 --- a/arch/mips/basler/excite/excite_iodev.c +++ b/arch/mips/basler/excite/excite_iodev.c @@ -33,8 +33,8 @@ static const struct resource *iodev_get_resource(struct platform_device *, const char *, unsigned int); -static int __init iodev_probe(struct device *); -static int __exit iodev_remove(struct device *); +static int __init iodev_probe(struct platform_device *); +static int __exit iodev_remove(struct platform_device *); static int iodev_open(struct inode *, struct file *); static int iodev_release(struct inode *, struct file *); static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *); @@ -65,13 +65,13 @@ static struct miscdevice miscdev = .fops = &fops }; -static struct device_driver iodev_driver = -{ - .name = (char *) iodev_name, - .bus = &platform_bus_type, - .owner = THIS_MODULE, +static struct platform_driver iodev_driver = { + .driver = { + .name = iodev_name, + .owner = THIS_MODULE, + }, .probe = iodev_probe, - .remove = __exit_p(iodev_remove) + .remove = __devexit_p(iodev_remove), }; @@ -89,11 +89,10 @@ iodev_get_resource(struct platform_device *pdv, const char *name, /* No hotplugging on the platform bus - use __init */ -static int __init iodev_probe(struct device *dev) +static int __init iodev_probe(struct platform_device *dev) { - struct platform_device * const pdv = to_platform_device(dev); const struct resource * const ri = - iodev_get_resource(pdv, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ); + iodev_get_resource(dev, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ); if (unlikely(!ri)) return -ENXIO; @@ -104,7 +103,7 @@ static int __init iodev_probe(struct device *dev) -static int __exit iodev_remove(struct device *dev) +static int __exit iodev_remove(struct platform_device *dev) { return misc_deregister(&miscdev); } @@ -160,14 +159,14 @@ static irqreturn_t iodev_irqhdl(int irq, void *ctxt) static int __init iodev_init_module(void) { - return driver_register(&iodev_driver); + return platform_driver_register(&iodev_driver); } static void __exit iodev_cleanup_module(void) { - driver_unregister(&iodev_driver); + platform_driver_unregister(&iodev_driver); } module_init(iodev_init_module); diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 1c2a7faf588..d6903c3f3d5 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -14,3 +14,5 @@ obj-y += dma-octeon.o flash_setup.o obj-y += octeon-memcpy.o obj-$(CONFIG_SMP) += smp.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c index 70fd92c3165..96110f217dc 100644 --- a/arch/mips/cavium-octeon/csrc-octeon.c +++ b/arch/mips/cavium-octeon/csrc-octeon.c @@ -38,7 +38,7 @@ void octeon_init_cvmcount(void) local_irq_restore(flags); } -static cycle_t octeon_cvmcount_read(void) +static cycle_t octeon_cvmcount_read(struct clocksource *cs) { return read_c0_cvmcount(); } diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c index 553d36cbcc4..008f657116e 100644 --- a/arch/mips/cavium-octeon/flash_setup.c +++ b/arch/mips/cavium-octeon/flash_setup.c @@ -57,7 +57,7 @@ static int __init flash_init(void) flash_map.bankwidth = 1; flash_map.virt = ioremap(flash_map.phys, flash_map.size); pr_notice("Bootbus flash: Setting flash for %luMB flash at " - "0x%08lx\n", flash_map.size >> 20, flash_map.phys); + "0x%08llx\n", flash_map.size >> 20, flash_map.phys); simple_map_init(&flash_map); mymtd = do_map_probe("cfi_probe", &flash_map); if (mymtd) { diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index fc72984a5da..1c19af8daa6 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -31,7 +31,7 @@ static void octeon_irq_core_ack(unsigned int irq) static void octeon_irq_core_eoi(unsigned int irq) { - irq_desc_t *desc = irq_desc + irq; + struct irq_desc *desc = irq_desc + irq; unsigned int bit = irq - OCTEON_IRQ_SW0; /* * If an IRQ is being processed while we are disabling it the diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c index ac4fb912649..cb9bf820fe5 100644 --- a/arch/mips/cobalt/irq.c +++ b/arch/mips/cobalt/irq.c @@ -47,7 +47,6 @@ asmlinkage void plat_irq_dispatch(void) static struct irqaction cascade = { .handler = no_action, - .mask = CPU_MASK_NONE, .name = "cascade", }; diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/markeins_defconfig index fea9bc9865a..bad8901f8f3 100644 --- a/arch/mips/configs/emma2rh_defconfig +++ b/arch/mips/configs/markeins_defconfig @@ -35,7 +35,7 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set -CONFIG_MARKEINS=y +CONFIG_NEC_MARKEINS=y # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -68,7 +68,7 @@ CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_SWAP_IO_SPACE=y -CONFIG_EMMA2RH=y +CONFIG_SOC_EMMA2RH=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # @@ -574,9 +574,9 @@ CONFIG_MTD_CFI_UTIL=y # # CONFIG_MTD_COMPLEX_MAPPINGS is not set CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0x1e000000 -CONFIG_MTD_PHYSMAP_LEN=0x02000000 -CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +CONFIG_MTD_PHYSMAP_START=0x0 +CONFIG_MTD_PHYSMAP_LEN=0x0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=0 # CONFIG_MTD_PLATRAM is not set # diff --git a/arch/mips/emma/Kconfig b/arch/mips/emma/Kconfig deleted file mode 100644 index 9669c72123c..00000000000 --- a/arch/mips/emma/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -choice - prompt "Machine type" - depends on MACH_EMMA - default NEC_MARKEINS - -config NEC_MARKEINS - bool "NEC EMMA2RH Mark-eins board" - select SOC_EMMA2RH - select HW_HAS_PCI - help - This enables support for the NEC Electronics Mark-eins boards. - -endchoice - -config SOC_EMMA2RH - bool - select SOC_EMMA - select SYS_HAS_CPU_R5500 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - -config SOC_EMMA - bool - select CEVT_R4K - select CSRC_R4K - select DMA_NONCOHERENT - select IRQ_CPU - select SWAP_IO_SPACE - select SYS_SUPPORTS_BIG_ENDIAN diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c index c2583ecc93c..43828ae796e 100644 --- a/arch/mips/emma/markeins/irq.c +++ b/arch/mips/emma/markeins/irq.c @@ -80,9 +80,9 @@ void emma2rh_irq_init(void) u32 i; for (i = 0; i < NUM_EMMA2RH_IRQ; i++) - set_irq_chip_and_handler(EMMA2RH_IRQ_BASE + i, - &emma2rh_irq_controller, - handle_level_irq); + set_irq_chip_and_handler_name(EMMA2RH_IRQ_BASE + i, + &emma2rh_irq_controller, + handle_level_irq, "level"); } static void emma2rh_sw_irq_enable(unsigned int irq) @@ -120,9 +120,9 @@ void emma2rh_sw_irq_init(void) u32 i; for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++) - set_irq_chip_and_handler(EMMA2RH_SW_IRQ_BASE + i, - &emma2rh_sw_irq_controller, - handle_level_irq); + set_irq_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i, + &emma2rh_sw_irq_controller, + handle_level_irq, "level"); } static void emma2rh_gpio_irq_enable(unsigned int irq) @@ -149,37 +149,28 @@ static void emma2rh_gpio_irq_disable(unsigned int irq) static void emma2rh_gpio_irq_ack(unsigned int irq) { - u32 reg; - irq -= EMMA2RH_GPIO_IRQ_BASE; emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); - - reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); - reg &= ~(1 << irq); - emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); } -static void emma2rh_gpio_irq_end(unsigned int irq) +static void emma2rh_gpio_irq_mask_ack(unsigned int irq) { u32 reg; - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { - - irq -= EMMA2RH_GPIO_IRQ_BASE; + irq -= EMMA2RH_GPIO_IRQ_BASE; + emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); - reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); - reg |= 1 << irq; - emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); - } + reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); + reg &= ~(1 << irq); + emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); } struct irq_chip emma2rh_gpio_irq_controller = { .name = "emma2rh_gpio_irq", .ack = emma2rh_gpio_irq_ack, .mask = emma2rh_gpio_irq_disable, - .mask_ack = emma2rh_gpio_irq_ack, + .mask_ack = emma2rh_gpio_irq_mask_ack, .unmask = emma2rh_gpio_irq_enable, - .end = emma2rh_gpio_irq_end, }; void emma2rh_gpio_irq_init(void) @@ -187,14 +178,14 @@ void emma2rh_gpio_irq_init(void) u32 i; for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++) - set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i, - &emma2rh_gpio_irq_controller); + set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i, + &emma2rh_gpio_irq_controller, + handle_edge_irq, "edge"); } static struct irqaction irq_cascade = { .handler = no_action, .flags = 0, - .mask = CPU_MASK_NONE, .name = "cascade", .dev_id = NULL, .next = NULL, @@ -213,8 +204,7 @@ void emma2rh_irq_dispatch(void) emma2rh_in32(EMMA2RH_BHIF_INT_EN_0); #ifdef EMMA2RH_SW_CASCADE - if (intStatus & - (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) { + if (intStatus & (1UL << EMMA2RH_SW_CASCADE)) { u32 swIntStatus; swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT) & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); @@ -225,6 +215,8 @@ void emma2rh_irq_dispatch(void) } } } + /* Skip S/W interrupt */ + intStatus &= ~(1UL << EMMA2RH_SW_CASCADE); #endif for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { @@ -238,8 +230,7 @@ void emma2rh_irq_dispatch(void) emma2rh_in32(EMMA2RH_BHIF_INT_EN_1); #ifdef EMMA2RH_GPIO_CASCADE - if (intStatus & - (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) { + if (intStatus & (1UL << (EMMA2RH_GPIO_CASCADE % 32))) { u32 gpioIntStatus; gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST) & emma2rh_in32(EMMA2RH_GPIO_INT_MASK); @@ -250,6 +241,8 @@ void emma2rh_irq_dispatch(void) } } } + /* Skip GPIO interrupt */ + intStatus &= ~(1UL << (EMMA2RH_GPIO_CASCADE % 32)); #endif for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) { diff --git a/arch/mips/emma/markeins/platform.c b/arch/mips/emma/markeins/platform.c index 88e87f6b344..80ae12ef87d 100644 --- a/arch/mips/emma/markeins/platform.c +++ b/arch/mips/emma/markeins/platform.c @@ -110,6 +110,7 @@ struct platform_device i2c_emma_devices[] = { static struct plat_serial8250_port platform_serial_ports[] = { [0] = { .membase= (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3), + .mapbase = EMMA2RH_PFUR0_BASE + 3, .irq = EMMA2RH_IRQ_PFUR0, .uartclk = EMMA2RH_SERIAL_CLOCK, .regshift = 4, @@ -117,6 +118,7 @@ static struct plat_serial8250_port platform_serial_ports[] = { .flags = EMMA2RH_SERIAL_FLAGS, }, [1] = { .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3), + .mapbase = EMMA2RH_PFUR1_BASE + 3, .irq = EMMA2RH_IRQ_PFUR1, .uartclk = EMMA2RH_SERIAL_CLOCK, .regshift = 4, @@ -124,6 +126,7 @@ static struct plat_serial8250_port platform_serial_ports[] = { .flags = EMMA2RH_SERIAL_FLAGS, }, [2] = { .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3), + .mapbase = EMMA2RH_PFUR2_BASE + 3, .irq = EMMA2RH_IRQ_PFUR2, .uartclk = EMMA2RH_SERIAL_CLOCK, .regshift = 4, @@ -141,13 +144,6 @@ static struct platform_device serial_emma = { }, }; -static struct platform_device *devices[] = { - &i2c_emma_devices[0], - &i2c_emma_devices[1], - &i2c_emma_devices[2], - &serial_emma, -}; - static struct mtd_partition markeins_parts[] = { [0] = { .name = "RootFS", @@ -181,11 +177,39 @@ static struct mtd_partition markeins_parts[] = { }, }; +static struct physmap_flash_data markeins_flash_data = { + .width = 2, + .nr_parts = ARRAY_SIZE(markeins_parts), + .parts = markeins_parts +}; + +static struct resource markeins_flash_resource = { + .start = 0x1e000000, + .end = 0x02000000, + .flags = IORESOURCE_MEM +}; + +static struct platform_device markeins_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &markeins_flash_data, + }, + .num_resources = 1, + .resource = &markeins_flash_resource, +}; + +static struct platform_device *devices[] = { + i2c_emma_devices, + i2c_emma_devices + 1, + i2c_emma_devices + 2, + &serial_emma, + &markeins_flash_device, +}; + static int __init platform_devices_setup(void) { - physmap_set_partitions(markeins_parts, ARRAY_SIZE(markeins_parts)); return platform_add_devices(devices, ARRAY_SIZE(devices)); } arch_initcall(platform_devices_setup); - diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index bac4a960b24..b1e9e97a9c7 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -567,7 +567,7 @@ static inline unsigned long __fls(unsigned long word) int num; if (BITS_PER_LONG == 32 && - __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { + __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) { __asm__( " .set push \n" " .set mips32 \n" @@ -644,7 +644,7 @@ static inline int fls(int x) { int r; - if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { + if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) { __asm__("clz %0, %1" : "=r" (x) : "r" (x)); return 32 - x; diff --git a/arch/mips/include/asm/checksum.h b/arch/mips/include/asm/checksum.h index 290485ac540..f2f7c6c264d 100644 --- a/arch/mips/include/asm/checksum.h +++ b/arch/mips/include/asm/checksum.h @@ -40,7 +40,7 @@ static inline __wsum csum_partial_copy_from_user(const void __user *src, void *dst, int len, __wsum sum, int *err_ptr) { - might_sleep(); + might_fault(); return __csum_partial_copy_user((__force void *)src, dst, len, sum, err_ptr); } @@ -53,7 +53,7 @@ static inline __wsum csum_and_copy_to_user(const void *src, void __user *dst, int len, __wsum sum, int *err_ptr) { - might_sleep(); + might_fault(); if (access_ok(VERIFY_WRITE, dst, len)) return __csum_partial_copy_user(src, (__force void *)dst, len, sum, err_ptr); diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h index 6c5b40905dd..f58aed354bf 100644 --- a/arch/mips/include/asm/compat.h +++ b/arch/mips/include/asm/compat.h @@ -3,7 +3,6 @@ /* * Architecture specific compatibility types */ -#include <linux/seccomp.h> #include <linux/thread_info.h> #include <linux/types.h> #include <asm/page.h> diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index a0d14f85b78..c0047f86133 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -147,6 +147,15 @@ #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ cpu_has_mips64r1 | cpu_has_mips64r2) +/* + * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other + * pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels + * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. + */ +# ifndef cpu_has_clo_clz +# define cpu_has_clo_clz cpu_has_mips_r +# endif + #ifndef cpu_has_dsp #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) #endif diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index 744cd8fb107..126044308de 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h @@ -39,8 +39,8 @@ struct cache_desc { #define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */ struct cpuinfo_mips { - unsigned long udelay_val; - unsigned long asid_cache; + unsigned int udelay_val; + unsigned int asid_cache; /* * Capability and feature descriptor structure for MIPS CPU diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index c018727c7dd..3bdc0e3d89c 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -209,8 +209,7 @@ enum cpu_type_enum { * MIPS32 class processors */ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, - CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, - CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, + CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, /* * MIPS64 class processors diff --git a/arch/mips/include/asm/delay.h b/arch/mips/include/asm/delay.h index b0bccd2c4ed..a07e51b2be1 100644 --- a/arch/mips/include/asm/delay.h +++ b/arch/mips/include/asm/delay.h @@ -11,94 +11,12 @@ #ifndef _ASM_DELAY_H #define _ASM_DELAY_H -#include <linux/param.h> -#include <linux/smp.h> +extern void __delay(unsigned int loops); +extern void __ndelay(unsigned int ns); +extern void __udelay(unsigned int us); -#include <asm/compiler.h> -#include <asm/war.h> - -static inline void __delay(unsigned long loops) -{ - if (sizeof(long) == 4) - __asm__ __volatile__ ( - " .set noreorder \n" - " .align 3 \n" - "1: bnez %0, 1b \n" - " subu %0, 1 \n" - " .set reorder \n" - : "=r" (loops) - : "0" (loops)); - else if (sizeof(long) == 8 && !DADDI_WAR) - __asm__ __volatile__ ( - " .set noreorder \n" - " .align 3 \n" - "1: bnez %0, 1b \n" - " dsubu %0, 1 \n" - " .set reorder \n" - : "=r" (loops) - : "0" (loops)); - else if (sizeof(long) == 8 && DADDI_WAR) - __asm__ __volatile__ ( - " .set noreorder \n" - " .align 3 \n" - "1: bnez %0, 1b \n" - " dsubu %0, %2 \n" - " .set reorder \n" - : "=r" (loops) - : "0" (loops), "r" (1)); -} - - -/* - * Division by multiplication: you don't have to worry about - * loss of precision. - * - * Use only for very small delays ( < 1 msec). Should probably use a - * lookup table, really, as the multiplications take much too long with - * short delays. This is a "reasonable" implementation, though (and the - * first constant multiplications gets optimized away if the delay is - * a constant) - */ - -static inline void __udelay(unsigned long usecs, unsigned long lpj) -{ - unsigned long hi, lo; - - /* - * The rates of 128 is rounded wrongly by the catchall case - * for 64-bit. Excessive precission? Probably ... - */ -#if defined(CONFIG_64BIT) && (HZ == 128) - usecs *= 0x0008637bd05af6c7UL; /* 2**64 / (1000000 / HZ) */ -#elif defined(CONFIG_64BIT) - usecs *= (0x8000000000000000UL / (500000 / HZ)); -#else /* 32-bit junk follows here */ - usecs *= (unsigned long) (((0x8000000000000000ULL / (500000 / HZ)) + - 0x80000000ULL) >> 32); -#endif - - if (sizeof(long) == 4) - __asm__("multu\t%2, %3" - : "=h" (usecs), "=l" (lo) - : "r" (usecs), "r" (lpj) - : GCC_REG_ACCUM); - else if (sizeof(long) == 8 && !R4000_WAR) - __asm__("dmultu\t%2, %3" - : "=h" (usecs), "=l" (lo) - : "r" (usecs), "r" (lpj) - : GCC_REG_ACCUM); - else if (sizeof(long) == 8 && R4000_WAR) - __asm__("dmultu\t%3, %4\n\tmfhi\t%0" - : "=r" (usecs), "=h" (hi), "=l" (lo) - : "r" (usecs), "r" (lpj) - : GCC_REG_ACCUM); - - __delay(usecs); -} - -#define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val - -#define udelay(usecs) __udelay((usecs), __udelay_val) +#define ndelay(ns) __udelay(ns) +#define udelay(us) __udelay(us) /* make sure "usecs *= ..." in udelay do not overflow. */ #if HZ >= 1000 diff --git a/arch/mips/include/asm/div64.h b/arch/mips/include/asm/div64.h index d1d699105c1..dc5ea573644 100644 --- a/arch/mips/include/asm/div64.h +++ b/arch/mips/include/asm/div64.h @@ -6,105 +6,63 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. */ -#ifndef _ASM_DIV64_H -#define _ASM_DIV64_H +#ifndef __ASM_DIV64_H +#define __ASM_DIV64_H -#include <linux/types.h> +#include <asm-generic/div64.h> -#if (_MIPS_SZLONG == 32) +#if BITS_PER_LONG == 64 -#include <asm/compiler.h> +#include <linux/types.h> /* * No traps on overflows for any of these... */ -#define do_div64_32(res, high, low, base) ({ \ - unsigned long __quot32, __mod32; \ - unsigned long __cf, __tmp, __tmp2, __i; \ - \ - __asm__(".set push\n\t" \ - ".set noat\n\t" \ - ".set noreorder\n\t" \ - "move %2, $0\n\t" \ - "move %3, $0\n\t" \ - "b 1f\n\t" \ - " li %4, 0x21\n" \ - "0:\n\t" \ - "sll $1, %0, 0x1\n\t" \ - "srl %3, %0, 0x1f\n\t" \ - "or %0, $1, %5\n\t" \ - "sll %1, %1, 0x1\n\t" \ - "sll %2, %2, 0x1\n" \ - "1:\n\t" \ - "bnez %3, 2f\n\t" \ - " sltu %5, %0, %z6\n\t" \ - "bnez %5, 3f\n" \ - "2:\n\t" \ - " addiu %4, %4, -1\n\t" \ - "subu %0, %0, %z6\n\t" \ - "addiu %2, %2, 1\n" \ - "3:\n\t" \ - "bnez %4, 0b\n\t" \ - " srl %5, %1, 0x1f\n\t" \ - ".set pop" \ - : "=&r" (__mod32), "=&r" (__tmp), \ - "=&r" (__quot32), "=&r" (__cf), \ - "=&r" (__i), "=&r" (__tmp2) \ - : "Jr" (base), "0" (high), "1" (low)); \ - \ - (res) = __quot32; \ - __mod32; }) - -#define do_div(n, base) ({ \ - unsigned long long __quot; \ - unsigned long __mod; \ - unsigned long long __div; \ - unsigned long __upper, __low, __high, __base; \ - \ - __div = (n); \ - __base = (base); \ - \ - __high = __div >> 32; \ - __low = __div; \ - __upper = __high; \ - \ - if (__high) \ - __asm__("divu $0, %z2, %z3" \ - : "=h" (__upper), "=l" (__high) \ - : "Jr" (__high), "Jr" (__base) \ - : GCC_REG_ACCUM); \ - \ - __mod = do_div64_32(__low, __upper, __low, __base); \ - \ - __quot = __high; \ - __quot = __quot << 32 | __low; \ - (n) = __quot; \ - __mod; }) - -#endif /* (_MIPS_SZLONG == 32) */ - -#if (_MIPS_SZLONG == 64) - -/* - * Hey, we're already 64-bit, no - * need to play games.. - */ -#define do_div(n, base) ({ \ - unsigned long __quot; \ - unsigned int __mod; \ - unsigned long __div; \ - unsigned int __base; \ - \ - __div = (n); \ - __base = (base); \ - \ - __mod = __div % __base; \ - __quot = __div / __base; \ - \ - (n) = __quot; \ - __mod; }) +#define __div64_32(n, base) \ +({ \ + unsigned long __cf, __tmp, __tmp2, __i; \ + unsigned long __quot32, __mod32; \ + unsigned long __high, __low; \ + unsigned long long __n; \ + \ + __high = *__n >> 32; \ + __low = __n; \ + __asm__( \ + " .set push \n" \ + " .set noat \n" \ + " .set noreorder \n" \ + " move %2, $0 \n" \ + " move %3, $0 \n" \ + " b 1f \n" \ + " li %4, 0x21 \n" \ + "0: \n" \ + " sll $1, %0, 0x1 \n" \ + " srl %3, %0, 0x1f \n" \ + " or %0, $1, %5 \n" \ + " sll %1, %1, 0x1 \n" \ + " sll %2, %2, 0x1 \n" \ + "1: \n" \ + " bnez %3, 2f \n" \ + " sltu %5, %0, %z6 \n" \ + " bnez %5, 3f \n" \ + "2: \n" \ + " addiu %4, %4, -1 \n" \ + " subu %0, %0, %z6 \n" \ + " addiu %2, %2, 1 \n" \ + "3: \n" \ + " bnez %4, 0b\n\t" \ + " srl %5, %1, 0x1f\n\t" \ + " .set pop" \ + : "=&r" (__mod32), "=&r" (__tmp), \ + "=&r" (__quot32), "=&r" (__cf), \ + "=&r" (__i), "=&r" (__tmp2) \ + : "Jr" (base), "0" (__high), "1" (__low)); \ + \ + (__n) = __quot32; \ + __mod32; \ +}) -#endif /* (_MIPS_SZLONG == 64) */ +#endif /* BITS_PER_LONG == 64 */ -#endif /* _ASM_DIV64_H */ +#endif /* __ASM_DIV64_H */ diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h index c64afb40cd0..d16afddb09a 100644 --- a/arch/mips/include/asm/dma-mapping.h +++ b/arch/mips/include/asm/dma-mapping.h @@ -24,8 +24,13 @@ extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, enum dma_data_direction direction); extern dma_addr_t dma_map_page(struct device *dev, struct page *page, unsigned long offset, size_t size, enum dma_data_direction direction); -extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address, - size_t size, enum dma_data_direction direction); + +static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address, + size_t size, enum dma_data_direction direction) +{ + dma_unmap_single(dev, dma_address, size, direction); +} + extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, enum dma_data_direction direction); extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, diff --git a/arch/mips/include/asm/fixmap.h b/arch/mips/include/asm/fixmap.h index 9cc8522a394..0f5caa1307f 100644 --- a/arch/mips/include/asm/fixmap.h +++ b/arch/mips/include/asm/fixmap.h @@ -108,6 +108,9 @@ static inline unsigned long virt_to_fix(const unsigned long vaddr) return __virt_to_fix(vaddr); } +#define kmap_get_fixmap_pte(vaddr) \ + pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr)) + /* * Called from pgtable_init() */ diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h new file mode 100644 index 00000000000..40a8c178f10 --- /dev/null +++ b/arch/mips/include/asm/ftrace.h @@ -0,0 +1 @@ +/* empty */ diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index 134e1fc8f4d..0eaf77ffbc4 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -87,7 +87,7 @@ do { \ : "=r" (tmp)); \ } while (0) -#elif defined(CONFIG_CPU_MIPSR1) +#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY) /* * These are slightly complicated by the fact that we guarantee R1 kernels to @@ -138,7 +138,8 @@ do { \ __instruction_hazard(); \ } while (0) -#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ +#elif defined(CONFIG_MACH_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ + defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ defined(CONFIG_CPU_R5500) /* diff --git a/arch/mips/include/asm/highmem.h b/arch/mips/include/asm/highmem.h index 4374ab2adc7..25adfb02923 100644 --- a/arch/mips/include/asm/highmem.h +++ b/arch/mips/include/asm/highmem.h @@ -30,8 +30,6 @@ /* declarations for highmem.c */ extern unsigned long highstart_pfn, highend_pfn; -extern pte_t *kmap_pte; -extern pgprot_t kmap_prot; extern pte_t *pkmap_page_table; /* @@ -62,6 +60,10 @@ extern struct page *__kmap_atomic_to_page(void *ptr); #define flush_cache_kmaps() flush_cache_all() +extern void kmap_init(void); + +#define kmap_prot PAGE_KERNEL + #endif /* __KERNEL__ */ #endif /* _ASM_HIGHMEM_H */ diff --git a/arch/mips/include/asm/ioctl.h b/arch/mips/include/asm/ioctl.h index 85067e248a8..916163401b2 100644 --- a/arch/mips/include/asm/ioctl.h +++ b/arch/mips/include/asm/ioctl.h @@ -60,12 +60,16 @@ ((nr) << _IOC_NRSHIFT) | \ ((size) << _IOC_SIZESHIFT)) +#ifdef __KERNEL__ /* provoke compile error for invalid uses of size argument */ extern unsigned int __invalid_size_argument_for_IOC; #define _IOC_TYPECHECK(t) \ ((sizeof(t) == sizeof(t[1]) && \ sizeof(t) < (1 << _IOC_SIZEBITS)) ? \ sizeof(t) : __invalid_size_argument_for_IOC) +#else +#define _IOC_TYPECHECK(t) (sizeof(t)) +#endif /* used to create numbers */ #define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0) diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index abc62aa744a..3214ade02d1 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h @@ -66,7 +66,7 @@ extern void smtc_forward_irq(unsigned int irq); */ #define IRQ_AFFINITY_HOOK(irq) \ do { \ - if (!cpu_isset(smp_processor_id(), irq_desc[irq].affinity)) { \ + if (!cpumask_test_cpu(smp_processor_id(), irq_desc[irq].affinity)) {\ smtc_forward_irq(irq); \ irq_exit(); \ return; \ diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 62f91f50b5b..854e95f1b07 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -715,7 +715,7 @@ enum soc_au1500_ints { #ifdef CONFIG_SOC_AU1100 enum soc_au1100_ints { AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, - AU1100_UART0_INT, + AU1100_UART0_INT = AU1100_FIRST_INT, AU1100_UART1_INT, AU1100_SD_INT, AU1100_UART3_INT, @@ -902,8 +902,8 @@ enum soc_au1200_ints { AU1000_RTC_MATCH0_INT, AU1000_RTC_MATCH1_INT, AU1000_RTC_MATCH2_INT, - - AU1200_NAND_INT = AU1200_FIRST_INT + 23, + AU1200_GPIO_203, + AU1200_NAND_INT, AU1200_GPIO_204, AU1200_GPIO_205, AU1200_GPIO_206, diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h index 60638b8969b..5656c72de6d 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h @@ -46,20 +46,6 @@ #define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0 #endif -#ifdef CONFIG_PM -/* - * This will enable the device to be powered up when write() or read() - * is called. If this is not defined, the driver will return -EBUSY. - */ -#define WAKE_ON_ACCESS 1 - -typedef struct { - spinlock_t lock; /* Used to block on state transitions */ - au1xxx_power_dev_t *dev; /* Power Managers device structure */ - unsigned stopped; /* Used to signal device is stopped */ -} pm_state; -#endif - typedef struct { u32 tx_dev_id, rx_dev_id, target_dev_id; u32 tx_chan, rx_chan; @@ -72,9 +58,6 @@ typedef struct { #endif int irq; u32 regbase; -#ifdef CONFIG_PM - pm_state pm; -#endif } _auide_hwif; /******************************************************************************/ diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h new file mode 100644 index 00000000000..d5df0cab9b8 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h @@ -0,0 +1,49 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_mcheck 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 +#define cpu_has_mips16 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 1 +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_vint 0 +#define cpu_has_veic 0 +#define cpu_has_inclusive_pcaches 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 + +#endif /* __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h index 2dc61e009a0..34d9b727902 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio.h +++ b/arch/mips/include/asm/mach-au1x00/gpio.h @@ -5,65 +5,29 @@ #define AU1XXX_GPIO_BASE 200 -struct au1x00_gpio2 { - u32 dir; - u32 reserved; - u32 output; - u32 pinstate; - u32 inten; - u32 enable; -}; +/* GPIO bank 1 offsets */ +#define AU1000_GPIO1_TRI_OUT 0x0100 +#define AU1000_GPIO1_OUT 0x0108 +#define AU1000_GPIO1_ST 0x0110 +#define AU1000_GPIO1_CLR 0x010C -extern int au1xxx_gpio_get_value(unsigned gpio); -extern void au1xxx_gpio_set_value(unsigned gpio, int value); -extern int au1xxx_gpio_direction_input(unsigned gpio); -extern int au1xxx_gpio_direction_output(unsigned gpio, int value); +/* GPIO bank 2 offsets */ +#define AU1000_GPIO2_DIR 0x00 +#define AU1000_GPIO2_RSVD 0x04 +#define AU1000_GPIO2_OUT 0x08 +#define AU1000_GPIO2_ST 0x0C +#define AU1000_GPIO2_INT 0x10 +#define AU1000_GPIO2_EN 0x14 +#define GPIO2_OUT_EN_MASK 0x00010000 -/* Wrappers for the arch-neutral GPIO API */ +#define gpio_to_irq(gpio) NULL -static inline int gpio_request(unsigned gpio, const char *label) -{ - /* Not yet implemented */ - return 0; -} +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value -static inline void gpio_free(unsigned gpio) -{ - /* Not yet implemented */ -} +#define gpio_cansleep __gpio_cansleep -static inline int gpio_direction_input(unsigned gpio) -{ - return au1xxx_gpio_direction_input(gpio); -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ - return au1xxx_gpio_direction_output(gpio, value); -} - -static inline int gpio_get_value(unsigned gpio) -{ - return au1xxx_gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - au1xxx_gpio_set_value(gpio, value); -} - -static inline int gpio_to_irq(unsigned gpio) -{ - return gpio; -} - -static inline int irq_to_gpio(unsigned irq) -{ - return irq; -} - -/* For cansleep */ #include <asm-generic/gpio.h> #endif /* _AU1XXX_GPIO_H_ */ diff --git a/arch/mips/include/asm/mach-bcm47xx/gpio.h b/arch/mips/include/asm/mach-bcm47xx/gpio.h index d8ff4cd89ab..1784fde2e28 100644 --- a/arch/mips/include/asm/mach-bcm47xx/gpio.h +++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h @@ -31,24 +31,28 @@ static inline void gpio_set_value(unsigned gpio, int value) static inline int gpio_direction_input(unsigned gpio) { - return ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 0); + ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 0); + return 0; } static inline int gpio_direction_output(unsigned gpio, int value) { - return ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 1 << gpio); + ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 1 << gpio); + return 0; } -static int gpio_intmask(unsigned gpio, int value) +static inline int gpio_intmask(unsigned gpio, int value) { - return ssb_gpio_intmask(&ssb_bcm47xx, 1 << gpio, - value ? 1 << gpio : 0); + ssb_gpio_intmask(&ssb_bcm47xx, 1 << gpio, + value ? 1 << gpio : 0); + return 0; } -static int gpio_polarity(unsigned gpio, int value) +static inline int gpio_polarity(unsigned gpio, int value) { - return ssb_gpio_polarity(&ssb_bcm47xx, 1 << gpio, - value ? 1 << gpio : 0); + ssb_gpio_polarity(&ssb_bcm47xx, 1 << gpio, + value ? 1 << gpio : 0); + return 0; } diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h index 55d481569a1..07547231e07 100644 --- a/arch/mips/include/asm/mach-ip27/topology.h +++ b/arch/mips/include/asm/mach-ip27/topology.h @@ -26,7 +26,6 @@ extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS]; #define parent_node(node) (node) #define node_to_cpumask(node) (hub_data(node)->h_cpus) #define cpumask_of_node(node) (&hub_data(node)->h_cpus) -#define node_to_first_cpu(node) (cpumask_first(cpumask_of_node(node))) struct pci_bus; extern int pcibus_to_node(struct pci_bus *); diff --git a/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h b/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h new file mode 100644 index 00000000000..550a10dc9db --- /dev/null +++ b/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h @@ -0,0 +1,59 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2009 Wu Zhangjin <wuzj@lemote.com> + * Copyright (C) 2009 Philippe Vachon <philippe@cowpig.ca> + * Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org> + * + * reference: /proc/cpuinfo, + * arch/mips/kernel/cpu-probe.c(cpu_probe_legacy), + * arch/mips/kernel/proc.c(show_cpuinfo), + * loongson2f user manual. + */ + +#ifndef __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 +#define cpu_scache_line_size() 32 + + +#define cpu_has_32fpr 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_4kex 1 +#define cpu_has_64bits 1 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_counter 1 +#define cpu_has_dc_aliases 1 +#define cpu_has_divec 0 +#define cpu_has_dsp 0 +#define cpu_has_ejtag 0 +#define cpu_has_fpu 1 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_inclusive_pcaches 1 +#define cpu_has_llsc 1 +#define cpu_has_mcheck 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips16 0 +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips3d 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 +#define cpu_has_mipsmt 0 +#define cpu_has_prefetch 0 +#define cpu_has_smartmips 0 +#define cpu_has_tlb 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_userlocal 0 +#define cpu_has_vce 0 +#define cpu_has_vtag_icache 0 +#define cpu_has_watch 1 +#define cpu_icache_snoops_remote_store 1 + +#endif /* __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h index 3cb50d17b62..12ee8d51016 100644 --- a/arch/mips/include/asm/mach-rc32434/gpio.h +++ b/arch/mips/include/asm/mach-rc32434/gpio.h @@ -80,6 +80,9 @@ struct rb532_gpio_reg { /* Compact Flash GPIO pin */ #define CF_GPIO_NUM 13 +/* S1 button GPIO (shared with UART0_SIN) */ +#define GPIO_BTN_S1 1 + extern void rb532_gpio_set_ilevel(int bit, unsigned gpio); extern void rb532_gpio_set_istat(int bit, unsigned gpio); extern void rb532_gpio_set_func(unsigned gpio); diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h index 7f0b034dd9a..c0da1a881e3 100644 --- a/arch/mips/include/asm/mips-boards/generic.h +++ b/arch/mips/include/asm/mips-boards/generic.h @@ -71,8 +71,6 @@ #define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) -extern int mips_revision_corid; - #define MIPS_REVISION_SCON_OTHER 0 #define MIPS_REVISION_SCON_SOCITSC 1 #define MIPS_REVISION_SCON_SOCITSCP 2 diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 0417516503f..32ef8bec5c8 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -184,12 +184,19 @@ #else #define PM_4K 0x00000000 +#define PM_8K 0x00002000 #define PM_16K 0x00006000 +#define PM_32K 0x0000e000 #define PM_64K 0x0001e000 +#define PM_128K 0x0003e000 #define PM_256K 0x0007e000 +#define PM_512K 0x000fe000 #define PM_1M 0x001fe000 +#define PM_2M 0x003fe000 #define PM_4M 0x007fe000 +#define PM_8M 0x00ffe000 #define PM_16M 0x01ffe000 +#define PM_32M 0x03ffe000 #define PM_64M 0x07ffe000 #define PM_256M 0x1fffe000 #define PM_1G 0x7fffe000 @@ -201,8 +208,12 @@ */ #ifdef CONFIG_PAGE_SIZE_4KB #define PM_DEFAULT_MASK PM_4K +#elif defined(CONFIG_PAGE_SIZE_8KB) +#define PM_DEFAULT_MASK PM_8K #elif defined(CONFIG_PAGE_SIZE_16KB) #define PM_DEFAULT_MASK PM_16K +#elif defined(CONFIG_PAGE_SIZE_32KB) +#define PM_DEFAULT_MASK PM_32K #elif defined(CONFIG_PAGE_SIZE_64KB) #define PM_DEFAULT_MASK PM_64K #else @@ -717,8 +728,8 @@ do { \ ".set\tmips64\n\t" \ "dmfc0\t%M0, " #source "\n\t" \ "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ + "dsra\t%M0, %M0, 32\n\t" \ + "dsra\t%L0, %L0, 32\n\t" \ ".set\tmips0" \ : "=r" (__val)); \ else \ @@ -726,8 +737,8 @@ do { \ ".set\tmips64\n\t" \ "dmfc0\t%M0, " #source ", " #sel "\n\t" \ "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ + "dsra\t%M0, %M0, 32\n\t" \ + "dsra\t%L0, %L0, 32\n\t" \ ".set\tmips0" \ : "=r" (__val)); \ local_irq_restore(__flags); \ @@ -1391,11 +1402,11 @@ static inline void tlb_write_random(void) static inline unsigned int \ set_c0_##name(unsigned int set) \ { \ - unsigned int res; \ + unsigned int res, new; \ \ res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ + new = res | set; \ + write_c0_##name(new); \ \ return res; \ } \ @@ -1403,24 +1414,24 @@ set_c0_##name(unsigned int set) \ static inline unsigned int \ clear_c0_##name(unsigned int clear) \ { \ - unsigned int res; \ + unsigned int res, new; \ \ res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ + new = res & ~clear; \ + write_c0_##name(new); \ \ return res; \ } \ \ static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int new) \ +change_c0_##name(unsigned int change, unsigned int val) \ { \ - unsigned int res; \ + unsigned int res, new; \ \ res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ + new = res & ~change; \ + new |= (val & change); \ + write_c0_##name(new); \ \ return res; \ } @@ -1484,14 +1495,15 @@ static inline unsigned int \ set_c0_##name(unsigned int set) \ { \ unsigned int res; \ + unsigned int new; \ unsigned int omt; \ unsigned long flags; \ \ local_irq_save(flags); \ omt = __dmt(); \ res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ + new = res | set; \ + write_c0_##name(new); \ __emt(omt); \ local_irq_restore(flags); \ \ @@ -1502,14 +1514,15 @@ static inline unsigned int \ clear_c0_##name(unsigned int clear) \ { \ unsigned int res; \ + unsigned int new; \ unsigned int omt; \ unsigned long flags; \ \ local_irq_save(flags); \ omt = __dmt(); \ res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ + new = res & ~clear; \ + write_c0_##name(new); \ __emt(omt); \ local_irq_restore(flags); \ \ @@ -1517,9 +1530,10 @@ clear_c0_##name(unsigned int clear) \ } \ \ static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int new) \ +change_c0_##name(unsigned int change, unsigned int newbits) \ { \ unsigned int res; \ + unsigned int new; \ unsigned int omt; \ unsigned long flags; \ \ @@ -1527,9 +1541,9 @@ change_c0_##name(unsigned int change, unsigned int new) \ \ omt = __dmt(); \ res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ + new = res & ~change; \ + new |= (newbits & change); \ + write_c0_##name(new); \ __emt(omt); \ local_irq_restore(flags); \ \ diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index fe7a88ea066..9f946e4ca05 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -23,6 +23,9 @@ #ifdef CONFIG_PAGE_SIZE_16KB #define PAGE_SHIFT 14 #endif +#ifdef CONFIG_PAGE_SIZE_32KB +#define PAGE_SHIFT 15 +#endif #ifdef CONFIG_PAGE_SIZE_64KB #define PAGE_SHIFT 16 #endif diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index 943515f0ef8..4ed9d1bba2b 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -83,6 +83,12 @@ #define PMD_ORDER 0 #define PTE_ORDER 0 #endif +#ifdef CONFIG_PAGE_SIZE_32KB +#define PGD_ORDER 0 +#define PUD_ORDER aieeee_attempt_to_allocate_pud +#define PMD_ORDER 0 +#define PTE_ORDER 0 +#endif #ifdef CONFIG_PAGE_SIZE_64KB #define PGD_ORDER 0 #define PUD_ORDER aieeee_attempt_to_allocate_pud diff --git a/arch/mips/include/asm/seccomp.h b/arch/mips/include/asm/seccomp.h index a6772e9507f..ae6306ebdca 100644 --- a/arch/mips/include/asm/seccomp.h +++ b/arch/mips/include/asm/seccomp.h @@ -15,8 +15,6 @@ */ #ifdef CONFIG_MIPS32_O32 -#define TIF_32BIT TIF_32BIT_REGS - #define __NR_seccomp_read_32 4003 #define __NR_seccomp_write_32 4004 #define __NR_seccomp_exit_32 4001 @@ -24,8 +22,6 @@ #elif defined(CONFIG_MIPS32_N32) -#define TIF_32BIT _TIF_32BIT_ADDR - #define __NR_seccomp_read_32 6000 #define __NR_seccomp_write_32 6001 #define __NR_seccomp_exit_32 6058 diff --git a/arch/mips/include/asm/sigcontext.h b/arch/mips/include/asm/sigcontext.h index 9ce0607d7a4..9e89cf99d4e 100644 --- a/arch/mips/include/asm/sigcontext.h +++ b/arch/mips/include/asm/sigcontext.h @@ -9,6 +9,7 @@ #ifndef _ASM_SIGCONTEXT_H #define _ASM_SIGCONTEXT_H +#include <linux/types.h> #include <asm/sgidefs.h> #if _MIPS_SIM == _MIPS_SIM_ABI32 diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h index 43c207e72a6..64ffc0290b8 100644 --- a/arch/mips/include/asm/smp-ops.h +++ b/arch/mips/include/asm/smp-ops.h @@ -15,6 +15,8 @@ #include <linux/cpumask.h> +struct task_struct; + struct plat_smp_ops { void (*send_ipi_single)(int cpu, unsigned int action); void (*send_ipi_mask)(cpumask_t mask, unsigned int action); diff --git a/arch/mips/include/asm/sn/addrs.h b/arch/mips/include/asm/sn/addrs.h index fec9bdd3491..3a56d90abfa 100644 --- a/arch/mips/include/asm/sn/addrs.h +++ b/arch/mips/include/asm/sn/addrs.h @@ -359,11 +359,11 @@ TO_NODE_UNCAC((nasid), LAUNCH_OFFSET(nasid, slice)) #define LAUNCH_SIZE(nasid) KLD_LAUNCH(nasid)->size -#define NMI_OFFSET(nasid, slice) \ +#define SN_NMI_OFFSET(nasid, slice) \ (KLD_NMI(nasid)->offset + \ KLD_NMI(nasid)->stride * (slice)) #define NMI_ADDR(nasid, slice) \ - TO_NODE_UNCAC((nasid), NMI_OFFSET(nasid, slice)) + TO_NODE_UNCAC((nasid), SN_NMI_OFFSET(nasid, slice)) #define NMI_SIZE(nasid) KLD_NMI(nasid)->size #define KLCONFIG_OFFSET(nasid) KLD_KLCONFIG(nasid)->offset diff --git a/arch/mips/include/asm/sn/nmi.h b/arch/mips/include/asm/sn/nmi.h index 6b7b0b5f372..1af49897d4e 100644 --- a/arch/mips/include/asm/sn/nmi.h +++ b/arch/mips/include/asm/sn/nmi.h @@ -3,13 +3,13 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * + * Derived from IRIX <sys/SN/nmi.h>, Revision 1.5. + * * Copyright (C) 1992 - 1997 Silicon Graphics, Inc. */ #ifndef __ASM_SN_NMI_H #define __ASM_SN_NMI_H -#ident "$Revision: 1.5 $" - #include <asm/sn/addrs.h> /* diff --git a/arch/mips/include/asm/socket.h b/arch/mips/include/asm/socket.h index facc2d7a87c..2abca178016 100644 --- a/arch/mips/include/asm/socket.h +++ b/arch/mips/include/asm/socket.h @@ -75,6 +75,9 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */ #define SO_MARK 36 +#define SO_TIMESTAMPING 37 +#define SCM_TIMESTAMPING SO_TIMESTAMPING + #ifdef __KERNEL__ /** sock_type - Socket types diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h index 0884947ebe2..5b60a09a0f0 100644 --- a/arch/mips/include/asm/spinlock.h +++ b/arch/mips/include/asm/spinlock.h @@ -76,7 +76,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock) "2: \n" " .subsection 2 \n" "4: andi %[ticket], %[ticket], 0x1fff \n" - "5: sll %[ticket], 5 \n" + " sll %[ticket], 5 \n" " \n" "6: bnez %[ticket], 6b \n" " subu %[ticket], 1 \n" @@ -85,7 +85,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock) " andi %[ticket], %[ticket], 0x1fff \n" " beq %[ticket], %[my_ticket], 2b \n" " subu %[ticket], %[my_ticket], %[ticket] \n" - " b 5b \n" + " b 4b \n" " subu %[ticket], %[ticket], 1 \n" " .previous \n" " .set pop \n" @@ -113,7 +113,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock) " ll %[ticket], %[ticket_ptr] \n" " \n" "4: andi %[ticket], %[ticket], 0x1fff \n" - "5: sll %[ticket], 5 \n" + " sll %[ticket], 5 \n" " \n" "6: bnez %[ticket], 6b \n" " subu %[ticket], 1 \n" @@ -122,7 +122,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock) " andi %[ticket], %[ticket], 0x1fff \n" " beq %[ticket], %[my_ticket], 2b \n" " subu %[ticket], %[my_ticket], %[ticket] \n" - " b 5b \n" + " b 4b \n" " subu %[ticket], %[ticket], 1 \n" " .previous \n" " .set pop \n" @@ -480,6 +480,8 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw) return ret; } +#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock) +#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock) #define _raw_spin_relax(lock) cpu_relax() #define _raw_read_relax(lock) cpu_relax() diff --git a/arch/mips/include/asm/swab.h b/arch/mips/include/asm/swab.h index 88f1f7d555c..99993c0d6c1 100644 --- a/arch/mips/include/asm/swab.h +++ b/arch/mips/include/asm/swab.h @@ -9,7 +9,7 @@ #define _ASM_SWAB_H #include <linux/compiler.h> -#include <asm/types.h> +#include <linux/types.h> #define __SWAB_64_THRU_32__ diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index 3f76de73c94..143a48136a4 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -75,6 +75,9 @@ register struct thread_info *__current_thread_info __asm__("$28"); #ifdef CONFIG_PAGE_SIZE_16KB #define THREAD_SIZE_ORDER (0) #endif +#ifdef CONFIG_PAGE_SIZE_32KB +#define THREAD_SIZE_ORDER (0) +#endif #ifdef CONFIG_PAGE_SIZE_64KB #define THREAD_SIZE_ORDER (0) #endif @@ -127,6 +130,12 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define TIF_LOAD_WATCH 25 /* If set, load watch registers */ #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ +#ifdef CONFIG_MIPS32_O32 +#define TIF_32BIT TIF_32BIT_REGS +#elif defined(CONFIG_MIPS32_N32) +#define TIF_32BIT _TIF_32BIT_ADDR +#endif /* CONFIG_MIPS32_O32 */ + #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index 38a30d2ee95..df6a430de5e 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -57,7 +57,11 @@ extern int r4k_clockevent_init(void); static inline int mips_clockevent_init(void) { -#ifdef CONFIG_CEVT_R4K +#ifdef CONFIG_MIPS_MT_SMTC + extern int smtc_clockevent_init(void); + + return smtc_clockevent_init(); +#elif defined(CONFIG_CEVT_R4K) return r4k_clockevent_init(); #else return -ENXIO; diff --git a/arch/mips/include/asm/txx9/ndfmc.h b/arch/mips/include/asm/txx9/ndfmc.h new file mode 100644 index 00000000000..fa67f3df78f --- /dev/null +++ b/arch/mips/include/asm/txx9/ndfmc.h @@ -0,0 +1,30 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * (C) Copyright TOSHIBA CORPORATION 2007 + */ +#ifndef __ASM_TXX9_NDFMC_H +#define __ASM_TXX9_NDFMC_H + +#define NDFMC_PLAT_FLAG_USE_BSPRT 0x01 +#define NDFMC_PLAT_FLAG_NO_RSTR 0x02 +#define NDFMC_PLAT_FLAG_HOLDADD 0x04 +#define NDFMC_PLAT_FLAG_DUMMYWRITE 0x08 + +struct txx9ndfmc_platform_data { + unsigned int shift; + unsigned int gbus_clock; + unsigned int hold; /* hold time in nanosecond */ + unsigned int spw; /* strobe pulse width in nanosecond */ + unsigned int flags; + unsigned char ch_mask; /* available channel bitmask */ + unsigned char wp_mask; /* write-protect bitmask */ + unsigned char wide_mask; /* 16bit-nand bitmask */ +}; + +void txx9_ndfmc_init(unsigned long baseaddr, + const struct txx9ndfmc_platform_data *plat_data); + +#endif /* __ASM_TXX9_NDFMC_H */ diff --git a/arch/mips/include/asm/txx9/rbtx4939.h b/arch/mips/include/asm/txx9/rbtx4939.h index 1acf428c0b4..e517899794a 100644 --- a/arch/mips/include/asm/txx9/rbtx4939.h +++ b/arch/mips/include/asm/txx9/rbtx4939.h @@ -130,4 +130,13 @@ void rbtx4939_prom_init(void); void rbtx4939_irq_setup(void); +struct mtd_partition; +struct map_info; +struct rbtx4939_flash_data { + unsigned int width; + unsigned int nr_parts; + struct mtd_partition *parts; + void (*map_init)(struct map_info *map); +}; + #endif /* __ASM_TXX9_RBTX4939_H */ diff --git a/arch/mips/include/asm/txx9/tx4938.h b/arch/mips/include/asm/txx9/tx4938.h index 0b068154054..cd8bc202175 100644 --- a/arch/mips/include/asm/txx9/tx4938.h +++ b/arch/mips/include/asm/txx9/tx4938.h @@ -291,6 +291,7 @@ int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot); void tx4938_setup_pcierr_irq(void); void tx4938_irq_init(void); void tx4938_mtd_init(int ch); +void tx4938_ndfmc_init(unsigned int hold, unsigned int spw); struct tx4938ide_platform_info { /* diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h index 964ef7ede26..f02c50b3abf 100644 --- a/arch/mips/include/asm/txx9/tx4939.h +++ b/arch/mips/include/asm/txx9/tx4939.h @@ -542,5 +542,7 @@ int tx4939_irq(void); void tx4939_mtd_init(int ch); void tx4939_ata_init(void); void tx4939_rtc_init(void); +void tx4939_ndfmc_init(unsigned int hold, unsigned int spw, + unsigned char ch_mask, unsigned char wide_mask); #endif /* __ASM_TXX9_TX4939_H */ diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h index bcbb8d675af..7956e69a3bd 100644 --- a/arch/mips/include/asm/types.h +++ b/arch/mips/include/asm/types.h @@ -4,12 +4,18 @@ * for more details. * * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle + * Copyright (C) 2008 Wind River Systems, + * written by Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. */ #ifndef _ASM_TYPES_H #define _ASM_TYPES_H -#if _MIPS_SZLONG == 64 +/* + * We don't use int-l64.h for the kernel anymore but still use it for + * userspace to avoid code changes. + */ +#if (_MIPS_SZLONG == 64) && !defined(__KERNEL__) # include <asm-generic/int-l64.h> #else # include <asm-generic/int-ll64.h> diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h index 09ff5bb1744..c2d53c18fd3 100644 --- a/arch/mips/include/asm/uaccess.h +++ b/arch/mips/include/asm/uaccess.h @@ -105,10 +105,20 @@ #define __access_mask get_fs().seg #define __access_ok(addr, size, mask) \ - (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0) +({ \ + unsigned long __addr = (unsigned long) (addr); \ + unsigned long __size = size; \ + unsigned long __mask = mask; \ + unsigned long __ok; \ + \ + __chk_user_ptr(addr); \ + __ok = (signed long)(__mask & (__addr | (__addr + __size) | \ + __ua_size(__size))); \ + __ok == 0; \ +}) #define access_ok(type, addr, size) \ - likely(__access_ok((unsigned long)(addr), (size), __access_mask)) + likely(__access_ok((addr), (size), __access_mask)) /* * put_user: - Write a simple value into user space. @@ -225,6 +235,7 @@ do { \ ({ \ int __gu_err; \ \ + __chk_user_ptr(ptr); \ __get_user_common((x), size, ptr); \ __gu_err; \ }) @@ -234,6 +245,7 @@ do { \ int __gu_err = -EFAULT; \ const __typeof__(*(ptr)) __user * __gu_ptr = (ptr); \ \ + might_fault(); \ if (likely(access_ok(VERIFY_READ, __gu_ptr, size))) \ __get_user_common((x), size, __gu_ptr); \ \ @@ -305,6 +317,7 @@ do { \ __typeof__(*(ptr)) __pu_val; \ int __pu_err = 0; \ \ + __chk_user_ptr(ptr); \ __pu_val = (x); \ switch (size) { \ case 1: __put_user_asm("sb", ptr); break; \ @@ -322,6 +335,7 @@ do { \ __typeof__(*(ptr)) __pu_val = (x); \ int __pu_err = -EFAULT; \ \ + might_fault(); \ if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) { \ switch (size) { \ case 1: __put_user_asm("sb", __pu_addr); break; \ @@ -696,10 +710,10 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); const void *__cu_from; \ long __cu_len; \ \ - might_sleep(); \ __cu_to = (to); \ __cu_from = (from); \ __cu_len = (n); \ + might_fault(); \ __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \ __cu_len; \ }) @@ -752,13 +766,14 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); const void *__cu_from; \ long __cu_len; \ \ - might_sleep(); \ __cu_to = (to); \ __cu_from = (from); \ __cu_len = (n); \ - if (access_ok(VERIFY_WRITE, __cu_to, __cu_len)) \ + if (access_ok(VERIFY_WRITE, __cu_to, __cu_len)) { \ + might_fault(); \ __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, \ __cu_len); \ + } \ __cu_len; \ }) @@ -831,10 +846,10 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); const void __user *__cu_from; \ long __cu_len; \ \ - might_sleep(); \ __cu_to = (to); \ __cu_from = (from); \ __cu_len = (n); \ + might_fault(); \ __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ __cu_len); \ __cu_len; \ @@ -862,17 +877,31 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); const void __user *__cu_from; \ long __cu_len; \ \ - might_sleep(); \ __cu_to = (to); \ __cu_from = (from); \ __cu_len = (n); \ - if (access_ok(VERIFY_READ, __cu_from, __cu_len)) \ + if (access_ok(VERIFY_READ, __cu_from, __cu_len)) { \ + might_fault(); \ __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ __cu_len); \ + } \ __cu_len; \ }) -#define __copy_in_user(to, from, n) __copy_from_user(to, from, n) +#define __copy_in_user(to, from, n) \ +({ \ + void __user *__cu_to; \ + const void __user *__cu_from; \ + long __cu_len; \ + \ + __cu_to = (to); \ + __cu_from = (from); \ + __cu_len = (n); \ + might_fault(); \ + __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ + __cu_len); \ + __cu_len; \ +}) #define copy_in_user(to, from, n) \ ({ \ @@ -880,14 +909,15 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n); const void __user *__cu_from; \ long __cu_len; \ \ - might_sleep(); \ __cu_to = (to); \ __cu_from = (from); \ __cu_len = (n); \ if (likely(access_ok(VERIFY_READ, __cu_from, __cu_len) && \ - access_ok(VERIFY_WRITE, __cu_to, __cu_len))) \ + access_ok(VERIFY_WRITE, __cu_to, __cu_len))) { \ + might_fault(); \ __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ __cu_len); \ + } \ __cu_len; \ }) @@ -907,7 +937,7 @@ __clear_user(void __user *addr, __kernel_size_t size) { __kernel_size_t res; - might_sleep(); + might_fault(); __asm__ __volatile__( "move\t$4, %1\n\t" "move\t$5, $0\n\t" @@ -926,7 +956,7 @@ __clear_user(void __user *addr, __kernel_size_t size) void __user * __cl_addr = (addr); \ unsigned long __cl_size = (n); \ if (__cl_size && access_ok(VERIFY_WRITE, \ - ((unsigned long)(__cl_addr)), __cl_size)) \ + __cl_addr, __cl_size)) \ __cl_size = __clear_user(__cl_addr, __cl_size); \ __cl_size; \ }) @@ -956,7 +986,7 @@ __strncpy_from_user(char *__to, const char __user *__from, long __len) { long res; - might_sleep(); + might_fault(); __asm__ __volatile__( "move\t$4, %1\n\t" "move\t$5, %2\n\t" @@ -993,7 +1023,7 @@ strncpy_from_user(char *__to, const char __user *__from, long __len) { long res; - might_sleep(); + might_fault(); __asm__ __volatile__( "move\t$4, %1\n\t" "move\t$5, %2\n\t" @@ -1012,7 +1042,7 @@ static inline long __strlen_user(const char __user *s) { long res; - might_sleep(); + might_fault(); __asm__ __volatile__( "move\t$4, %1\n\t" __MODULE_JAL(__strlen_user_nocheck_asm) @@ -1042,7 +1072,7 @@ static inline long strlen_user(const char __user *s) { long res; - might_sleep(); + might_fault(); __asm__ __volatile__( "move\t$4, %1\n\t" __MODULE_JAL(__strlen_user_asm) @@ -1059,7 +1089,7 @@ static inline long __strnlen_user(const char __user *s, long n) { long res; - might_sleep(); + might_fault(); __asm__ __volatile__( "move\t$4, %1\n\t" "move\t$5, %2\n\t" @@ -1090,7 +1120,7 @@ static inline long strnlen_user(const char __user *s, long n) { long res; - might_sleep(); + might_fault(); __asm__ __volatile__( "move\t$4, %1\n\t" "move\t$5, %2\n\t" diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h index a73e1531e15..40005010827 100644 --- a/arch/mips/include/asm/unistd.h +++ b/arch/mips/include/asm/unistd.h @@ -350,16 +350,18 @@ #define __NR_dup3 (__NR_Linux + 327) #define __NR_pipe2 (__NR_Linux + 328) #define __NR_inotify_init1 (__NR_Linux + 329) +#define __NR_preadv (__NR_Linux + 330) +#define __NR_pwritev (__NR_Linux + 331) /* * Offset of the last Linux o32 flavoured syscall */ -#define __NR_Linux_syscalls 329 +#define __NR_Linux_syscalls 331 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ #define __NR_O32_Linux 4000 -#define __NR_O32_Linux_syscalls 329 +#define __NR_O32_Linux_syscalls 331 #if _MIPS_SIM == _MIPS_SIM_ABI64 @@ -656,16 +658,18 @@ #define __NR_dup3 (__NR_Linux + 286) #define __NR_pipe2 (__NR_Linux + 287) #define __NR_inotify_init1 (__NR_Linux + 288) +#define __NR_preadv (__NR_Linux + 289) +#define __NR_pwritev (__NR_Linux + 290) /* * Offset of the last Linux 64-bit flavoured syscall */ -#define __NR_Linux_syscalls 288 +#define __NR_Linux_syscalls 290 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ #define __NR_64_Linux 5000 -#define __NR_64_Linux_syscalls 288 +#define __NR_64_Linux_syscalls 290 #if _MIPS_SIM == _MIPS_SIM_NABI32 @@ -966,16 +970,18 @@ #define __NR_dup3 (__NR_Linux + 290) #define __NR_pipe2 (__NR_Linux + 291) #define __NR_inotify_init1 (__NR_Linux + 292) +#define __NR_preadv (__NR_Linux + 293) +#define __NR_pwritev (__NR_Linux + 294) /* * Offset of the last N32 flavoured syscall */ -#define __NR_Linux_syscalls 292 +#define __NR_Linux_syscalls 294 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ #define __NR_N32_Linux 6000 -#define __NR_N32_Linux_syscalls 292 +#define __NR_N32_Linux_syscalls 294 #ifdef __KERNEL__ diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index 03965cb1b25..d9b6a5b5399 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c @@ -134,7 +134,6 @@ static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id) static struct irqaction r4030_timer_irqaction = { .handler = r4030_timer_interrupt, .flags = IRQF_DISABLED, - .mask = CPU_MASK_CPU0, .name = "R4030 timer", }; diff --git a/arch/mips/jazz/jazzdma.c b/arch/mips/jazz/jazzdma.c index c672c08d49e..f0fd636723b 100644 --- a/arch/mips/jazz/jazzdma.c +++ b/arch/mips/jazz/jazzdma.c @@ -68,8 +68,7 @@ static int __init vdma_init(void) */ pgtbl = (VDMA_PGTBL_ENTRY *)__get_free_pages(GFP_KERNEL | GFP_DMA, get_order(VDMA_PGTBL_SIZE)); - if (!pgtbl) - BUG(); + BUG_ON(!pgtbl); dma_cache_wback_inv((unsigned long)pgtbl, VDMA_PGTBL_SIZE); pgtbl = (VDMA_PGTBL_ENTRY *)KSEG1ADDR(pgtbl); diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c index b820661678b..a5182a20769 100644 --- a/arch/mips/kernel/cevt-bcm1480.c +++ b/arch/mips/kernel/cevt-bcm1480.c @@ -144,7 +144,6 @@ void __cpuinit sb1480_clockevent_init(void) action->handler = sibyte_counter_handler; action->flags = IRQF_DISABLED | IRQF_PERCPU; - action->mask = cpumask_of_cpu(cpu); action->name = name; action->dev_id = cd; diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c index a2eebaafda5..340f53e5c6b 100644 --- a/arch/mips/kernel/cevt-sb1250.c +++ b/arch/mips/kernel/cevt-sb1250.c @@ -143,7 +143,6 @@ void __cpuinit sb1250_clockevent_init(void) action->handler = sibyte_counter_handler; action->flags = IRQF_DISABLED | IRQF_PERCPU; - action->mask = cpumask_of_cpu(cpu); action->name = name; action->dev_id = cd; diff --git a/arch/mips/kernel/cevt-smtc.c b/arch/mips/kernel/cevt-smtc.c index 6d45e24db5b..df6f5bc6057 100644 --- a/arch/mips/kernel/cevt-smtc.c +++ b/arch/mips/kernel/cevt-smtc.c @@ -245,7 +245,7 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id) } -int __cpuinit mips_clockevent_init(void) +int __cpuinit smtc_clockevent_init(void) { uint64_t mips_freq = mips_hpt_frequency; unsigned int cpu = smp_processor_id(); diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c index eccf7d6096b..2e911e3da8d 100644 --- a/arch/mips/kernel/cevt-txx9.c +++ b/arch/mips/kernel/cevt-txx9.c @@ -22,7 +22,7 @@ static struct txx9_tmr_reg __iomem *txx9_cs_tmrptr; -static cycle_t txx9_cs_read(void) +static cycle_t txx9_cs_read(struct clocksource *cs) { return __raw_readl(&txx9_cs_tmrptr->trr); } diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 1bdbcad3bb7..b13b8eb3059 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -183,13 +183,7 @@ void __init check_wait(void) case CPU_TX49XX: cpu_wait = r4k_wait_irqoff; break; - case CPU_AU1000: - case CPU_AU1100: - case CPU_AU1500: - case CPU_AU1550: - case CPU_AU1200: - case CPU_AU1210: - case CPU_AU1250: + case CPU_ALCHEMY: cpu_wait = au1k_wait; break; case CPU_20KC: @@ -783,37 +777,30 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) switch (c->processor_id & 0xff00) { case PRID_IMP_AU1_REV1: case PRID_IMP_AU1_REV2: + c->cputype = CPU_ALCHEMY; switch ((c->processor_id >> 24) & 0xff) { case 0: - c->cputype = CPU_AU1000; __cpu_name[cpu] = "Au1000"; break; case 1: - c->cputype = CPU_AU1500; __cpu_name[cpu] = "Au1500"; break; case 2: - c->cputype = CPU_AU1100; __cpu_name[cpu] = "Au1100"; break; case 3: - c->cputype = CPU_AU1550; __cpu_name[cpu] = "Au1550"; break; case 4: - c->cputype = CPU_AU1200; __cpu_name[cpu] = "Au1200"; - if ((c->processor_id & 0xff) == 2) { - c->cputype = CPU_AU1250; + if ((c->processor_id & 0xff) == 2) __cpu_name[cpu] = "Au1250"; - } break; case 5: - c->cputype = CPU_AU1210; __cpu_name[cpu] = "Au1210"; break; default: - panic("Unknown Au Core!"); + __cpu_name[cpu] = "Au1xxx"; break; } break; diff --git a/arch/mips/kernel/csrc-bcm1480.c b/arch/mips/kernel/csrc-bcm1480.c index 868745e7184..51489f8a825 100644 --- a/arch/mips/kernel/csrc-bcm1480.c +++ b/arch/mips/kernel/csrc-bcm1480.c @@ -28,7 +28,7 @@ #include <asm/sibyte/sb1250.h> -static cycle_t bcm1480_hpt_read(void) +static cycle_t bcm1480_hpt_read(struct clocksource *cs) { return (cycle_t) __raw_readq(IOADDR(A_SCD_ZBBUS_CYCLE_COUNT)); } diff --git a/arch/mips/kernel/csrc-ioasic.c b/arch/mips/kernel/csrc-ioasic.c index 1d5f63cf899..b551f48d3a0 100644 --- a/arch/mips/kernel/csrc-ioasic.c +++ b/arch/mips/kernel/csrc-ioasic.c @@ -25,7 +25,7 @@ #include <asm/dec/ioasic.h> #include <asm/dec/ioasic_addrs.h> -static cycle_t dec_ioasic_hpt_read(void) +static cycle_t dec_ioasic_hpt_read(struct clocksource *cs) { return ioasic_read(IO_REG_FCTR); } @@ -47,13 +47,13 @@ void __init dec_ioasic_clocksource_init(void) while (!ds1287_timer_state()) ; - start = dec_ioasic_hpt_read(); + start = dec_ioasic_hpt_read(&clocksource_dec); while (i--) while (!ds1287_timer_state()) ; - end = dec_ioasic_hpt_read(); + end = dec_ioasic_hpt_read(&clocksource_dec); freq = (end - start) * 10; printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq); diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index f1a2893931e..e95a3cd48ee 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -10,7 +10,7 @@ #include <asm/time.h> -static cycle_t c0_hpt_read(void) +static cycle_t c0_hpt_read(struct clocksource *cs) { return read_c0_count(); } diff --git a/arch/mips/kernel/csrc-sb1250.c b/arch/mips/kernel/csrc-sb1250.c index 92212bbb8e4..d14d3d1907f 100644 --- a/arch/mips/kernel/csrc-sb1250.c +++ b/arch/mips/kernel/csrc-sb1250.c @@ -33,7 +33,7 @@ * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over * again. */ -static cycle_t sb1250_hpt_read(void) +static cycle_t sb1250_hpt_read(struct clocksource *cs) { unsigned int count; diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c index f4d187825f9..ed20e7fe65e 100644 --- a/arch/mips/kernel/i8253.c +++ b/arch/mips/kernel/i8253.c @@ -98,7 +98,6 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id) static struct irqaction irq0 = { .handler = timer_interrupt, .flags = IRQF_DISABLED | IRQF_NOBALANCING, - .mask = CPU_MASK_NONE, .name = "timer" }; @@ -121,7 +120,6 @@ void __init setup_pit_timer(void) cd->min_delta_ns = clockevent_delta2ns(0xF, cd); clockevents_register_device(cd); - irq0.mask = cpumask_of_cpu(cpu); setup_irq(0, &irq0); } @@ -130,7 +128,7 @@ void __init setup_pit_timer(void) * to just read by itself. So use jiffies to emulate a free * running counter: */ -static cycle_t pit_read(void) +static cycle_t pit_read(struct clocksource *cs) { unsigned long flags; int count; diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index 413bd1d37f5..01c0885a806 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c @@ -306,7 +306,6 @@ static void init_8259A(int auto_eoi) */ static struct irqaction irq2 = { .handler = no_action, - .mask = CPU_MASK_NONE, .name = "cascade", }; diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index 494a49a317e..87deb8f6c45 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c @@ -187,7 +187,7 @@ static void gic_set_affinity(unsigned int irq, const struct cpumask *cpumask) set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask); } - irq_desc[irq].affinity = *cpumask; + cpumask_copy(irq_desc[irq].affinity, cpumask); spin_unlock_irqrestore(&gic_lock, flags); } diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index 963c16d266a..6a8cd28133d 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c @@ -140,14 +140,16 @@ void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqma switch (imp->im_type) { case MSC01_IRQ_EDGE: - set_irq_chip(irqbase+n, &msc_edgeirq_type); + set_irq_chip_and_handler_name(irqbase + n, + &msc_edgeirq_type, handle_edge_irq, "edge"); if (cpu_has_veic) MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); else MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); break; case MSC01_IRQ_LEVEL: - set_irq_chip(irqbase+n, &msc_levelirq_type); + set_irq_chip_and_handler_name(irqbase+n, + &msc_levelirq_type, handle_level_irq, "level"); if (cpu_has_veic) MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); else diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 4b4007b3083..7b845ba9dff 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -108,7 +108,7 @@ int show_interrupts(struct seq_file *p, void *v) seq_printf(p, "%10u ", kstat_irqs(i)); #else for_each_online_cpu(j) - seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); + seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); #endif seq_printf(p, " %14s", irq_desc[i].chip->name); seq_printf(p, " %s", action->name); diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 0ee2567b780..55c8a3ca507 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c @@ -112,7 +112,8 @@ void __init mips_cpu_irq_init(void) */ if (cpu_has_mipsmt) for (i = irq_base; i < irq_base + 2; i++) - set_irq_chip(i, &mips_mt_cpu_irq_controller); + set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller, + handle_percpu_irq); for (i = irq_base + 2; i < irq_base + 8; i++) set_irq_chip_and_handler(i, &mips_cpu_irq_controller, diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index 1a86f84fa94..6242bc68add 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c @@ -32,7 +32,6 @@ #include <linux/module.h> #include <linux/binfmts.h> #include <linux/security.h> -#include <linux/syscalls.h> #include <linux/compat.h> #include <linux/vfs.h> #include <linux/ipc.h> @@ -134,9 +133,9 @@ SYSCALL_DEFINE4(32_ftruncate64, unsigned long, fd, unsigned long, __dummy, return sys_ftruncate(fd, merge_64(a2, a3)); } -SYSCALL_DEFINE5(32_llseek, unsigned long, fd, unsigned long, offset_high, - unsigned long, offset_low, loff_t __user *, result, - unsigned long, origin) +SYSCALL_DEFINE5(32_llseek, unsigned int, fd, unsigned int, offset_high, + unsigned int, offset_low, loff_t __user *, result, + unsigned int, origin) { return sys_llseek(fd, offset_high, offset_low, result, origin); } @@ -356,40 +355,6 @@ SYSCALL_DEFINE1(32_personality, unsigned long, personality) return ret; } -/* ustat compatibility */ -struct ustat32 { - compat_daddr_t f_tfree; - compat_ino_t f_tinode; - char f_fname[6]; - char f_fpack[6]; -}; - -extern asmlinkage long sys_ustat(dev_t dev, struct ustat __user * ubuf); - -SYSCALL_DEFINE2(32_ustat, dev_t, dev, struct ustat32 __user *, ubuf32) -{ - int err; - struct ustat tmp; - struct ustat32 tmp32; - mm_segment_t old_fs = get_fs(); - - set_fs(KERNEL_DS); - err = sys_ustat(dev, (struct ustat __user *)&tmp); - set_fs(old_fs); - - if (err) - goto out; - - memset(&tmp32, 0, sizeof(struct ustat32)); - tmp32.f_tfree = tmp.f_tfree; - tmp32.f_tinode = tmp.f_tinode; - - err = copy_to_user(ubuf32, &tmp32, sizeof(struct ustat32)) ? -EFAULT : 0; - -out: - return err; -} - SYSCALL_DEFINE4(32_sendfile, long, out_fd, long, in_fd, compat_off_t __user *, offset, s32, count) { diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 26760cad8b6..e0a4ac18fa0 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -42,7 +42,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, fmt, __cpu_name[n], (version >> 4) & 0x0f, version & 0x0f, (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); - seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n", + seq_printf(m, "BogoMIPS\t\t: %u.%02u\n", cpu_data[n].udelay_val / (500000/HZ), (cpu_data[n].udelay_val / (5000/HZ)) % 100); seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index ca2e4026ad2..1eaaa450e20 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -99,7 +99,7 @@ void flush_thread(void) { } -int copy_thread(int nr, unsigned long clone_flags, unsigned long usp, +int copy_thread(unsigned long clone_flags, unsigned long usp, unsigned long unused, struct task_struct *p, struct pt_regs *regs) { struct thread_info *ti = task_thread_info(p); diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index 9ab70c3b5be..0b31b9bda04 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -650,6 +650,8 @@ einval: li v0, -ENOSYS sys sys_dup3 3 sys sys_pipe2 2 sys sys_inotify_init1 1 + sys sys_preadv 6 /* 4330 */ + sys sys_pwritev 6 .endm /* We pre-compute the number of _instruction_ bytes needed to diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 9b469866715..c647fd6e722 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -487,4 +487,6 @@ sys_call_table: PTR sys_dup3 PTR sys_pipe2 PTR sys_inotify_init1 + PTR sys_preadv + PTR sys_pwritev /* 5390 */ .size sys_call_table,.-sys_call_table diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index 7438e92f8a0..93cc672f452 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -253,7 +253,7 @@ EXPORT(sysn32_call_table) PTR compat_sys_utime /* 6130 */ PTR sys_mknod PTR sys_32_personality - PTR sys_32_ustat + PTR compat_sys_ustat PTR compat_sys_statfs PTR compat_sys_fstatfs /* 6135 */ PTR sys_sysfs @@ -405,12 +405,14 @@ EXPORT(sysn32_call_table) PTR sys_eventfd PTR sys_fallocate PTR sys_timerfd_create - PTR sys_timerfd_gettime /* 5285 */ - PTR sys_timerfd_settime + PTR compat_sys_timerfd_gettime /* 5285 */ + PTR compat_sys_timerfd_settime PTR sys_signalfd4 PTR sys_eventfd2 PTR sys_epoll_create1 PTR sys_dup3 /* 5290 */ PTR sys_pipe2 PTR sys_inotify_init1 + PTR sys_preadv + PTR sys_pwritev .size sysn32_call_table,.-sysn32_call_table diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index b0fef4ff982..a5598b2339d 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -265,7 +265,7 @@ sys_call_table: PTR sys_olduname PTR sys_umask /* 4060 */ PTR sys_chroot - PTR sys_32_ustat + PTR compat_sys_ustat PTR sys_dup2 PTR sys_getppid PTR sys_getpgrp /* 4065 */ @@ -525,12 +525,14 @@ sys_call_table: PTR sys_eventfd PTR sys32_fallocate /* 4320 */ PTR sys_timerfd_create - PTR sys_timerfd_gettime - PTR sys_timerfd_settime + PTR compat_sys_timerfd_gettime + PTR compat_sys_timerfd_settime PTR compat_sys_signalfd4 PTR sys_eventfd2 /* 4325 */ PTR sys_epoll_create1 PTR sys_dup3 PTR sys_pipe2 PTR sys_inotify_init1 + PTR compat_sys_preadv /* 4330 */ + PTR compat_sys_pwritev .size sys_call_table,.-sys_call_table diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 4430a1f8fdf..2950b97253b 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -277,7 +277,8 @@ static void __init bootmem_init(void) * not selected. Once that done we can determine the low bound * of usable memory. */ - reserved_end = max(init_initrd(), PFN_UP(__pa_symbol(&_end))); + reserved_end = max(init_initrd(), + (unsigned long) PFN_UP(__pa_symbol(&_end))); /* * max_low_pfn is not a number of pages. The number of pages diff --git a/arch/mips/kernel/smp-up.c b/arch/mips/kernel/smp-up.c index ead6c30eeb1..878e3733bbb 100644 --- a/arch/mips/kernel/smp-up.c +++ b/arch/mips/kernel/smp-up.c @@ -13,7 +13,7 @@ /* * Send inter-processor interrupt */ -void up_send_ipi_single(int cpu, unsigned int action) +static void up_send_ipi_single(int cpu, unsigned int action) { panic(KERN_ERR "%s called", __func__); } @@ -27,31 +27,31 @@ static inline void up_send_ipi_mask(cpumask_t mask, unsigned int action) * After we've done initial boot, this function is called to allow the * board code to clean up state, if needed */ -void __cpuinit up_init_secondary(void) +static void __cpuinit up_init_secondary(void) { } -void __cpuinit up_smp_finish(void) +static void __cpuinit up_smp_finish(void) { } /* Hook for after all CPUs are online */ -void up_cpus_done(void) +static void up_cpus_done(void) { } /* * Firmware CPU startup hook */ -void __cpuinit up_boot_secondary(int cpu, struct task_struct *idle) +static void __cpuinit up_boot_secondary(int cpu, struct task_struct *idle) { } -void __init up_smp_setup(void) +static void __init up_smp_setup(void) { } -void __init up_prepare_cpus(unsigned int max_cpus) +static void __init up_prepare_cpus(unsigned int max_cpus) { } diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 3da94704f81..c937506a03a 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -44,7 +44,7 @@ #include <asm/mipsmtregs.h> #endif /* CONFIG_MIPS_MT_SMTC */ -volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ +static volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index b6cca01ff82..5f5af7d4c89 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -686,7 +686,7 @@ void smtc_forward_irq(unsigned int irq) * and efficiency, we just pick the easiest one to find. */ - target = first_cpu(irq_desc[irq].affinity); + target = cpumask_first(irq_desc[irq].affinity); /* * We depend on the platform code to have correctly processed @@ -921,11 +921,13 @@ void ipi_decode(struct smtc_ipi *pipi) struct clock_event_device *cd; void *arg_copy = pipi->arg; int type_copy = pipi->type; + int irq = MIPS_CPU_IRQ_BASE + 1; + smtc_ipi_nq(&freeIPIq, pipi); switch (type_copy) { case SMTC_CLOCK_TICK: irq_enter(); - kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + 1]++; + kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); cd = &per_cpu(mips_clockevent_device, cpu); cd->event_handler(cd); irq_exit(); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index b2d7041341b..e83da174b53 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1277,8 +1277,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) u32 *w; unsigned char *b; - if (!cpu_has_veic && !cpu_has_vint) - BUG(); + BUG_ON(!cpu_has_veic && !cpu_has_vint); if (addr == NULL) { handler = (unsigned long) do_default_vi; @@ -1520,7 +1519,9 @@ void __cpuinit per_cpu_trap_init(void) #endif /* CONFIG_MIPS_MT_SMTC */ if (cpu_has_veic || cpu_has_vint) { + unsigned long sr = set_c0_status(ST0_BEV); write_c0_ebase(ebase); + write_c0_status(sr); /* Setting vector spacing enables EI/VI mode */ change_c0_intctl(0x3e0, VECTORSPACING); } @@ -1602,8 +1603,6 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr, #ifdef CONFIG_64BIT unsigned long uncached_ebase = TO_UNCAC(ebase); #endif - if (cpu_has_mips_r2) - uncached_ebase += (read_c0_ebase() & 0x3ffff000); if (!addr) panic(panic_null_cerr); @@ -1635,9 +1634,11 @@ void __init trap_init(void) return; /* Already done */ #endif - if (cpu_has_veic || cpu_has_vint) - ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); - else { + if (cpu_has_veic || cpu_has_vint) { + unsigned long size = 0x200 + VECTORSPACING*64; + ebase = (unsigned long) + __alloc_bootmem(size, 1 << fls(size), 0); + } else { ebase = CAC_BASE; if (cpu_has_mips_r2) ebase += (read_c0_ebase() & 0x3ffff000); diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index bf4c4a979ab..67bd626942a 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -482,19 +482,19 @@ fault: return; die_if_kernel("Unhandled kernel unaligned access", regs); - send_sig(SIGSEGV, current, 1); + force_sig(SIGSEGV, current); return; sigbus: die_if_kernel("Unhandled kernel unaligned access", regs); - send_sig(SIGBUS, current, 1); + force_sig(SIGBUS, current); return; sigill: die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs); - send_sig(SIGILL, current, 1); + force_sig(SIGILL, current); } asmlinkage void do_ade(struct pt_regs *regs) diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c index d1ac7a25c85..1353fb135ed 100644 --- a/arch/mips/lasat/interrupt.c +++ b/arch/mips/lasat/interrupt.c @@ -104,7 +104,6 @@ asmlinkage void plat_irq_dispatch(void) static struct irqaction cascade = { .handler = no_action, - .mask = CPU_MASK_NONE, .name = "cascade", }; diff --git a/arch/mips/lemote/lm2e/irq.c b/arch/mips/lemote/lm2e/irq.c index 3e0b7beb100..1d0a09f3b83 100644 --- a/arch/mips/lemote/lm2e/irq.c +++ b/arch/mips/lemote/lm2e/irq.c @@ -92,7 +92,6 @@ asmlinkage void plat_irq_dispatch(void) static struct irqaction cascade_irqaction = { .handler = no_action, - .mask = CPU_MASK_NONE, .name = "cascade", }; diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index c13c7ad2cda..2adead5a8a3 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -2,8 +2,8 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial.o memcpy.o memcpy-inatomic.o memset.o strlen_user.o \ - strncpy_user.o strnlen_user.o uncached.o +lib-y += csum_partial.o delay.o memcpy.o memcpy-inatomic.o memset.o \ + strlen_user.o strncpy_user.o strnlen_user.o uncached.o obj-y += iomap.o obj-$(CONFIG_PCI) += iomap-pci.o diff --git a/arch/mips/lib/delay.c b/arch/mips/lib/delay.c new file mode 100644 index 00000000000..f69c6b569eb --- /dev/null +++ b/arch/mips/lib/delay.c @@ -0,0 +1,56 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 by Waldorf Electronics + * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 2007 Maciej W. Rozycki + */ +#include <linux/module.h> +#include <linux/param.h> +#include <linux/smp.h> + +#include <asm/compiler.h> +#include <asm/war.h> + +inline void __delay(unsigned int loops) +{ + __asm__ __volatile__ ( + " .set noreorder \n" + " .align 3 \n" + "1: bnez %0, 1b \n" + " subu %0, 1 \n" + " .set reorder \n" + : "=r" (loops) + : "0" (loops)); +} +EXPORT_SYMBOL(__delay); + +/* + * Division by multiplication: you don't have to worry about + * loss of precision. + * + * Use only for very small delays ( < 1 msec). Should probably use a + * lookup table, really, as the multiplications take much too long with + * short delays. This is a "reasonable" implementation, though (and the + * first constant multiplications gets optimized away if the delay is + * a constant) + */ + +void __udelay(unsigned long us) +{ + unsigned int lpj = current_cpu_data.udelay_val; + + __delay((us * 0x000010c7 * HZ * lpj) >> 32); +} +EXPORT_SYMBOL(__udelay); + +void __ndelay(unsigned long ns) +{ + unsigned int lpj = current_cpu_data.udelay_val; + + __delay((us * 0x00000005 * HZ * lpj) >> 32); +} +EXPORT_SYMBOL(__ndelay); diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c index 779821cd54a..3f69725556a 100644 --- a/arch/mips/lib/dump_tlb.c +++ b/arch/mips/lib/dump_tlb.c @@ -19,6 +19,15 @@ static inline const char *msk2str(unsigned int mask) case PM_16K: return "16kb"; case PM_64K: return "64kb"; case PM_256K: return "256kb"; +#ifdef CONFIG_CPU_CAVIUM_OCTEON + case PM_8K: return "8kb"; + case PM_32K: return "32kb"; + case PM_128K: return "128kb"; + case PM_512K: return "512kb"; + case PM_2M: return "2Mb"; + case PM_8M: return "8Mb"; + case PM_32M: return "32Mb"; +#endif #ifndef CONFIG_CPU_VR41XX case PM_1M: return "1Mb"; case PM_4M: return "4Mb"; diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index c43f4b26a69..171951d2305 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -780,7 +780,7 @@ static void __cpuinit probe_pcache(void) c->dcache.ways = 2; c->dcache.waybit = 0; - c->options |= MIPS_CPU_CACHE_CDEX_P; + c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; break; case CPU_TX49XX: @@ -1026,13 +1026,7 @@ static void __cpuinit probe_pcache(void) c->icache.flags |= MIPS_CACHE_VTAG; break; - case CPU_AU1000: - case CPU_AU1500: - case CPU_AU1100: - case CPU_AU1550: - case CPU_AU1200: - case CPU_AU1210: - case CPU_AU1250: + case CPU_ALCHEMY: c->icache.flags |= MIPS_CACHE_IC_F_DC; break; } @@ -1047,7 +1041,7 @@ static void __cpuinit probe_pcache(void) printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", icache_size >> 10, - cpu_has_vtag_icache ? "VIVT" : "VIPT", + c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", way_string[c->icache.ways], c->icache.linesz); printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", @@ -1244,7 +1238,7 @@ void au1x00_fixup_config_od(void) /* * Au1100 errata actually keeps silence about this bit, so we set it * just in case for those revisions that require it to be set according - * to arch/mips/au1000/common/cputable.c + * to the (now gone) cpu table. */ case 0x02030200: /* Au1100 AB */ case 0x02030201: /* Au1100 BA */ @@ -1314,11 +1308,10 @@ static void __cpuinit coherency_setup(void) break; /* * We need to catch the early Alchemy SOCs with - * the write-only co_config.od bit and set it back to one... + * the write-only co_config.od bit and set it back to one on: + * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB */ - case CPU_AU1000: /* rev. DA, HA, HB */ - case CPU_AU1100: /* rev. AB, BA, BC ?? */ - case CPU_AU1500: /* rev. AB */ + case CPU_ALCHEMY: au1x00_fixup_config_od(); break; diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 546e6977d4f..4fdb7f5216b 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -209,7 +209,7 @@ dma_addr_t dma_map_page(struct device *dev, struct page *page, unsigned long addr; addr = (unsigned long) page_address(page) + offset; - dma_cache_wback_inv(addr, size); + __dma_sync(addr, size, direction); } return plat_map_dma_mem_page(dev, page) + offset; @@ -217,23 +217,6 @@ dma_addr_t dma_map_page(struct device *dev, struct page *page, EXPORT_SYMBOL(dma_map_page); -void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, - enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); - - if (!plat_device_is_coherent(dev) && direction != DMA_TO_DEVICE) { - unsigned long addr; - - addr = plat_dma_addr_to_phys(dma_address); - dma_cache_wback_inv(addr, size); - } - - plat_unmap_dma_mem(dev, dma_address); -} - -EXPORT_SYMBOL(dma_unmap_page); - void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, enum dma_data_direction direction) { diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c index 8f2cd8eda74..2b1309b2580 100644 --- a/arch/mips/mm/highmem.c +++ b/arch/mips/mm/highmem.c @@ -1,7 +1,12 @@ #include <linux/module.h> #include <linux/highmem.h> +#include <asm/fixmap.h> #include <asm/tlbflush.h> +static pte_t *kmap_pte; + +unsigned long highstart_pfn, highend_pfn; + void *__kmap(struct page *page) { void *addr; @@ -14,15 +19,16 @@ void *__kmap(struct page *page) return addr; } +EXPORT_SYMBOL(__kmap); void __kunmap(struct page *page) { - if (in_interrupt()) - BUG(); + BUG_ON(in_interrupt()); if (!PageHighMem(page)) return; kunmap_high(page); } +EXPORT_SYMBOL(__kunmap); /* * kmap_atomic/kunmap_atomic is significantly faster than kmap/kunmap because @@ -43,17 +49,18 @@ void *__kmap_atomic(struct page *page, enum km_type type) if (!PageHighMem(page)) return page_address(page); + debug_kmap_atomic(type); idx = type + KM_TYPE_NR*smp_processor_id(); vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); #ifdef CONFIG_DEBUG_HIGHMEM - if (!pte_none(*(kmap_pte-idx))) - BUG(); + BUG_ON(!pte_none(*(kmap_pte - idx))); #endif - set_pte(kmap_pte-idx, mk_pte(page, kmap_prot)); + set_pte(kmap_pte-idx, mk_pte(page, PAGE_KERNEL)); local_flush_tlb_one((unsigned long)vaddr); return (void*) vaddr; } +EXPORT_SYMBOL(__kmap_atomic); void __kunmap_atomic(void *kvaddr, enum km_type type) { @@ -66,8 +73,7 @@ void __kunmap_atomic(void *kvaddr, enum km_type type) return; } - if (vaddr != __fix_to_virt(FIX_KMAP_BEGIN+idx)) - BUG(); + BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx)); /* * force other mappings to Oops if they'll try to access @@ -79,6 +85,7 @@ void __kunmap_atomic(void *kvaddr, enum km_type type) pagefault_enable(); } +EXPORT_SYMBOL(__kunmap_atomic); /* * This is the same as kmap_atomic() but can map memory that doesn't @@ -91,9 +98,10 @@ void *kmap_atomic_pfn(unsigned long pfn, enum km_type type) pagefault_disable(); + debug_kmap_atomic(type); idx = type + KM_TYPE_NR*smp_processor_id(); vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); - set_pte(kmap_pte-idx, pfn_pte(pfn, kmap_prot)); + set_pte(kmap_pte-idx, pfn_pte(pfn, PAGE_KERNEL)); flush_tlb_one(vaddr); return (void*) vaddr; @@ -112,7 +120,11 @@ struct page *__kmap_atomic_to_page(void *ptr) return pte_page(*pte); } -EXPORT_SYMBOL(__kmap); -EXPORT_SYMBOL(__kunmap); -EXPORT_SYMBOL(__kmap_atomic); -EXPORT_SYMBOL(__kunmap_atomic); +void __init kmap_init(void) +{ + unsigned long kmap_vstart; + + /* cache the first kmap pte */ + kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN); + kmap_pte = kmap_get_fixmap_pte(kmap_vstart); +} diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 137c14bafd6..c5511294a9e 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -104,14 +104,6 @@ unsigned long setup_zero_pages(void) return 1UL << order; } -/* - * These are almost like kmap_atomic / kunmap_atmic except they take an - * additional address argument as the hint. - */ - -#define kmap_get_fixmap_pte(vaddr) \ - pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr)) - #ifdef CONFIG_MIPS_MT_SMTC static pte_t *kmap_coherent_pte; static void __init kmap_coherent_init(void) @@ -264,24 +256,6 @@ void copy_from_user_page(struct vm_area_struct *vma, } } -#ifdef CONFIG_HIGHMEM -unsigned long highstart_pfn, highend_pfn; - -pte_t *kmap_pte; -pgprot_t kmap_prot; - -static void __init kmap_init(void) -{ - unsigned long kmap_vstart; - - /* cache the first kmap pte */ - kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN); - kmap_pte = kmap_get_fixmap_pte(kmap_vstart); - - kmap_prot = PAGE_KERNEL; -} -#endif /* CONFIG_HIGHMEM */ - void __init fixrange_init(unsigned long start, unsigned long end, pgd_t *pgd_base) { @@ -307,8 +281,7 @@ void __init fixrange_init(unsigned long start, unsigned long end, if (pmd_none(*pmd)) { pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE); set_pmd(pmd, __pmd((unsigned long)pte)); - if (pte != pte_offset_kernel(pmd, 0)) - BUG(); + BUG_ON(pte != pte_offset_kernel(pmd, 0)); } vaddr += PMD_SIZE; } diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c index 59945b9ee23..0c43248347b 100644 --- a/arch/mips/mm/ioremap.c +++ b/arch/mips/mm/ioremap.c @@ -27,8 +27,7 @@ static inline void remap_area_pte(pte_t * pte, unsigned long address, end = address + size; if (end > PMD_SIZE) end = PMD_SIZE; - if (address >= end) - BUG(); + BUG_ON(address >= end); pfn = phys_addr >> PAGE_SHIFT; do { if (!pte_none(*pte)) { @@ -52,8 +51,7 @@ static inline int remap_area_pmd(pmd_t * pmd, unsigned long address, if (end > PGDIR_SIZE) end = PGDIR_SIZE; phys_addr -= address; - if (address >= end) - BUG(); + BUG_ON(address >= end); do { pte_t * pte = pte_alloc_kernel(pmd, address); if (!pte) @@ -75,8 +73,7 @@ static int remap_area_pages(unsigned long address, phys_t phys_addr, phys_addr -= address; dir = pgd_offset(&init_mm, address); flush_cache_all(); - if (address >= end) - BUG(); + BUG_ON(address >= end); do { pud_t *pud; pmd_t *pmd; diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c index e3abfb2d7e8..de69bfbf506 100644 --- a/arch/mips/mm/sc-rm7k.c +++ b/arch/mips/mm/sc-rm7k.c @@ -29,7 +29,7 @@ extern unsigned long icache_way_size, dcache_way_size; #include <asm/r4kcache.h> -int rm7k_tcache_enabled; +static int rm7k_tcache_enabled; /* * Writeback and invalidate the primary cache dcache before DMA. @@ -121,7 +121,7 @@ static void rm7k_sc_disable(void) clear_c0_config(RM7K_CONF_SE); } -struct bcache_ops rm7k_sc_ops = { +static struct bcache_ops rm7k_sc_ops = { .bc_enable = rm7k_sc_enable, .bc_disable = rm7k_sc_disable, .bc_wback_inv = rm7k_sc_wback_inv, diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c index f0cf46adb97..1c0048a6f5c 100644 --- a/arch/mips/mm/tlb-r3k.c +++ b/arch/mips/mm/tlb-r3k.c @@ -82,8 +82,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, int cpu = smp_processor_id(); if (cpu_context(cpu, mm) != 0) { - unsigned long flags; - int size; + unsigned long size, flags; #ifdef DEBUG_TLB printk("[tlbrange<%lu,0x%08lx,0x%08lx>]", @@ -121,8 +120,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) { - unsigned long flags; - int size; + unsigned long size, flags; #ifdef DEBUG_TLB printk("[tlbrange<%lu,0x%08lx,0x%08lx>]", start, end); diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 9619f66e531..892be426787 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -117,8 +117,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, int cpu = smp_processor_id(); if (cpu_context(cpu, mm) != 0) { - unsigned long flags; - int size; + unsigned long size, flags; ENTER_CRITICAL(flags); size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; @@ -160,8 +159,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) { - unsigned long flags; - int size; + unsigned long size, flags; ENTER_CRITICAL(flags); size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c index 4f01a3be215..4ec95cc2df2 100644 --- a/arch/mips/mm/tlb-r8k.c +++ b/arch/mips/mm/tlb-r8k.c @@ -111,8 +111,7 @@ out_restore: /* Usable for KV1 addresses only! */ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) { - unsigned long flags; - int size; + unsigned long size, flags; size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; size = (size + 1) >> 1; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index f335cf6cdd7..0615b62efd6 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -292,13 +292,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_R4300: case CPU_5KC: case CPU_TX49XX: - case CPU_AU1000: - case CPU_AU1100: - case CPU_AU1500: - case CPU_AU1550: - case CPU_AU1200: - case CPU_AU1210: - case CPU_AU1250: case CPU_PR4450: uasm_i_nop(p); tlbw(p); @@ -321,6 +314,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_R5500: if (m4kc_tlbp_war()) uasm_i_nop(p); + case CPU_ALCHEMY: tlbw(p); break; diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c index 4832af25166..475038a141a 100644 --- a/arch/mips/mti-malta/malta-init.c +++ b/arch/mips/mti-malta/malta-init.c @@ -48,7 +48,7 @@ int *_prom_argv, *_prom_envp; int init_debug = 0; -int mips_revision_corid; +static int mips_revision_corid; int mips_revision_sconid; /* Bonito64 system controller register base. */ diff --git a/arch/mips/mti-malta/malta-smtc.c b/arch/mips/mti-malta/malta-smtc.c index aabd7274507..5ba31888fef 100644 --- a/arch/mips/mti-malta/malta-smtc.c +++ b/arch/mips/mti-malta/malta-smtc.c @@ -116,7 +116,7 @@ struct plat_smp_ops msmtc_smp_ops = { void plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity) { - cpumask_t tmask = *affinity; + cpumask_t tmask; int cpu = 0; void smtc_set_irq_affinity(unsigned int irq, cpumask_t aff); @@ -139,11 +139,12 @@ void plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity) * be made to forward to an offline "CPU". */ + cpumask_copy(&tmask, affinity); for_each_cpu(cpu, affinity) { if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu)) cpu_clear(cpu, tmask); } - irq_desc[irq].affinity = tmask; + cpumask_copy(irq_desc[irq].affinity, &tmask); if (cpus_empty(tmask)) /* diff --git a/arch/mips/nxp/pnx833x/common/platform.c b/arch/mips/nxp/pnx833x/common/platform.c index b1ccbcc18f7..01f8345a206 100644 --- a/arch/mips/nxp/pnx833x/common/platform.c +++ b/arch/mips/nxp/pnx833x/common/platform.c @@ -42,7 +42,7 @@ #include <irq-mapping.h> #include <pnx833x.h> -static u64 uart_dmamask = DMA_32BIT_MASK; +static u64 uart_dmamask = DMA_BIT_MASK(32); static struct resource pnx833x_uart_resources[] = { [0] = { @@ -101,14 +101,14 @@ static struct platform_device pnx833x_uart_device = { .id = -1, .dev = { .dma_mask = &uart_dmamask, - .coherent_dma_mask = DMA_32BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = pnx8xxx_ports, }, .num_resources = ARRAY_SIZE(pnx833x_uart_resources), .resource = pnx833x_uart_resources, }; -static u64 ehci_dmamask = DMA_32BIT_MASK; +static u64 ehci_dmamask = DMA_BIT_MASK(32); static struct resource pnx833x_usb_ehci_resources[] = { [0] = { @@ -128,7 +128,7 @@ static struct platform_device pnx833x_usb_ehci_device = { .id = -1, .dev = { .dma_mask = &ehci_dmamask, - .coherent_dma_mask = DMA_32BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(pnx833x_usb_ehci_resources), .resource = pnx833x_usb_ehci_resources, @@ -198,7 +198,7 @@ static struct platform_device pnx833x_i2c1_device = { }; #endif -static u64 ethernet_dmamask = DMA_32BIT_MASK; +static u64 ethernet_dmamask = DMA_BIT_MASK(32); static struct resource pnx833x_ethernet_resources[] = { [0] = { @@ -218,7 +218,7 @@ static struct platform_device pnx833x_ethernet_device = { .id = -1, .dev = { .dma_mask = ðernet_dmamask, - .coherent_dma_mask = DMA_32BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(pnx833x_ethernet_resources), .resource = pnx833x_ethernet_resources, diff --git a/arch/mips/nxp/pnx8550/common/platform.c b/arch/mips/nxp/pnx8550/common/platform.c index 21d2955359b..5264cc09a27 100644 --- a/arch/mips/nxp/pnx8550/common/platform.c +++ b/arch/mips/nxp/pnx8550/common/platform.c @@ -92,16 +92,16 @@ struct pnx8xxx_port pnx8xxx_ports[] = { }; /* The dmamask must be set for OHCI to work */ -static u64 ohci_dmamask = DMA_32BIT_MASK; +static u64 ohci_dmamask = DMA_BIT_MASK(32); -static u64 uart_dmamask = DMA_32BIT_MASK; +static u64 uart_dmamask = DMA_BIT_MASK(32); static struct platform_device pnx8550_usb_ohci_device = { .name = "pnx8550-ohci", .id = -1, .dev = { .dma_mask = &ohci_dmamask, - .coherent_dma_mask = DMA_32BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(pnx8550_usb_ohci_resources), .resource = pnx8550_usb_ohci_resources, @@ -112,7 +112,7 @@ static struct platform_device pnx8550_uart_device = { .id = -1, .dev = { .dma_mask = &uart_dmamask, - .coherent_dma_mask = DMA_32BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = pnx8xxx_ports, }, .num_resources = ARRAY_SIZE(pnx8550_uart_resources), diff --git a/arch/mips/nxp/pnx8550/common/time.c b/arch/mips/nxp/pnx8550/common/time.c index cf293b27909..8df43e9e4d9 100644 --- a/arch/mips/nxp/pnx8550/common/time.c +++ b/arch/mips/nxp/pnx8550/common/time.c @@ -35,7 +35,7 @@ static unsigned long cpj; -static cycle_t hpt_read(void) +static cycle_t hpt_read(struct clocksource *cs) { return read_c0_count2(); } diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig index 90261b83db0..c139988bb85 100644 --- a/arch/mips/pmc-sierra/Kconfig +++ b/arch/mips/pmc-sierra/Kconfig @@ -36,18 +36,6 @@ config PMC_MSP7120_FPGA endchoice -menu "Options for PMC-Sierra MSP chipsets" - depends on PMC_MSP - -config PMC_MSP_EMBEDDED_ROOTFS - bool "Root filesystem embedded in kernel image" - select MTD - select MTD_BLOCK - select MTD_PMC_MSP_RAMROOT - select MTD_RAM - -endmenu - config HYPERTRANSPORT bool "Hypertransport Support for PMC-Sierra Yosemite" depends on PMC_YOSEMITE diff --git a/arch/mips/pmc-sierra/msp71xx/msp_prom.c b/arch/mips/pmc-sierra/msp71xx/msp_prom.c index e5bd5481d8d..c317a3623ce 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_prom.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_prom.c @@ -40,12 +40,6 @@ #include <linux/string.h> #include <linux/interrupt.h> #include <linux/mm.h> -#ifdef CONFIG_CRAMFS -#include <linux/cramfs_fs.h> -#endif -#ifdef CONFIG_SQUASHFS -#include <linux/squashfs_fs.h> -#endif #include <asm/addrspace.h> #include <asm/bootinfo.h> @@ -435,10 +429,6 @@ struct prom_pmemblock *__init prom_getmdesc(void) char *str; unsigned int memsize; unsigned int heaptop; -#ifdef CONFIG_MTD_PMC_MSP_RAMROOT - void *ramroot_start; - unsigned long ramroot_size; -#endif int i; str = prom_getenv(memsz_env); @@ -506,19 +496,7 @@ struct prom_pmemblock *__init prom_getmdesc(void) i++; /* 3 */ mdesc[i].type = BOOT_MEM_RESERVED; mdesc[i].base = CPHYSADDR((u32)_text); -#ifdef CONFIG_MTD_PMC_MSP_RAMROOT - if (get_ramroot(&ramroot_start, &ramroot_size)) { - /* - * Rootfs in RAM -- follows kernel - * Combine rootfs image with kernel block so a - * page (4k) isn't wasted between memory blocks - */ - mdesc[i].size = CPHYSADDR(PAGE_ALIGN( - (u32)ramroot_start + ramroot_size)) - mdesc[i].base; - } else -#endif - mdesc[i].size = CPHYSADDR(PAGE_ALIGN( - (u32)_end)) - mdesc[i].base; + mdesc[i].size = CPHYSADDR(PAGE_ALIGN((u32)_end)) - mdesc[i].base; /* Remainder of RAM -- under memsize */ i++; /* 5 */ @@ -528,39 +506,3 @@ struct prom_pmemblock *__init prom_getmdesc(void) return &mdesc[0]; } - -/* rootfs functions */ -#ifdef CONFIG_MTD_PMC_MSP_RAMROOT -bool get_ramroot(void **start, unsigned long *size) -{ - extern char _end[]; - - /* Check for start following the end of the kernel */ - void *check_start = (void *)_end; - - /* Check for supported rootfs types */ -#ifdef CONFIG_CRAMFS - if (*(__u32 *)check_start == CRAMFS_MAGIC) { - /* Get CRAMFS size */ - *start = check_start; - *size = PAGE_ALIGN(((struct cramfs_super *) - check_start)->size); - - return true; - } -#endif -#ifdef CONFIG_SQUASHFS - if (*((unsigned int *)check_start) == SQUASHFS_MAGIC) { - /* Get SQUASHFS size */ - *start = check_start; - *size = PAGE_ALIGN(((struct squashfs_super_block *) - check_start)->bytes_used); - - return true; - } -#endif - - return false; -} -EXPORT_SYMBOL(get_ramroot); -#endif diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c index c93675615f5..a54e85b3cf2 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c @@ -21,7 +21,6 @@ #if defined(CONFIG_PMC_MSP7120_GW) #include <msp_regops.h> -#include <msp_gpio.h> #define MSP_BOARD_RESET_GPIO 9 #endif @@ -88,11 +87,8 @@ void msp7120_reset(void) * as GPIO char driver may not be enabled and it would look up * data inRAM! */ - set_value_reg32(GPIO_CFG3_REG, - basic_mode_mask(MSP_BOARD_RESET_GPIO), - basic_mode(MSP_GPIO_OUTPUT, MSP_BOARD_RESET_GPIO)); - set_reg32(GPIO_DATA3_REG, - basic_data_mask(MSP_BOARD_RESET_GPIO)); + set_value_reg32(GPIO_CFG3_REG, 0xf000, 0x8000); + set_reg32(GPIO_DATA3_REG, 8); /* * In case GPIO9 doesn't reset the board (jumper configurable!) diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c index 7cfeda5a651..cca64e15f57 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_time.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c @@ -81,10 +81,7 @@ void __init plat_time_init(void) mips_hpt_frequency = cpu_rate/2; } -void __init plat_timer_setup(struct irqaction *irq) +unsigned int __init get_c0_compare_int(void) { -#ifdef CONFIG_IRQ_MSP_CIC - /* we are using the vpe0 counter for timer interrupts */ - setup_irq(MSP_INT_VPE0_TIMER, irq); -#endif + return MSP_INT_VPE0_TIMER; } diff --git a/arch/mips/pmc-sierra/msp71xx/msp_usb.c b/arch/mips/pmc-sierra/msp71xx/msp_usb.c index f7ca4f58233..0ee01e359dd 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_usb.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_usb.c @@ -49,14 +49,14 @@ static struct resource msp_usbhost_resources [] = { }, }; -static u64 msp_usbhost_dma_mask = DMA_32BIT_MASK; +static u64 msp_usbhost_dma_mask = DMA_BIT_MASK(32); static struct platform_device msp_usbhost_device = { .name = "pmcmsp-ehci", .id = 0, .dev = { .dma_mask = &msp_usbhost_dma_mask, - .coherent_dma_mask = DMA_32BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(msp_usbhost_resources), .resource = msp_usbhost_resources, @@ -77,14 +77,14 @@ static struct resource msp_usbdev_resources [] = { }, }; -static u64 msp_usbdev_dma_mask = DMA_32BIT_MASK; +static u64 msp_usbdev_dma_mask = DMA_BIT_MASK(32); static struct platform_device msp_usbdev_device = { .name = "msp71xx_udc", .id = 0, .dev = { .dma_mask = &msp_usbdev_dma_mask, - .coherent_dma_mask = DMA_32BIT_MASK, + .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(msp_usbdev_resources), .resource = msp_usbdev_resources, diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c index 4a5f05b662a..9f40e1ff9b4 100644 --- a/arch/mips/rb532/devices.c +++ b/arch/mips/rb532/devices.c @@ -200,26 +200,9 @@ static struct platform_device rb532_led = { .id = -1, }; -static struct gpio_keys_button rb532_gpio_btn[] = { - { - .gpio = 1, - .code = BTN_0, - .desc = "S1", - .active_low = 1, - } -}; - -static struct gpio_keys_platform_data rb532_gpio_btn_data = { - .buttons = rb532_gpio_btn, - .nbuttons = ARRAY_SIZE(rb532_gpio_btn), -}; - static struct platform_device rb532_button = { - .name = "gpio-keys", + .name = "rb532-button", .id = -1, - .dev = { - .platform_data = &rb532_gpio_btn_data, - } }; static struct resource rb532_wdt_res[] = { diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index f8b18af141a..0ecd5fe9486 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c @@ -155,7 +155,7 @@ static void indy_buserror_irq(void) int irq = SGI_BUSERR_IRQ; irq_enter(); - kstat_this_cpu.irqs[irq]++; + kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); ip22_be_interrupt(irq); irq_exit(); } diff --git a/arch/mips/sgi-ip22/ip22-reset.c b/arch/mips/sgi-ip22/ip22-reset.c index 4ad5c3393fd..45b6694c207 100644 --- a/arch/mips/sgi-ip22/ip22-reset.c +++ b/arch/mips/sgi-ip22/ip22-reset.c @@ -148,7 +148,7 @@ static irqreturn_t panel_int(int irq, void *dev_id) if (sgint->istat1 & SGINT_ISTAT1_PWR) { /* Wait until interrupt goes away */ - disable_irq(SGI_PANEL_IRQ); + disable_irq_nosync(SGI_PANEL_IRQ); init_timer(&debounce_timer); debounce_timer.function = debounce; debounce_timer.expires = jiffies + 5; diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c index 3dcb27ec0c5..c8f7d2328b2 100644 --- a/arch/mips/sgi-ip22/ip22-time.c +++ b/arch/mips/sgi-ip22/ip22-time.c @@ -122,7 +122,7 @@ void indy_8254timer_irq(void) char c; irq_enter(); - kstat_this_cpu.irqs[irq]++; + kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); printk(KERN_ALERT "Oops, got 8254 interrupt.\n"); ArcRead(0, &c, 1, &cnt); ArcEnterInteractiveMode(); diff --git a/arch/mips/sgi-ip27/ip27-berr.c b/arch/mips/sgi-ip27/ip27-berr.c index 7d05e68fdc7..04cebadc2b3 100644 --- a/arch/mips/sgi-ip27/ip27-berr.c +++ b/arch/mips/sgi-ip27/ip27-berr.c @@ -66,7 +66,7 @@ int ip27_be_handler(struct pt_regs *regs, int is_fixup) printk("Slice %c got %cbe at 0x%lx\n", 'A' + cpu, data ? 'd' : 'i', regs->cp0_epc); printk("Hub information:\n"); - printk("ERR_INT_PEND = 0x%06lx\n", LOCAL_HUB_L(PI_ERR_INT_PEND)); + printk("ERR_INT_PEND = 0x%06llx\n", LOCAL_HUB_L(PI_ERR_INT_PEND)); errst0 = LOCAL_HUB_L(cpu ? PI_ERR_STATUS0_B : PI_ERR_STATUS0_A); errst1 = LOCAL_HUB_L(cpu ? PI_ERR_STATUS1_B : PI_ERR_STATUS1_A); dump_hub_information(errst0, errst1); diff --git a/arch/mips/sgi-ip27/ip27-nmi.c b/arch/mips/sgi-ip27/ip27-nmi.c index 64459e7d891..6c5a630566f 100644 --- a/arch/mips/sgi-ip27/ip27-nmi.c +++ b/arch/mips/sgi-ip27/ip27-nmi.c @@ -143,8 +143,8 @@ void nmi_dump_hub_irq(nasid_t nasid, int slice) pend0 = REMOTE_HUB_L(nasid, PI_INT_PEND0); pend1 = REMOTE_HUB_L(nasid, PI_INT_PEND1); - printk("PI_INT_MASK0: %16lx PI_INT_MASK1: %16lx\n", mask0, mask1); - printk("PI_INT_PEND0: %16lx PI_INT_PEND1: %16lx\n", pend0, pend1); + printk("PI_INT_MASK0: %16Lx PI_INT_MASK1: %16Lx\n", mask0, mask1); + printk("PI_INT_PEND0: %16Lx PI_INT_PEND1: %16Lx\n", pend0, pend1); printk("\n\n"); } @@ -219,7 +219,7 @@ cont_nmi_dump(void) if (i == 1000) { for_each_online_node(node) if (NODEPDA(node)->dump_count == 0) { - cpu = node_to_first_cpu(node); + cpu = cpumask_first(cpumask_of_node(node)); for (n=0; n < CNODE_NUM_CPUS(node); cpu++, n++) { CPUMASK_SETB(nmied_cpus, cpu); /* diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c index 5b47d6b6527..cbcd7eb83bd 100644 --- a/arch/mips/sgi-ip27/ip27-smp.c +++ b/arch/mips/sgi-ip27/ip27-smp.c @@ -221,7 +221,7 @@ static void __init ip27_smp_setup(void) * Assumption to be fixed: we're always booted on logical / physical * processor 0. While we're always running on logical processor 0 * this still means this is physical processor zero; it might for - * example be disabled in the firwware. + * example be disabled in the firmware. */ alloc_cpupda(0, 0); } diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index f024057a35f..f10a7cd64f7 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -159,7 +159,7 @@ static void __init hub_rt_clock_event_global_init(void) setup_irq(irq, &hub_rt_irqaction); } -static cycle_t hub_rt_read(void) +static cycle_t hub_rt_read(struct clocksource *cs) { return REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT); } diff --git a/arch/mips/sgi-ip32/ip32-berr.c b/arch/mips/sgi-ip32/ip32-berr.c index a278e918a01..afc1cadbba3 100644 --- a/arch/mips/sgi-ip32/ip32-berr.c +++ b/arch/mips/sgi-ip32/ip32-berr.c @@ -16,7 +16,7 @@ #include <asm/ptrace.h> #include <asm/tlbdebug.h> -int ip32_be_handler(struct pt_regs *regs, int is_fixup) +static int ip32_be_handler(struct pt_regs *regs, int is_fixup) { int data = regs->cp0_cause & 4; diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index 0d6b6663d5f..5c2bf111ca6 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c @@ -112,17 +112,15 @@ static void inline flush_mace_bus(void) extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); -struct irqaction memerr_irq = { +static struct irqaction memerr_irq = { .handler = crime_memerr_intr, .flags = IRQF_DISABLED, - .mask = CPU_MASK_NONE, .name = "CRIME memory error", }; -struct irqaction cpuerr_irq = { +static struct irqaction cpuerr_irq = { .handler = crime_cpuerr_intr, .flags = IRQF_DISABLED, - .mask = CPU_MASK_NONE, .name = "CRIME CPU error", }; @@ -325,16 +323,11 @@ static void mask_and_ack_maceisa_irq(unsigned int irq) { unsigned long mace_int; - switch (irq) { - case MACEISA_PARALLEL_IRQ: - case MACEISA_SERIAL1_TDMAPR_IRQ: - case MACEISA_SERIAL2_TDMAPR_IRQ: - /* edge triggered */ - mace_int = mace->perif.ctrl.istat; - mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ)); - mace->perif.ctrl.istat = mace_int; - break; - } + /* edge triggered */ + mace_int = mace->perif.ctrl.istat; + mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ)); + mace->perif.ctrl.istat = mace_int; + disable_maceisa_irq(irq); } @@ -344,7 +337,16 @@ static void end_maceisa_irq(unsigned irq) enable_maceisa_irq(irq); } -static struct irq_chip ip32_maceisa_interrupt = { +static struct irq_chip ip32_maceisa_level_interrupt = { + .name = "IP32 MACE ISA", + .ack = disable_maceisa_irq, + .mask = disable_maceisa_irq, + .mask_ack = disable_maceisa_irq, + .unmask = enable_maceisa_irq, + .end = end_maceisa_irq, +}; + +static struct irq_chip ip32_maceisa_edge_interrupt = { .name = "IP32 MACE ISA", .ack = mask_and_ack_maceisa_irq, .mask = disable_maceisa_irq, @@ -500,27 +502,50 @@ void __init arch_init_irq(void) for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) { switch (irq) { case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: - set_irq_chip(irq, &ip32_mace_interrupt); + set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt, + handle_level_irq, "level"); break; + case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ: - set_irq_chip(irq, &ip32_macepci_interrupt); + set_irq_chip_and_handler_name(irq, + &ip32_macepci_interrupt, handle_level_irq, + "level"); break; + case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ: - set_irq_chip(irq, &crime_edge_interrupt); + set_irq_chip_and_handler_name(irq, + &crime_edge_interrupt, handle_edge_irq, "edge"); break; case CRIME_CPUERR_IRQ: case CRIME_MEMERR_IRQ: - set_irq_chip(irq, &crime_level_interrupt); + set_irq_chip_and_handler_name(irq, + &crime_level_interrupt, handle_level_irq, + "level"); break; + case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ: case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ: - set_irq_chip(irq, &crime_edge_interrupt); + set_irq_chip_and_handler_name(irq, + &crime_edge_interrupt, handle_edge_irq, "edge"); break; + case CRIME_VICE_IRQ: - set_irq_chip(irq, &crime_edge_interrupt); + set_irq_chip_and_handler_name(irq, + &crime_edge_interrupt, handle_edge_irq, "edge"); + break; + + case MACEISA_PARALLEL_IRQ: + case MACEISA_SERIAL1_TDMAPR_IRQ: + case MACEISA_SERIAL2_TDMAPR_IRQ: + set_irq_chip_and_handler_name(irq, + &ip32_maceisa_edge_interrupt, handle_edge_irq, + "edge"); break; + default: - set_irq_chip(irq, &ip32_maceisa_interrupt); + set_irq_chip_and_handler_name(irq, + &ip32_maceisa_level_interrupt, handle_level_irq, + "level"); break; } } diff --git a/arch/mips/sgi-ip32/ip32-memory.c b/arch/mips/sgi-ip32/ip32-memory.c index ca93ecf825a..828ce131c22 100644 --- a/arch/mips/sgi-ip32/ip32-memory.c +++ b/arch/mips/sgi-ip32/ip32-memory.c @@ -36,7 +36,7 @@ void __init prom_meminit(void) if (base + size > (256 << 20)) base += CRIME_HI_MEM_BASE; - printk("CRIME MC: bank %u base 0x%016lx size %luMiB\n", + printk("CRIME MC: bank %u base 0x%016Lx size %LuMiB\n", bank, base, size >> 20); add_memory_region(base, size, BOOT_MEM_RAM); } diff --git a/arch/mips/sgi-ip32/ip32-reset.c b/arch/mips/sgi-ip32/ip32-reset.c index b6cab089561..9b95d80ebc6 100644 --- a/arch/mips/sgi-ip32/ip32-reset.c +++ b/arch/mips/sgi-ip32/ip32-reset.c @@ -53,7 +53,7 @@ static inline void ip32_machine_halt(void) static void ip32_machine_power_off(void) { - volatile unsigned char reg_a, xctrl_a, xctrl_b; + unsigned char reg_a, xctrl_a, xctrl_b; disable_irq(MACEISA_RTC_IRQ); reg_a = CMOS_READ(RTC_REG_A); @@ -91,9 +91,10 @@ static void blink_timeout(unsigned long data) static void debounce(unsigned long data) { - volatile unsigned char reg_a, reg_c, xctrl_a; + unsigned char reg_a, reg_c, xctrl_a; reg_c = CMOS_READ(RTC_INTR_FLAGS); + reg_a = CMOS_READ(RTC_REG_A); CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A); wbflush(); xctrl_a = CMOS_READ(DS_B1_XCTRL4A); @@ -137,7 +138,7 @@ static inline void ip32_power_button(void) static irqreturn_t ip32_rtc_int(int irq, void *dev_id) { - volatile unsigned char reg_c; + unsigned char reg_c; reg_c = CMOS_READ(RTC_INTR_FLAGS); if (!(reg_c & RTC_IRQF)) { @@ -145,7 +146,7 @@ static irqreturn_t ip32_rtc_int(int irq, void *dev_id) "%s: RTC IRQ without RTC_IRQF\n", __func__); } /* Wait until interrupt goes away */ - disable_irq(MACEISA_RTC_IRQ); + disable_irq_nosync(MACEISA_RTC_IRQ); init_timer(&debounce_timer); debounce_timer.function = debounce; debounce_timer.expires = jiffies + 50; diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c index 12b465d404d..c147c4b35d3 100644 --- a/arch/mips/sibyte/bcm1480/irq.c +++ b/arch/mips/sibyte/bcm1480/irq.c @@ -113,7 +113,6 @@ static void bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask) { int i = 0, old_cpu, cpu, int_on, k; u64 cur_ints; - struct irq_desc *desc = irq_desc + irq; unsigned long flags; unsigned int irq_dirty; @@ -127,8 +126,7 @@ static void bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask) cpu = cpu_logical_map(i); /* Protect against other affinity changers and IMR manipulation */ - spin_lock_irqsave(&desc->lock, flags); - spin_lock(&bcm1480_imr_lock); + spin_lock_irqsave(&bcm1480_imr_lock, flags); /* Swizzle each CPU's IMR (but leave the IP selection alone) */ old_cpu = bcm1480_irq_owner[irq]; @@ -153,8 +151,7 @@ static void bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask) ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); } } - spin_unlock(&bcm1480_imr_lock); - spin_unlock_irqrestore(&desc->lock, flags); + spin_unlock_irqrestore(&bcm1480_imr_lock, flags); } #endif @@ -236,7 +233,7 @@ void __init init_bcm1480_irqs(void) int i; for (i = 0; i < BCM1480_NR_IRQS; i++) { - set_irq_chip(i, &bcm1480_irq_type); + set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq); bcm1480_irq_owner[i] = 0; } } diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c index dddfda8e829..314691648c9 100644 --- a/arch/mips/sibyte/bcm1480/smp.c +++ b/arch/mips/sibyte/bcm1480/smp.c @@ -178,9 +178,10 @@ struct plat_smp_ops bcm1480_smp_ops = { void bcm1480_mailbox_interrupt(void) { int cpu = smp_processor_id(); + int irq = K_BCM1480_INT_MBOX_0_0; unsigned int action; - kstat_this_cpu.irqs[K_BCM1480_INT_MBOX_0_0]++; + kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); /* Load the mailbox register to figure out what we're supposed to do */ action = (__raw_readq(mailbox_0_regs[cpu]) >> 48) & 0xffff; diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c index 3de30f79db3..eb5396cf81b 100644 --- a/arch/mips/sibyte/cfe/setup.c +++ b/arch/mips/sibyte/cfe/setup.c @@ -288,13 +288,7 @@ void __init prom_init(void) */ cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE); if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, CL_SIZE) < 0) { - if (argc < 0) { - /* - * It's OK for direct boot to not provide a - * command line - */ - strcpy(arcs_cmdline, "root=/dev/ram0 "); - } else { + if (argc >= 0) { /* The loader should have set the command line */ /* too early for panic to do any good */ printk("LINUX_CMDLINE not defined in cfe."); diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index 808ac2959b8..38cb998ade2 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -107,7 +107,6 @@ static void sb1250_set_affinity(unsigned int irq, const struct cpumask *mask) { int i = 0, old_cpu, cpu, int_on; u64 cur_ints; - struct irq_desc *desc = irq_desc + irq; unsigned long flags; i = cpumask_first(mask); @@ -121,8 +120,7 @@ static void sb1250_set_affinity(unsigned int irq, const struct cpumask *mask) cpu = cpu_logical_map(i); /* Protect against other affinity changers and IMR manipulation */ - spin_lock_irqsave(&desc->lock, flags); - spin_lock(&sb1250_imr_lock); + spin_lock_irqsave(&sb1250_imr_lock, flags); /* Swizzle each CPU's IMR (but leave the IP selection alone) */ old_cpu = sb1250_irq_owner[irq]; @@ -144,8 +142,7 @@ static void sb1250_set_affinity(unsigned int irq, const struct cpumask *mask) ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); } - spin_unlock(&sb1250_imr_lock); - spin_unlock_irqrestore(&desc->lock, flags); + spin_unlock_irqrestore(&sb1250_imr_lock, flags); } #endif @@ -220,7 +217,7 @@ void __init init_sb1250_irqs(void) int i; for (i = 0; i < SB1250_NR_IRQS; i++) { - set_irq_chip(i, &sb1250_irq_type); + set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq); sb1250_irq_owner[i] = 0; } } diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c index 5950a288a7d..cad14003b84 100644 --- a/arch/mips/sibyte/sb1250/smp.c +++ b/arch/mips/sibyte/sb1250/smp.c @@ -166,9 +166,10 @@ struct plat_smp_ops sb_smp_ops = { void sb1250_mailbox_interrupt(void) { int cpu = smp_processor_id(); + int irq = K_INT_MBOX_0; unsigned int action; - kstat_this_cpu.irqs[K_INT_MBOX_0]++; + kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); /* Load the mailbox register to figure out what we're supposed to do */ action = (____raw_readq(mailbox_regs[cpu]) >> 48) & 0xffff; diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c index 3f8cf5eb2f0..7dd76fb3b64 100644 --- a/arch/mips/sni/a20r.c +++ b/arch/mips/sni/a20r.c @@ -219,7 +219,7 @@ void __init sni_a20r_irq_init(void) int i; for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++) - set_irq_chip(i, &a20r_irq_type); + set_irq_chip_and_handler(i, &a20r_irq_type, handle_level_irq); sni_hwint = a20r_hwint; change_c0_status(ST0_IM, IE_IRQ0); setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq); diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c index 834650f371e..74e6c67982f 100644 --- a/arch/mips/sni/pcimt.c +++ b/arch/mips/sni/pcimt.c @@ -304,7 +304,7 @@ void __init sni_pcimt_irq_init(void) mips_cpu_irq_init(); /* Actually we've got more interrupts to handle ... */ for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++) - set_irq_chip(i, &pcimt_irq_type); + set_irq_chip_and_handler(i, &pcimt_irq_type, handle_level_irq); sni_hwint = sni_pcimt_hwint; change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3); } diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c index e5f12cf96e8..071a9573ac7 100644 --- a/arch/mips/sni/pcit.c +++ b/arch/mips/sni/pcit.c @@ -246,7 +246,7 @@ void __init sni_pcit_irq_init(void) mips_cpu_irq_init(); for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) - set_irq_chip(i, &pcit_irq_type); + set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq); *(volatile u32 *)SNI_PCIT_INT_REG = 0; sni_hwint = sni_pcit_hwint; change_c0_status(ST0_IM, IE_IRQ1); @@ -259,7 +259,7 @@ void __init sni_pcit_cplus_irq_init(void) mips_cpu_irq_init(); for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) - set_irq_chip(i, &pcit_irq_type); + set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq); *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; sni_hwint = sni_pcit_hwint_cplus; change_c0_status(ST0_IM, IE_IRQ0); diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c index 5310aa75afa..5e687819cbc 100644 --- a/arch/mips/sni/rm200.c +++ b/arch/mips/sni/rm200.c @@ -359,7 +359,8 @@ void sni_rm200_init_8259A(void) * IRQ2 is cascade interrupt to second interrupt controller */ static struct irqaction sni_rm200_irq2 = { - no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL + .handler = no_action, + .name = "cascade", }; static struct resource sni_rm200_pic1_resource = { @@ -487,7 +488,7 @@ void __init sni_rm200_irq_init(void) mips_cpu_irq_init(); /* Actually we've got more interrupts to handle ... */ for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++) - set_irq_chip(i, &rm200_irq_type); + set_irq_chip_and_handler(i, &rm200_irq_type, handle_level_irq); sni_hwint = sni_rm200_hwint; change_c0_status(ST0_IM, IE_IRQ0); setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq); diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig index 226e8bb2f0a..0db7cf38ed8 100644 --- a/arch/mips/txx9/Kconfig +++ b/arch/mips/txx9/Kconfig @@ -20,7 +20,6 @@ config MACH_TXX9 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_BIG_ENDIAN - select GENERIC_HARDIRQS_NO__DO_IRQ config TOSHIBA_JMR3927 bool "Toshiba JMR-TX3927 board" diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index a13a08b8c9e..8a266c6a3f5 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -32,6 +32,7 @@ #include <asm/txx9/generic.h> #include <asm/txx9/pci.h> #include <asm/txx9tmr.h> +#include <asm/txx9/ndfmc.h> #ifdef CONFIG_CPU_TX49XX #include <asm/txx9/tx4938.h> #endif @@ -691,6 +692,26 @@ void __init txx9_physmap_flash_init(int no, unsigned long addr, #endif } +void __init txx9_ndfmc_init(unsigned long baseaddr, + const struct txx9ndfmc_platform_data *pdata) +{ +#if defined(CONFIG_MTD_NAND_TXX9NDFMC) || \ + defined(CONFIG_MTD_NAND_TXX9NDFMC_MODULE) + struct resource res = { + .start = baseaddr, + .end = baseaddr + 0x1000 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *pdev = platform_device_alloc("txx9ndfmc", -1); + + if (!pdev || + platform_device_add_resources(pdev, &res, 1) || + platform_device_add_data(pdev, pdata, sizeof(*pdata)) || + platform_device_add(pdev)) + platform_device_put(pdev); +#endif +} + #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) static DEFINE_SPINLOCK(txx9_iocled_lock); diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c index 914e93c6263..1093549df1a 100644 --- a/arch/mips/txx9/generic/setup_tx4927.c +++ b/arch/mips/txx9/generic/setup_tx4927.c @@ -88,7 +88,7 @@ void __init tx4927_setup(void) { int i; __u32 divmode; - int cpuclk = 0; + unsigned int cpuclk = 0; u64 ccfg; txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE, diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c index 25819ff1c35..3925219b897 100644 --- a/arch/mips/txx9/generic/setup_tx4938.c +++ b/arch/mips/txx9/generic/setup_tx4938.c @@ -23,6 +23,7 @@ #include <asm/txx9tmr.h> #include <asm/txx9pio.h> #include <asm/txx9/generic.h> +#include <asm/txx9/ndfmc.h> #include <asm/txx9/tx4938.h> static void __init tx4938_wdr_init(void) @@ -92,7 +93,7 @@ void __init tx4938_setup(void) { int i; __u32 divmode; - int cpuclk = 0; + unsigned int cpuclk = 0; u64 ccfg; txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE, @@ -382,6 +383,26 @@ void __init tx4938_ata_init(unsigned int irq, unsigned int shift, int tune) platform_device_put(pdev); } +void __init tx4938_ndfmc_init(unsigned int hold, unsigned int spw) +{ + struct txx9ndfmc_platform_data plat_data = { + .shift = 1, + .gbus_clock = txx9_gbus_clock, + .hold = hold, + .spw = spw, + .ch_mask = 1, + }; + unsigned long baseaddr = TX4938_NDFMC_REG & 0xfffffffffULL; + +#ifdef __BIG_ENDIAN + baseaddr += 4; +#endif + if ((__raw_readq(&tx4938_ccfgptr->pcfg) & + (TX4938_PCFG_ATA_SEL|TX4938_PCFG_ISA_SEL|TX4938_PCFG_NDF_SEL)) == + TX4938_PCFG_NDF_SEL) + txx9_ndfmc_init(baseaddr, &plat_data); +} + static void __init tx4938_stop_unused_modules(void) { __u64 pcfg, rst = 0, ckd = 0; diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c index 55440967b3a..c2bf150c883 100644 --- a/arch/mips/txx9/generic/setup_tx4939.c +++ b/arch/mips/txx9/generic/setup_tx4939.c @@ -27,6 +27,7 @@ #include <asm/txx9irq.h> #include <asm/txx9tmr.h> #include <asm/txx9/generic.h> +#include <asm/txx9/ndfmc.h> #include <asm/txx9/tx4939.h> static void __init tx4939_wdr_init(void) @@ -113,7 +114,7 @@ void __init tx4939_setup(void) int i; __u32 divmode; __u64 pcfg; - int cpuclk = 0; + unsigned int cpuclk = 0; txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE, TX4939_REG_SIZE); @@ -457,6 +458,22 @@ void __init tx4939_rtc_init(void) platform_device_register(&rtc_dev); } +void __init tx4939_ndfmc_init(unsigned int hold, unsigned int spw, + unsigned char ch_mask, unsigned char wide_mask) +{ + struct txx9ndfmc_platform_data plat_data = { + .shift = 1, + .gbus_clock = txx9_gbus_clock, + .hold = hold, + .spw = spw, + .flags = NDFMC_PLAT_FLAG_NO_RSTR | NDFMC_PLAT_FLAG_HOLDADD | + NDFMC_PLAT_FLAG_DUMMYWRITE, + .ch_mask = ch_mask, + .wide_mask = wide_mask, + }; + txx9_ndfmc_init(TX4939_NDFMC_REG & 0xfffffffffULL, &plat_data); +} + static void __init tx4939_stop_unused_modules(void) { __u64 pcfg, rst = 0, ckd = 0; diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c index 547ff2920bf..65d13df8878 100644 --- a/arch/mips/txx9/rbtx4938/setup.c +++ b/arch/mips/txx9/rbtx4938/setup.c @@ -352,6 +352,8 @@ static void __init rbtx4938_device_init(void) rbtx4938_ne_init(); tx4938_wdt_init(); rbtx4938_mtd_init(); + /* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */ + tx4938_ndfmc_init(10, 35); tx4938_ata_init(RBTX4938_IRQ_IOC_ATA, 0, 1); txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL); } diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c index 656603b85b7..4199c6fd4d1 100644 --- a/arch/mips/txx9/rbtx4939/setup.c +++ b/arch/mips/txx9/rbtx4939/setup.c @@ -16,6 +16,9 @@ #include <linux/leds.h> #include <linux/interrupt.h> #include <linux/smc91x.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/mtd/map.h> #include <asm/reboot.h> #include <asm/txx9/generic.h> #include <asm/txx9/pci.h> @@ -282,6 +285,159 @@ static void rbtx4939_7segled_putc(unsigned int pos, unsigned char val) __rbtx4939_7segled_putc(pos, val); } +#if defined(CONFIG_MTD_RBTX4939) || defined(CONFIG_MTD_RBTX4939_MODULE) +/* special mapping for boot rom */ +static unsigned long rbtx4939_flash_fixup_ofs(unsigned long ofs) +{ + u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f; + unsigned char shift; + + if (bdipsw & 8) { + /* BOOT Mode: USER ROM1 / USER ROM2 */ + shift = bdipsw & 3; + /* rotate A[23:22] */ + return (ofs & ~0xc00000) | ((((ofs >> 22) + shift) & 3) << 22); + } +#ifdef __BIG_ENDIAN + if (bdipsw == 0) + /* BOOT Mode: Monitor ROM */ + ofs ^= 0x400000; /* swap A[22] */ +#endif + return ofs; +} + +static map_word rbtx4939_flash_read16(struct map_info *map, unsigned long ofs) +{ + map_word r; + + ofs = rbtx4939_flash_fixup_ofs(ofs); + r.x[0] = __raw_readw(map->virt + ofs); + return r; +} + +static void rbtx4939_flash_write16(struct map_info *map, const map_word datum, + unsigned long ofs) +{ + ofs = rbtx4939_flash_fixup_ofs(ofs); + __raw_writew(datum.x[0], map->virt + ofs); + mb(); /* see inline_map_write() in mtd/map.h */ +} + +static void rbtx4939_flash_copy_from(struct map_info *map, void *to, + unsigned long from, ssize_t len) +{ + u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f; + unsigned char shift; + ssize_t curlen; + + from += (unsigned long)map->virt; + if (bdipsw & 8) { + /* BOOT Mode: USER ROM1 / USER ROM2 */ + shift = bdipsw & 3; + while (len) { + curlen = min_t(unsigned long, len, + 0x400000 - (from & (0x400000 - 1))); + memcpy(to, + (void *)((from & ~0xc00000) | + ((((from >> 22) + shift) & 3) << 22)), + curlen); + len -= curlen; + from += curlen; + to += curlen; + } + return; + } +#ifdef __BIG_ENDIAN + if (bdipsw == 0) { + /* BOOT Mode: Monitor ROM */ + while (len) { + curlen = min_t(unsigned long, len, + 0x400000 - (from & (0x400000 - 1))); + memcpy(to, (void *)(from ^ 0x400000), curlen); + len -= curlen; + from += curlen; + to += curlen; + } + return; + } +#endif + memcpy(to, (void *)from, len); +} + +static void rbtx4939_flash_map_init(struct map_info *map) +{ + map->read = rbtx4939_flash_read16; + map->write = rbtx4939_flash_write16; + map->copy_from = rbtx4939_flash_copy_from; +} + +static void __init rbtx4939_mtd_init(void) +{ + static struct { + struct platform_device dev; + struct resource res; + struct rbtx4939_flash_data data; + } pdevs[4]; + int i; + static char names[4][8]; + static struct mtd_partition parts[4]; + struct rbtx4939_flash_data *boot_pdata = &pdevs[0].data; + u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f; + + if (bdipsw & 8) { + /* BOOT Mode: USER ROM1 / USER ROM2 */ + boot_pdata->nr_parts = 4; + for (i = 0; i < boot_pdata->nr_parts; i++) { + sprintf(names[i], "img%d", 4 - i); + parts[i].name = names[i]; + parts[i].size = 0x400000; + parts[i].offset = MTDPART_OFS_NXTBLK; + } + } else if (bdipsw == 0) { + /* BOOT Mode: Monitor ROM */ + boot_pdata->nr_parts = 2; + strcpy(names[0], "big"); + strcpy(names[1], "little"); + for (i = 0; i < boot_pdata->nr_parts; i++) { + parts[i].name = names[i]; + parts[i].size = 0x400000; + parts[i].offset = MTDPART_OFS_NXTBLK; + } + } else { + /* BOOT Mode: ROM Emulator */ + boot_pdata->nr_parts = 2; + parts[0].name = "boot"; + parts[0].offset = 0xc00000; + parts[0].size = 0x400000; + parts[1].name = "user"; + parts[1].offset = 0; + parts[1].size = 0xc00000; + } + boot_pdata->parts = parts; + boot_pdata->map_init = rbtx4939_flash_map_init; + + for (i = 0; i < ARRAY_SIZE(pdevs); i++) { + struct resource *r = &pdevs[i].res; + struct platform_device *dev = &pdevs[i].dev; + + r->start = 0x1f000000 - i * 0x1000000; + r->end = r->start + 0x1000000 - 1; + r->flags = IORESOURCE_MEM; + pdevs[i].data.width = 2; + dev->num_resources = 1; + dev->resource = r; + dev->id = i; + dev->name = "rbtx4939-flash"; + dev->dev.platform_data = &pdevs[i].data; + platform_device_register(dev); + } +} +#else +static void __init rbtx4939_mtd_init(void) +{ +} +#endif + static void __init rbtx4939_arch_init(void) { rbtx4939_pci_setup(); @@ -333,6 +489,11 @@ static void __init rbtx4939_device_init(void) platform_device_add_data(pdev, &smc_pdata, sizeof(smc_pdata)) || platform_device_add(pdev)) platform_device_put(pdev); + rbtx4939_mtd_init(); + /* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */ + tx4939_ndfmc_init(10, 35, + (1 << 1) | (1 << 2), + (1 << 2)); /* ch1:8bit, ch2:16bit */ rbtx4939_led_setup(); tx4939_wdt_init(); tx4939_ata_init(); @@ -375,7 +536,7 @@ static void __init rbtx4939_setup(void) } struct txx9_board_vec rbtx4939_vec __initdata = { - .system = "Tothiba RBTX4939", + .system = "Toshiba RBTX4939", .prom_init = rbtx4939_prom_init, .mem_setup = rbtx4939_setup, .irq_setup = rbtx4939_irq_setup, diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c index 92dd1a0ca35..9cc389109b1 100644 --- a/arch/mips/vr41xx/common/irq.c +++ b/arch/mips/vr41xx/common/irq.c @@ -32,7 +32,6 @@ static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned; static struct irqaction cascade_irqaction = { .handler = no_action, - .mask = CPU_MASK_NONE, .name = "cascade", }; |