diff options
Diffstat (limited to 'arch/ppc/platforms')
-rw-r--r-- | arch/ppc/platforms/4xx/ebony.c | 2 | ||||
-rw-r--r-- | arch/ppc/platforms/4xx/luan.c | 7 | ||||
-rw-r--r-- | arch/ppc/platforms/4xx/ocotea.c | 2 | ||||
-rw-r--r-- | arch/ppc/platforms/4xx/taishan.c | 2 |
4 files changed, 9 insertions, 4 deletions
diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c index 05d7184d7e1..453643a0eee 100644 --- a/arch/ppc/platforms/4xx/ebony.c +++ b/arch/ppc/platforms/4xx/ebony.c @@ -236,7 +236,7 @@ ebony_early_serial_map(void) gen550_init(0, &port); /* Purge TLB entry added in head_44x.S for early serial access */ - _tlbie(UART0_IO_BASE); + _tlbie(UART0_IO_BASE, 0); #endif port.membase = ioremap64(PPC440GP_UART1_ADDR, 8); diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c index 4b169610f15..b79ebb8a3e6 100644 --- a/arch/ppc/platforms/4xx/luan.c +++ b/arch/ppc/platforms/4xx/luan.c @@ -230,9 +230,14 @@ luan_setup_hoses(void) /* Allocate hoses for PCIX1 and PCIX2 */ hose1 = pcibios_alloc_controller(); + if (!hose1) + return; + hose2 = pcibios_alloc_controller(); - if (!hose1 || !hose2) + if (!hose2) { + pcibios_free_controller(hose1); return; + } /* Setup PCIX1 */ hose1->first_busno = 0; diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c index fd0f971881d..28a712cd480 100644 --- a/arch/ppc/platforms/4xx/ocotea.c +++ b/arch/ppc/platforms/4xx/ocotea.c @@ -259,7 +259,7 @@ ocotea_early_serial_map(void) gen550_init(0, &port); /* Purge TLB entry added in head_44x.S for early serial access */ - _tlbie(UART0_IO_BASE); + _tlbie(UART0_IO_BASE, 0); #endif port.membase = ioremap64(PPC440GX_UART1_ADDR, 8); diff --git a/arch/ppc/platforms/4xx/taishan.c b/arch/ppc/platforms/4xx/taishan.c index 888c492b4a4..f6a0c6650f3 100644 --- a/arch/ppc/platforms/4xx/taishan.c +++ b/arch/ppc/platforms/4xx/taishan.c @@ -316,7 +316,7 @@ taishan_early_serial_map(void) gen550_init(0, &port); /* Purge TLB entry added in head_44x.S for early serial access */ - _tlbie(UART0_IO_BASE); + _tlbie(UART0_IO_BASE, 0); #endif port.membase = ioremap64(PPC440GX_UART1_ADDR, 8); |